Datasheet OP481 Datasheet (ANALOG DEVICES)

Ultralow Power, Rail-to-Rail Output

FEATURES

Low supply current: 4 μA/amplifier maximum Single-supply operation: 2.7 V to 12 V Wide input voltage range Rail-to-rail output swing Low offset voltage: 1.5 mV No phase reversal

APPLICATIONS

Comparator Battery-powered instrumentation Safety monitoring Remote sensors Low voltage strain gage amplifiers

GENERAL DESCRIPTION

The OP281 and OP481 are dual and quad ultralow power single-supply amplifiers featuring rail-to-rail outputs. Each operates from supplies as low as 2.0 V and is specified at +3 V and +5 V single supplies as well as ±5 V dual supplies.

Fabricated on Analog Devices’ CBCMOS process, the OP281/OP481 feature a precision bipolar input and an output that swings to within millivolts of the supplies, continuing to sink or source current up to a voltage equal to the supply voltage.

Applications for these amplifiers include safety monitoring, portable equipment, battery and power supply control, and signal conditioning and interfacing for transducers in very low power systems.

The output’s ability to swing rail-to-rail and not increase supply current when the output is driven to a supply voltage enables the OP281/OP481 to be used as comparators in very low power systems. This is enhanced by their fast saturation recovery time. Propagation delays are 250 μs.

The OP281/OP481 are specified over the extended industrial temperature range (−40°C to +85°C). The OP281 dual amplifier is available in 8-lead SOIC surface-mount and TSSOP packages. The OP481 quad amplifier is available in narrow 14-lead SOIC and TSSOP packages.

Operational Amplifiers

OP281/OP481

PIN CONFIGURATIONS

14

13

12

11

8

7

6

5

14

13

12

11

10

9

8

V+

OUT B

–IN B

+IN B

8

7

6

5

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

V+

OUT B

–IN B

+IN B

00291-001

00291-002

00291-003

00291-004

OUT A

1

V–

OP281

2

TOP VIEW

3

(Not to Scale)

4

–IN A

+IN A

Figure 1. 8-Lead

Narrow-Body SOIC

(R Suffix)

1

OUT A

OP281

2

–IN A

+IN A

V–

TOP VIEW

3

(Not to Scale)

4

Figure 2. 8-Lead TSSOP

(RU Suffix)

1

OUT A

2

–IN A

3

+IN A

+IN B

–IN B

OUT B

OP481

4

V+

TOP VIEW

(Not to Scale)

5 10

6 9

7 8

Figure 3. 14-Lead

Narrow-Body SOIC

(R Suffix)

1

OUT A

2

–IN A

3

+IN A

V+

+IN B

–IN B

OUT B

OP481

TOP VIEW

4

(Not to Scale)

5

6

7

Figure 4. 14-Lead TSSOP

(RU Suffix)

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

OP281/OP481

REVISION HISTORY

9/08—Rev. C to Rev. D

Changes to Figure 40 ...................................................................... 14

Changes to Low-Side Current Monitor Section ......................... 15

Changes to Figure 42 ...................................................................... 15

10/07—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Offset Voltage Drift Condition .................................. 3

Changes to Slew Rate Symbol ......................................................... 5

Changes to Figure 8 .......................................................................... 7

Deleted SPICE Macro-Model Section ......................................... 13

Updated Outline Dimensions ....................................................... 17

Changes to Ordering Guide .......................................................... 18

3/03—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Theory of Operation .................................................................. 13

Input Overvoltage Protection ................................................... 13

Input Offset Voltage ................................................................... 13

Input Common-Mode Voltage Range ..................................... 13

Capacitive Loading ..................................................................... 14

Micropower Reference Voltage Generator .............................. 14

Window Comparator ................................................................. 14

Low-Side Current Monitor ....................................................... 15

Low Voltage Half-Wave and Full-Wave Rectifiers ................. 15

Battery-Powered Telephone Headset Amplifier ..................... 15

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 18

2/03—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Deleted OP181 .................................................................... Universal

Updated Package Options ................................................. Universal

Deleted OP181 Pin Configurations ................................................ 1

Deleted Epoxy DIP Pin Configurations ......................................... 1

Changes to Absolute Maximum Ratings ........................................ 5

Changes to Ordering Guide ............................................................. 5

Changes to Input Offset Voltage ................................................... 10

Deleted Former Figure 33 ............................................................. 10

Deleted Overdrive Recovery Time Section ................................. 11

Deleted Former Figure 36 ............................................................. 11

Deleted 8-Lead and 14-Lead Plastic DIP (N-8 and N-14)

Outline Dimensions ....................................................................... 14

Updated Outline Dimensions ....................................................... 14

Rev. D | Page 2 of 20

OP281/OP481

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Condition Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage

−40°C ≤ TA ≤ +85°C 2.5 mV Input Bias Current IB −40°C ≤ TA ≤ +85°C 3 10 nA Input Offset Current IOS −40°C ≤ TA ≤ +85°C 0.1 7 nA Input Voltage Range 0 2 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.0 V, −40°C ≤ TA ≤ +85°C 65 95 dB Large-Signal Voltage Gain A

−40°C ≤ TA ≤ +85°C 2 V/mV Offset Voltage Drift ΔVOS/∆T −40°C to +85°C 10 μV/°C Bias Current Drift ΔIB/ΔT 20 pA/°C Offset Current Drift ΔIOS/ΔT 2 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 100 kΩ to GND, −40°C ≤ TA ≤ +85°C 2.925 2.96 V Output Voltage Low VOL RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C 25 75 mV Short-Circuit Limit ISC ±1.1 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C 76 95 dB Supply Current/Amplifier ISY VO = 0 V 3 4 μA

−40°C ≤ TA ≤ +85°C 5 μA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ, CL = 50 pF 25 V/ms Turn-On Time AV = 1, VO = 1 V 40 μs A Saturation Recovery Time 65 μs Gain Bandwidth Product GBP 95 kHz Phase Margin φM 70 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 10 μV p-p Voltage Noise Density en f = 1 kHz 75 nV/√Hz Current Noise Density in <1 pA/√Hz

1

VOS is tested under a no load condition.

1

V

1.5 mV

OS

R

VO

= 1 MΩ, VO = 0.3 V to 2.7 V 5 13 V/mV

L

= 20, VO = 1 V 50 μs

V

Rev. D | Page 3 of 20

OP281/OP481

VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Condition Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage

−40°C ≤ TA ≤ +85°C 2.5 mV

Input Bias Current IB −40°C ≤ TA ≤ +85°C 3 10 nA

Input Offset Current IOS −40°C ≤ TA ≤ +85°C 0.1 7 nA

Input Voltage Range 0 4 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 4.0 V, −40°C ≤ TA ≤ +85°C 65 90 dB

Large-Signal Voltage Gain AVO RL = 1 MΩ, VO = 0.5 V to 4.5 V 5 15 V/mV

−40°C ≤ TA ≤ +85°C 2 V/mV

Offset Voltage Drift ΔVOS/ΔT −40°C to +85°C 10 μV/°C

Bias Current Drift ΔIB/ΔT 20 pA/°C

Offset Current Drift ΔIOS/ΔT 2 pA/°C OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 100 kΩ to GND, −40°C ≤ TA ≤ +85°C 4.925 4.96 V

Output Voltage Low VOL RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C 25 75 mV

Short-Circuit Limit ISC ±3.5 mA POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C 76 95 dB

Supply Current/Amplifier ISY VO = 0 V 3.2 4 μA

−40°C ≤ TA ≤ +85°C 5 μA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ, CL = 50 pF 27 V/ms

Saturation Recovery Time 120 μs

Gain Bandwidth Product GBP 100 kHz

Phase Margin φM 74 Degrees NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 10 μV p-p

Voltage Noise Density en f = 1 kHz 75 nV/√Hz

Current Noise Density in <1 pA/√Hz

1

VOS is tested under a no load condition.

1

V

0.1 1.5 mV

OS

Rev. D | Page 4 of 20

OP281/OP481

VS = ±5.0 V, TA = +25°C, unless otherwise noted.

Table 3.

Parameter Symbol Condition Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage –40°C ≤ TA ≤ +85°C 2.5 mV Input Bias Current IB –40°C ≤ TA ≤ +85°C 3 10 nA Input Offset Current IOS –40°C ≤ TA ≤ +85°C 0.1 7 nA Input Voltage Range –5 +4 V Common-Mode Rejection CMRR VCM = –5.0 V to +4.0 V, –40°C ≤ TA ≤ +85°C 65 95 dB Large-Signal Voltage Gain AVO RL = 1 MΩ, VO = ±4.0 V, 5 13 V/mV –40°C ≤ TA ≤ +85°C 2 V/mV Offset Voltage Drift ΔVOS/ΔT –40°C to +85°C 10 μV/°C Bias Current Drift ΔIB/ΔT 20 pA/°C Offset Current Drift ΔIOS/ΔT 2 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing VO RL = 100 kΩ to GND, –40°C ≤ TA ≤ +85°C ±4.925 ±4.98 V Short-Circuit Limit ISC 12 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±1.35 V to ±6 V, –40°C ≤ TA ≤ +85°C 76 95 dB Supply Current/Amplifier ISY VO = 0 V 3.3 5 μA –40°C ≤ TA ≤ +85°C 6 μA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ, CL = 50 pF 28 V/ms Gain Bandwidth Product GBP 105 kHz Phase Margin φM 75 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 10 μV p-p Voltage Noise Density en f = 1 kHz 85 nV/√Hz f = 10 kHz 75 nV/√Hz Current Noise Density in <1 pA/√Hz

1

VOS is tested under a no load condition.

1

V

0.1 1.5 mV

OS

Rev. D | Page 5 of 20

OP281/OP481

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 16 V Input Voltage GND to VS + 10 V Differential Input Voltage ±3.5 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +150°C Lead Temperature Range (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 5. Thermal Resistance

Package Type θ

8-Lead SOIC (R Suffix) 158 43 °C/W 8-Lead TSSOP (RU Suffix) 240 43 °C/W 14-Lead SOIC (R Suffix) 120 36 °C/W 14-Lead TSSOP (RU Suffix) 240 43 °C/W

1

θJA is specified for the worst-case conditions, that is, θJA is specified for device

soldered in circuit board for TSSOP and SOIC packages.

1

θ

JA

JC

Unit

ESD CAUTION

Rev. D | Page 6 of 20

OP281/OP481

TYPICAL PERFORMANCE CHARACTERISTICS

45

VS = 2.7V T

= 25°C

A

40

35

30

25

20

15

QUANTITY (Amplifiers)

10

5

0

INPUT OFFSET VOLTAGE (mV)

0.60.40.20

1.00.8–0.6 –0.4 –0.2–1.0 –0.8

00291-005

Figure 5. Input Offset Voltage Distribution

0

VS = 5V

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

INPUT BIAS CURRENT (nA)

–4.0

–4.5

–5.0

TEMPERATURE (° C)

1008060

12002040–40 –20

0291-008

Figure 8. Input Bias Current vs. Temperature

50

VS = 5V T

= 25°C

A

45

40

35

30

25

20

15

QUANTITY (Amplifiers)

10

5

0

INPUT OFFSET VOLTAGE (mV)

0.60.40.20

1.00.8–0.6 –0.4 –0.2–1.0 –0.8

00291-006

Figure 6. Input Offset Voltage Distribution

2000

VS = 5V

1800

1600

1400

1200

1000

800

600

INPUT OFFSET VOLTAGE (µV)

400

200

0

TEMPERATURE (° C)

1008060

12002040–40 –20

0291-007

Figure 7. Input Offset Voltage vs. Temperature

1.0 VS = 5V T

= 25°C

A

0.5

0

–0.5

–1.0

–1.5

–2.0

INPUT BIAS CURRENT (nA)

–2.5

–3.0

–3.5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

COMMON-MODE VOLTAGE (V)

Figure 9. Input Bias Current vs. Common-Mode Voltage

0.5

VS = 5V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

INPUT OFFSET CURRENT ( nA)

–0.3

–0.4

TEMPERATURE ( °C)

Figure 10. Input Offset Current vs. Temperature

00291-009

1008060

12002040–40 –20

0291-010

Rev. D | Page 7 of 20

OP281/OP481

10000

VS = 3V T

= 25°C

A

1000

100

SOURCE

10

OUTPUT VOLTAGE (mV)

1

0.1

SINK

LOAD CURRENT ( µA)

Figure 11. Output Voltage to Supply Rail vs. Load Current

1000100101

00291-011

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

–30

1k 10k 100k

FREQUENCY (H z)

Figure 14. Open-Loop Gain and Phase vs. Frequency

VS = 5V T

= 25°C

A

R

= 100kΩ

L

0

45

90

135

180

225

PHASE SHIF T (Degrees)

270

1M100

00291-014

1000

VS = 5V T

= 25°C

A

100

SOURCE

10

OUTPUT VO LTAGE (mV)

1

0.1

LOAD CURRENT ( µA)

SINK

Figure 12. Output Voltage to Supply Rail vs. Load Current

1000

VS = ±5V T

= 25°C

A

100

SOURCE

10

OUTPUT VOLTAGE (mV)

1

0.1

LOAD CURRENT ( µA)

SINK

Figure 13. Output Voltage to Supply Rail vs. Load Current

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

1000100101

00291-012

–30

1k 10k 100k

FREQUENCY (H z)

VS = 3V T

= 25°C

A

R

= 100kΩ

L

0

45

90

135

180

225

PHASE SHIFT (Degrees)

270

1M100

0291-015

Figure 15. Open-Loop Gain and Phase vs. Frequency

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

1000100101

00291-013

–30

1k 10k 100k

FREQUENCY (H z)

VS = 2.7V T

= 25°C

A

R

= 100kΩ

L

0

45

90

135

180

225

PHASE SHIFT (Degrees)

270

1M100

00291-016

Figure 16. Open-Loop Gain and Phase vs. Frequency

Rev. D | Page 8 of 20

OP281/OP481

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

–30

1k 10k 100k

FREQUENCY (H z)

VS = ±5V T

A

R

L

Figure 17. Open-Loop Gain and Phase vs. Frequency

= 25°C = 100kΩ TO GROUND

0

45

90

135

180

225

PHASE SHIFT (Degrees)

270

1M100

00291-017

90

VS = ±5V

80

70

VS = +5V

60

50

40

CMRR (dB)

30

20

10

0

–10

VS = +3V

10k 100k 1M

FREQUENCY (H z)

TA = 25°C

10M1k

00291-020

Figure 20. CMRR vs. Frequency

60

50

40

30

20

10

0

–10

CLOSED-LOOP GAIN (dB)

–20

–30

–40

FREQUENCY (H z)

Figure 18. Closed-Loop Gain vs. Frequency

(50nV/√Hz/DIV)

FREQUENCY (kHz)

Figure 19. Voltage Noise Density vs. Frequency

VS = 5V T

= 25°C

A

R

= ∞

L

VS = 5V T

= 25°C

A

MARKER @ 67nV/√Hz

160

140

120

100

80

60

PSRR (dB)

40

20

0

–20

1M10 100 1k 10k 100k

00291-018

–40

FREQUENCY (H z)

VS = ±5V, +5V, +3V, +2.7V T

= 25°C

A

R

= ∞

L

1M10 100 1k 10k 100k

00291-021

Figure 21. PSRR vs. Frequency

50

VS = +5V V

= ±50mV

45

IN

R

= 100kΩ

L

T

= 25°C

A

40

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT (%)

5

1086420

00291-019

0

10 1000

LOAD CAPACITANCE ( pF)

100

–OS

+OS

00291-022

Figure 22. Small-Signal Overshoot vs. Load Capacitance

Rev. D | Page 9 of 20

OP281/OP481

5

4

3

2

1

MAXIMUM OUTPUT SWING (V p-p)

0

10 100k

100 1k 10k

FREQUENCY (Hz)

VS = 5V V

= 4V p-p

IN

T

= 25°C

A

R

= ∞

L

Figure 23. Maximum Output Swing vs. Frequency

00291-023

4.5 VS = 5V

4.0

3.5

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT/AMPLIFIER (µA)

0.5

0

20 40 60 80 1201000–20–40

TEMPERATURE ( °C)

Figure 26. Supply Current/Amplifier vs. Temperature

00291-026

3

2

1

MAXIMUM OUTPUT SWING (V p-p)

0

10 100k

100 1k 10k

FREQUENCY (Hz)

VS = 3V V T R

Figure 24. Maximum Output Swing vs. Frequency

4.0 VS = 3V

3.5

3.0

2.5

2.0

= 2V p-p

IN

= 25°C

A

= ∞

L

3.50 TA = 25°C

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

SUPPLY CURRENT/AMPLIFIER (µA)

0.50

0.25

0

0.50 1.0 2.0 3.0 4.0 5.0 6.01.5 2.5 3. 5 4.5 5. 5

00291-024

SUPPLY VOLTAGE (±V)

0291-027

Figure 27. Supply Current/Amplifier vs. Supply Voltage

VS = ±2.5V

= 1

A

V

= 100kΩ

R

L

= 50pF

C

L

= 25°C

T

A

100

A2

90

0mV

1.5

1.0

SUPPLY CURRENT/AMPLIFIER (µA)

0.5

0

20 40 60 80 1201000–20–40

TEMPERATURE ( °C)

Figure 25. Supply Current/Amplifier vs. Temperature

00291-025

Rev. D | Page 10 of 20

10

0%

50mV

100µs

00291-028

Figure 28. Small-Signal Transient Response

OP281/OP481

100

A2

90

10

0%

0mV

50mV

Figure 29. Small-Signal Transient Response

A2

90

2.5V

100µs

VS = ±1.35V

= 1

A

V

R

= 100kΩ

L

= 50pF

C

L

T

= 25°C

A

VS = 5V

= 1

A

V

= 100kΩ

R

L

= 50pF

C

L

= 25°C

T

A

100µs

VS = 2.75V

= 1

A

V

R

= 100kΩ

L

= 50pF

C

L

T

= 25°C

A

00291-031

A2

100

90

10

0%

0.5V

500mV

00291-029

Figure 31. Large-Signal Transient Response

VS = 5V

= 25°C

T

A

100

A2

90

2.5V

10

0%

1V

Figure 30. Large-Signal Transient Response

100µs

10

0%

1V 1V

00291-030

200µs

00291-032

Figure 32. No Phase Reversal

Rev. D | Page 11 of 20

OP281/OP481

A2

100

90

10

0%

VS = ±1.35V

0V

500mV 500mV

= ∞

R

L

Figure 33. Saturation Recovery Time

50µs

VIN = ±1V p-p AT = 2kHz

120

105

90

75

60

45

30

15

CHANNEL SEPARATIO N (dB)

0

–15

–30

00291-033

100 1M

1k 10k 100k

FREQUENCY (Hz)

Figure 35. Channel Separation vs. Frequency

VS = 5V T

= 25°C

A

= ∞

R

L

00291-035

100

90

10

0%

A2

1V 500mV

0V

CIRCUIT = A

100µs

VOL

VS = 2.5V

= 25°C

T

A

= ∞

R

L

00291-034

Figure 34. Saturation Recovery Time

Rev. D | Page 12 of 20

OP281/OP481

−

V

APPLICATIONS

THEORY OF OPERATION

The OPx81 family of op amps is comprised of extremely low powered, rail-to-rail output amplifiers, requiring less than 4 μA of quiescent current per amplifier. Many other competitors’ devices may be advertised as low supply current amplifiers but draw significantly more current as the outputs of these devices are driven to a supply rail. The supply current of the OPx81 remains under 4 μA even when the output is driven to either supply rail. Supply currents should meet the specification as long as the inputs and outputs remain within the range of the power supplies.

Figure 36 shows a simplified schematic of a single channel for the OPx81. A bipolar differential pair is used in the input stage. PNP transistors are used to allow the input stage to remain linear with the common-mode range extending to ground. This is an important consideration for single-supply applications. The bipolar front end also contributes less noise than a MOS front end with only nanoamps of bias currents. The output of the op amp consists of a pair of CMOS transistors in a common source configuration. This setup allows the output of the amplifier to swing to within millivolts of either supply rail. The headroom required by the output stage is limited by the amount of current being driven into the load. The lower the output current, the closer the output can go to either supply rail. Figure 11, Figure 12, and Figure 13 show the output voltage headroom vs. the load current. This behavior is typical of railto-rail output amplifiers.

V

CC

OUT

+IN

–IN

to the lowest possible input signal excursion and can be found using the following formula:

VV

,

MININEE

R

=

3

105.0−×

where:

VEE is the negative power supply for the amplifier. V

is the lowest input voltage excursion expected.

IN, MIN

For example, a single channel of the OPx81 should be used with a single-supply voltage of +5 V if the input signal may go as low as

−1 V. Because the amplifier is powered from a single supply, V

is

EE

the ground; therefore, the necessary series resistance should be 2 kΩ.

INPUT OFFSET VOLTAGE

The OPx81 family of op amps was designed for low offset voltages (less than 1 mV).

100kΩ

CM

100kΩ

< 0 V

+3V

OP281

V

OUT

00291-037

100kΩ

–0.27V

Figure 37. Single OPx81 Channel Configured as a Difference Amplifier

+

–

100kΩ

VIN = 1kHz AT 400mV p-p

–0.1V

Operating at V

INPUT COMMON-MODE VOLTAGE RANGE

The OPx81 is rated with an input common-mode voltage range from V with a common-mode voltage that is slightly less than V Figure 37 shows a single OPx81 channel configured as a difference amplifier with a single-supply voltage of 3 V. Negative dc voltages are applied at both input terminals, creating a common-mode voltage that is less than ground. A 400 mV p-p input signal is then applied to the noninverting input. Figure 38 shows the resulting input and output waves. Notice how the output of the amplifier also drops slightly negative without distortion.

to 1 V less than VCC. However, the op amp can operate

EE

.

EE

V

EE

Figure 36. Simplified Schematic of a Single OPx81 Channel

00291-036

OUT

100

90

0.2ms

INPUT OVERVOLTAGE PROTECTION

The input stage to the OPx81 family of op amps consists of a PNP differential pair. If the base voltage of either of these input transistors drops to more than 0.6 V below the negative supply,

V

IN

the input ESD protection diodes become forward-biased, and large currents begin to flow. In addition to possibly damaging the device, this creates a phase reversal effect at the output. To prevent this, the input current should be limited to less than 0.5 mA.

This can be done by simply placing a resistor in series with the input to the device. The size of the resistor should be proportional

Rev. D | Page 13 of 20

10

0%

0.1V

Figure 38. Input and Output Signals with V

CM

< 0 V

0V

00291-038

OP281/OP481

V

CAPACITIVE LOADING

Most low supply current amplifiers have difficulty driving capacitive loads due to the higher currents required from the output stage for such loads. Higher capacitance at the output will increase the amount of overshoot and ringing in the amplifier’s step response and may affect the stability of the device. However, through careful design of the output stage and its high phase margin, the OPx81 family can tolerate some degree of capacitive loading. Figure 39 shows the step response of a single channel with a 10 nF capacitor connected at the output. Notice that the overshoot of the output does not exceed more than 10% with such a load, even with a supply voltage of only 3 V.

WINDOW COMPARATOR

The extremely low power supply current demands of the OPx81 family make it ideal for use in long-life battery-powered applications such as a monitoring system. Figure 41 shows a circuit that uses the OP281 as a window comparator.

5.1kΩ

3

V

OUT

Q1

3V

R1

R2

IN

2kΩ

3V

V

H

A1

OP281-A

3V

D1

10kΩ

5.1kΩ

100

90

10

0%

00291-039

Figure 39. Ringing and Overshoot of the Output of the Amplifier

MICROPOWER REFERENCE VOLTAGE GENERATOR

Many single-supply circuits are configured with the circuit biased to half of the supply voltage. In these cases, a false ground reference can be created by using a voltage divider buffered by an amplifier. Figure 40 shows the schematic for such a circuit.

The two 1 MΩ resistors generate the reference voltage while drawing only 1.5 μA of current from a 3 V supply. A capacitor connected from the inverting terminal to the output of the op amp provides compensation to allow a bypass capacitor to be connected at the reference output. This bypass capacitor helps to establish an ac ground for the reference output. The entire reference generator draws less than 5 μA from a 3 V supply source.

3V TO 12

10kΩ

0.022µF

R3

V

L

R4

A2

OP281-B

D2

00291-041

Figure 41. Using the OP281 as a Window Comparator

The threshold limits for the window are set by VH and VL, provided that V

> VL. The output of the first OP281 (A1) will

H

stay at the negative rail, in this case ground, as long as the input voltage is less than V

. Similarly, the output of the second

H

OP281 (A2) will stay at ground as long the input voltage is higher than V

. As long as VIN remains between VL and VH, the

L

outputs of both op amps will be 0 V. With no current flowing in either D1 or D2, the base of Q1 will stay at ground, putting the transistor in cutoff and forcing V If the input voltage rises above V

to the positive supply rail.

OUT

, the output of A2 stays at

H

ground, but the output of A1 goes to the positive rail and D1 conducts current. This creates a base voltage that turns on Q1 and drives V below V current. Therefore, V V

and VH, but low if the input voltage moves outside of that range.

L

low. The same condition occurs if VIN falls

OUT

with A2’s output going high and D2 conducting

L

is high if the input voltage is between

OUT

The R1 and R2 voltage divider sets the upper window voltage, and the R3 and R4 voltage divider sets the lower voltage for the window. For the window comparator to function properly, V must be a greater voltage than V

V

R2

=

H

=

L

R4

R2R1

+

R4R3

+

.

L

H

The 2 kΩ resistor connects the input voltage of the input terminals to the op amps. This protects the OP281 from possible excess current flowing into the input stages of the devices. D1 and D2 are small-signal switching diodes (1N4446 or equivalent), and Q1 is a 2N2222 or an equivalent NPN transistor.

1MΩ

1µF

2

3

8

OP281

4

100Ω

1

1µF

V

REF

1.5V TO 6V

00291-040

Figure 40. Single Channel Configured as a Micropower Bias Voltage Generator

Rev. D | Page 14 of 20

OP281/OP481

V

LOW-SIDE CURRENT MONITOR

In the design of power-supply control circuits, a great deal of design effort is focused on ensuring the long-term reliability of a pass transistor over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of primary importance in these designs. Figure 42 shows an example of a 5 V, single-supply current monitor that can be incorporated into the design of a voltage regulator with foldback current limiting or a high current power supply with crowbar protection. The design capitalizes on the OPx81’s common-mode range extending to ground. Current is monitored in the power-supply return path, where a 0.1 Ω shunt resistor, R

, creates a very small voltage drop. The

SENSE

voltage at the inverting terminal becomes equal to the voltage at the noninverting terminal through the feedback of Q1, which is a 2N2222 or an equivalent NPN transistor. This makes the voltage drop across R1 equal to the voltage drop across R

SENSE

. Therefore, the current through Q1 becomes directly proportional to the current through R

, and the output

SENSE

voltage is given by the following equation:

R

OUT

⎜ ⎝

SENSECC

R

1

2

⎛

VV

The voltage drop across R2 increases as I

decreases if a higher supply current is sensed. For the

V

OUT

element values shown, the V

−2.5 V/A, decreasing from V

OUT

Q1

Figure 42. Low-Side Load Current Monitor

CC

R

R2

2.49kΩ

R1 100Ω

0.1Ω

SENSE

OUT

CC

⎞

××−=

IR

⎟

L

⎠

increases; therefore,

L

transfer characteristic is

.

V

CC

SINGLE CHANNEL OPx81

RETURN TO GROUND

00291-042

LOW VOLTAGE HALF-WAVE AND FULL-WAVE RECTIFIERS

Because of its quick overdrive recovery time, an OP281 can be configured as a full-wave rectifier for low frequency (<500 Hz) applications. Figure 43 shows the schematic.

= 2V p-p

IN

R1

100kΩ

3V

2kΩ

A1

OP281-A

R2

100kΩ

3V

A2

OP281-B

FULL-WAVE RECTIF IED OUTPUT

HALF-W AVE RECTIF IED OUTPUT

00291-043

Figure 43. Single-Supply Full-Wave and Half-Wave Rectifiers Using an OP281

100

90

10

0%

SCALE

0.1V/DIV

SCALE

0.1ms/DIV

00291-044

Figure 44. Full-Wave Rectified Signal

Amplifier A1 is used as a voltage follower that tracks the input voltage only when it is greater than 0 V. This provides a halfwave rectification of the input signal to the noninverting terminal of Amplifier A2. When A1’s output is following the input, the inverting terminal of A2 also follows the input from the virtual ground between the inverting and noninverting terminals of A2. With no potential difference across R1, no current flows through either R1 or R2; therefore, the output of A2 also follows the input. When the input voltage goes below 0 V, the noninverting terminal of A2 becomes 0 V. This makes A2 work as an inverting amplifier with a gain of 1 and provides a full-wave rectified version of the input signal. A 2 kΩ resistor in series with A1’s noninverting input protects the device when the input signal becomes less than ground.

BATTERY-POWERED TELEPHONE HEADSET AMPLIFIER

Figure 45 shows how the OP281 can be used as a two-way amplifier in a telephone headset. One side of the OP281 can be used as an amplifier for the microphone, and the other side can be used to drive the speaker. A typical telephone headset uses a 600 Ω speaker and an electret microphone that requires a supply voltage and a biasing resistor.

Rev. D | Page 15 of 20

OP281/OP481

3V

2.2kΩ

INPUT

3V

1MΩ 1MΩ

ELECTRET MIC

1µF

10kΩ

POT.

1µF

0.1µF

11kΩ 300kΩ

3V

1MΩ

1µF

1MΩ

50kΩ10kΩ

3V

OP281-B

3V

OP281-A

20kΩ

1µF

3V

Q1

Q2

MIC OUT

1µF

600Ω

SPEAKER

00291-045

Figure 45. Two-Way Amplifier in a Battery-Powered Telephone Headset

The OP281-A op amp provides about 29 dB of gain for audio signals coming from the microphone. The gain is set by the 300 kΩ and 11 kΩ resistors. The gain bandwidth product of the amplifier is 95 kHz, which yields a −3 dB rolloff at 3.4 kHz for the set gain of 28. This is acceptable because telephone audio is band limited for 300 kHz to 3 kHz signals. If higher gain is required for the microphone, an additional gain stage should be used, because adding more gain to the OP281 would limit the

audio bandwidth. A 2.2 kΩ resistor is used to bias the electret microphone. This resistor value may vary depending on the specifications of the microphone. The output of the microphone is ac-coupled to the noninverting terminal of the op amp. Two 1 MΩ resistors are used to provide the dc offset for single-supply use.

The OP281-B amplifier (see Figure 45) can provide up to 15 dB of gain for the headset speaker. Incoming audio signals are ac-coupled to a 10 kΩ potentiometer that is used to adjust the volume. Again, two 1 MΩ resistors provide the dc offset with a 1 μF capacitor establishing an ac ground for the volume-control potentiometer. Because the OP281 is a rail-to-rail output amplifier, it would have difficulty driving a 600 Ω speaker directly. Here, a Class AB buffer is used to isolate the load from the amplifier and to provide the necessary current to drive the speaker. By placing the buffer in the feedback loop of the op amp, crossover distortion can be minimized. Q1 and Q2 should have minimum betas of 100. The 600 Ω speaker is ac-coupled to the emitters to prevent quiescent current from flowing into the speaker. The 1 μF coupling capacitor makes an equivalent high-pass filter cutoff at 265 Hz with a 600 Ω load attached. Again, this does not pose a problem because it is outside the frequency range for telephone audio signals.

The circuit in Figure 45 draws around 250 μA of current. The Class AB buffer has a quiescent current of 140 μA, and roughly 100 μA is drawn by the microphone itself. A CR2032 3 V lithium battery has a life expectancy of 160 mA hours, which means this circuit can run continuously for 640 hours on a single battery.

Rev. D | Page 16 of 20

OP281/OP481

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

4.00 (0.1574)

3.80 (0.1497)

SEATING

PLANE

85

1

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

BSC

8

6.20 (0.2441)

5.80 (0.2283)

7

1.75 (0.0689)

1.35 (0.0531)

SEATING PLANE

8° 0°

0.25 (0.0098)

0.17 (0.0067)

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 47. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

060606-A

Rev. D | Page 17 of 20

OP281/OP481

Y

0.15

0.05

COPLANARIT

0.10

3.10

3.00

2.90

8

5

4.50

6.40 BSC

4.40

4.30

41

PIN 1

0.65 BSC

1.20 MAX

0.30 SEATING

0.19

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AA

0.20

0.09

8° 0°

0.75

0.60

0.45

Figure 48. 8-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-8)

Dimensions shown in millimeters

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65 BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40 BSC

71

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

8° 0°

0.75

0.60

0.45

Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

OP281GRU-REEL –40°C to +85°C 8-Lead TSSOP RU-8 OP281GRUZ-REEL OP281GS –40°C to +85°C 8-Lead SOIC_N R-8 OP281GS-REEL –40°C to +85°C 8-Lead SOIC_N R-8 OP281GS-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ1 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ-REEL1 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ-REEL71 –40°C to +85°C 8-Lead SOIC_N R-8 OP481GRU-REEL –40°C to +85°C 14-Lead TSSOP RU-14 OP481GRUZ-REEL1 –40°C to +85°C 14-Lead TSSOP RU-14 OP481GS –40°C to +85°C 14-Lead SOIC_N R-14 OP481GS-REEL –40°C to +85°C 14-Lead SOIC_N R-14 OP481GS-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ1 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ-REEL1 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ-REEL71 –40°C to +85°C 14-Lead SOIC_N R-14

1

Z = RoHS Compliant Part.

1

–40°C to +85°C 8-Lead TSSOP RU-8

Rev. D | Page 18 of 20

OP281/OP481

NOTES

Rev. D | Page 19 of 20

OP281/OP481

NOTES

Rev. D | Page 20 of 20

Datasheet OP481 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PIN CONFIGURATIONS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS

THEORY OF OPERATION

INPUT OFFSET VOLTAGE

INPUT COMMON-MODE VOLTAGE RANGE

INPUT OVERVOLTAGE PROTECTION

CAPACITIVE LOADING

WINDOW COMPARATOR

MICROPOWER REFERENCE VOLTAGE GENERATOR

LOW-SIDE CURRENT MONITOR

LOW VOLTAGE HALF-WAVE AND FULL-WAVE RECTIFIERS

BATTERY-POWERED TELEPHONE HEADSET AMPLIFIER

OUTLINE DIMENSIONS

ORDERING GUIDE