Datasheet OP471EY, OP471GS, OP471GP, OP471FY Datasheet (Analog Devices)

14

13

12

11

10

9

8

1

2

3

4

5

6

7

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OP471

High Speed, Low Noise Quad

–

a

FEATURES
Excellent Speed: 8 V/s Typ
Low Noise: 11 nV/÷
Unity-Gain Stable
High Gain Bandwidth: 6.5 MHz Typ
Low Input Offset Voltage: 0.8 mV Max
Low Offset Voltage Drift: 4 V/C Max
High Gain: 500 V/mV Min
Outstanding CMR: 105 dB Min
Industry Standard Quad Pinouts

GENERAL DESCRIPTION

The OP471 is a monolithic quad op amp featuring low noise,
11 nV/÷Hz Max @ 1 kHz, excellent speed, 8 V/ms typical, a
gain bandwidth of 6.5 MHz, and unity-gain stability.

The OP471 has an input offset voltage under 0.8 mV and an
input offset voltage drift below 4 mV/∞C, guaranteed over the full
military temperature range. Open-loop gain of the OP471 is over
500,000 into a 10 kW load ensuring outstanding gain accuracy
and linearity. The input bias current is under 25 nA limiting
errors due to signal source resistance. The OP471’s CMR of
over 105 dB and PSRR of under 5.6 mV/V significantly reduce
errors caused by ground noise and power supply fluctuations.

The OP471 offers excellent amplifier matching which is important
for applications such as multiple gain blocks, low-noise instru­mentation amplifiers, quad buffers and low-noise active filters.

The OP471 conforms to the industry standard 14-lead DIP
pinout. It is pin-compatible with the LM148/LM149, HA4741,
RM4156, MC33074, TL084 and TL074 quad op amps and can
be used to upgrade systems using these devices.

For applications requiring even lower voltage noise the OP470
with a voltage density of 5 nV/÷Hz Max @ 1 kHz is recommended.

Hz @ 1 kHz Max

Operational Amplifier

PIN CONFIGURATIONS

14-Lead

Hermetic Dip

(Y-Suffix)

OUT A OUT D

–IN A –IN D

+IN A +IN D

+IN B +IN C

–IN B –IN C

OUT B OUT C

NC NC

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

16-Lead SOIC

(S-Suffix)

1

2

3

4

V+ V–

OP471

5

6

7

8

NC = NO CONNECT

16

15

14

13

12

11

10

9

V+

OP471

14-Lead

Plastic Dip

(P-Suffix)

1

2

3

4

OP471

5

6

7

14

13

12

11

10

9

8

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

BIAS

IN

+IN

OUT

V–

Figure 1. Simplified Schematic

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

OP471–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 15 V, TA = 25C, unless otherwise noted.)

OP471E OP471F OP471G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit

Input Offset Voltage V

Input Offset Current I

Input Bias Current I

Input Noise Voltage

Input Noise e

Voltage Density

1

2

OS

OS

B

VCM = 0 V 4 10 7 20 12 30 nA

VCM = 0 V 7 25 15 50 25 60 nA

en p-p 0.1 Hz to 10 Hz 250 500 250 500 250 500 nV p–p

n

fO = 10 Hz 9 16 9 16 9 16 nV/÷Hz
fO = 100 Hz 7 12 7 12 7 12 nV/÷Hz

0.25 0.8 0.5 1.5 1.0 1.8 mV

fO = 1 kHz 6.5 11 6.5 11 6.5 11 nV/÷Hz

Input Noise i

n

Current Density f

fO = 10 Hz 1.7 1.7 1.7 pA÷Hz

= 100 Hz 0.7 0.7 0 7 pA÷Hz

O

fO = 1 kHz 0.4 0.4 0.4 pA÷Hz

Large-Signal A

VO

Voltage Gain R

V = ± 10 V

= 10 kW 500 700 300 500 300 500 V/mV

L

RL = 2 kW 350 550 175 275 175 275 V/mV

Input Voltage Range3IVR ± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V

Output Voltage Swing V

O

Common-Mode CMR V

RL ≥ 2 kW±12 ± 13 ± 12 ± 13 ± 12 ± 13 V

= ± 11 V 105 120 95 115 95 115 dB

CM

Rejection

Power Supply PSRR V

= 4.5 V to 18 V 1 5.6 5.6 17.8 5.6 17.8 mV/V

S

Rejection Ratio

Slew Rate SR 6.5 8 6.5 8 6.5 8 V/ms

Supply Current I

SY

No Load 9.2 11 9.2 11 9.2 11 mA

(All Amplifiers)

Gain Bandwidth GBW Av = 10 6.5 6.5 6.5 MHz

Product

Channel Separation

1

CS VO = 20 V p-p 125 150 125 150 125 150 dB

fO = 10 Hz

Input Capacitance C

Input Resistance R

IN

IN

2.6 2.6 2.6 pF

1.1 1.1 1.1 MW

Differential-Mode

Input Resistance R

INCM

11 11 11 GW

Common-Mode

Settling Time t

S

AV = 1
To 0.1% 4.5 4.5 4.5 ms
To 0.01 % 7.5 7.5 7.5 ms

NOTES

1

Guaranteed but not 100% tested.

2

Sample tested.

3

Guaranteed by CMR test.

–2–

REV. A

OP471

WARNING!

ESD SENSITIVE DEVICE

(Vs = ±15 V, –25C £ TA £ 85C for OP471E/F, –40C £ TA £ 85 for OP471G,

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit

Input Offset Voltage V

Average Input TCV

Offset Voltage Drift

Input Offset Current los VCM = 0 V 5 20 8 40 20 50 nA

Input Bias Current I

Large-Signal V

Voltage Gain Avo R

Input Voltage Range* IVR ± 11 ± 12 ± 11 ± 12 ± 11 ± 12 V

Output Voltage Swing V

Common-Mode CMR V

Rejection

Power Supply PSRR V

Rejection Ratio

Supply Current

(All Amplifiers) I

*Guaranteed by CMR test.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Differential Input Voltage
Differential Input Current

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage

Output Short-Circuit Duration . . . . . . . . . . . . . . . Continuous

Storage Temperature Range

P, Y-Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C

Junction Temperature (T
Operating Temperature Range

OP471E, OP471F . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C

OP471G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C

NOTES

1

Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.

2

The OP471’s inputs are protected by back-to-back diodes. Current limiting

resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ± 1.0 V, the input current should be limited to ± 25 mA.

OS

OS

B

VCM = 0 V 13 50 2570 4075 nA

= ± 10 V

O

= 10 kW 375 600 200 400 200 400 V/mV

L

RL = 2 kW 250 400 125 200 125 200

O

SY

2

. . . . . . . . . . . . . . . . . . . . . . ± 1.0 V

2

. . . . . . . . . . . . . . . . . . . . ± 25 mW

) . . . . . . . . . . . . . –65∞C to +150∞C

i

RL ≥ 2 kW±12 ± 13 ± 12 ± 13 ± 12 ± 13 V

CM

= ± 4.5 V to ± 18 V 3.2 10 18 31.6 18 31.6 mV/V

S

No Load 9.3 11 9.3 11 9.3 11 mA

1

unless otherwise noted.)

OP471E OP471F OP471G

0.3 1.1 0.6 2.0 1.2 2.5 mV
14 27 4 mV/∞C

= ± 11 V 100 115 90 110 90 110 dB

Package Type JA* 

JC

Unit

14-Lead Hermetic DIP(Y) 94 10 ∞C/W

14-Lead Plastic DIP(P) 76 33 ∞C/W

16-Lead SOIC (S) 88 23 ∞C/W

*␪

is specified for worst-case mounting conditions, i.e., ␪JA is specified for device

JA

in socket for TO, CERDIP, PDIP packages; ␪JA is specified for device soldered to
printed circuit board for SO packages.

ORDERING GUIDE

TA = 25∞C Package Options Operating
V

MAX Temperature

OS

(mV) 14-Lead CERDIP Plastic Range

800 OP471EY IND
1,500 OP471FY* IND
1,800 OP471GP XIND
1,800 OP471GS XIND

*Not for new design. Obsolete April 2002.

For military processed devices, please refer to the standard
microcircuit drawing (SMD) available at

www.dscc.dla.mil/programs/milspec/default.asp

5962-88565022A - OP471ARCMDA
5962-88565023A - OP471ATCMDA
5962-8856502CA - OP471AYMDA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP471 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

OP471

k

k

100

40
30

20

10

–Typical Performance Characteristics

10

T

TA = 25C

= 15V

V

S

= 25C

A

8

6

AT 10Hz

AT 1kHz

5mV

100

90

1s

5

4
3

I/F CORNER = 5Hz

VOLTA G E NOISE – nV/ Hz

2

1

1

10 100 1

FREQUENCY – Hz

TPC 1. Voltage Noise Density
vs. Frequency

100

TA = 25C

= 15V

V

S

40
30

20

10

5

4
3

I/F CORNER = 5Hz

VOLTA G E NOISE – nV/ Hz

2

1

1

10 100 1

FREQUENCY – Hz

TPC 4. Current Noise Density
vs. Frequency

4

VOLTA G E NOISE – nV/ Hz

2

0 5 20

10 15

SUPPLY VOLTAGE – V

TPC 2. Voltage Noise Density
vs. Supply Voltage

400

VS = 15V

300

200

100

INPUT OFFSET VOLTAGE – V

0

–75

–50 –25 0 25 50 75 100 125

TEMPERATURE – C

TPC 5. Input Offset Voltage vs.
Temperature

10

0%

NOISE VOLTAGE – 100nV/DIV

024 6810

TIME – Seconds

TA = 25C

= 15V

V

S

TPC 3. 0.1 Hz to 10 Hz Noise

20

TA = 25C

18

= 15V

V

S

16

14

12

10

8

6

4

CHANGE IN OFFSET VOLTAGE – V

2

0

1 2345

0

TIME – Minutes

TPC 6. Warm-Up Offset
Voltage Drift

20

15

10

5

INPUT BIAS CURRENT – nA

0
–75

–50 –25 0 25 50 75 100 125

TEMPERATURE – C

TPC 7. Input Bias Current vs.
Temperature

VS = 15V

= 0V

V

CM

10

VS = 15V

9

= 0V

V

CM

8

7

6

5

4

3

2

INPUT OFFSET CURRENT – nA

1

0

–50 –25 0 25 50 75 100 125

–75

TEMPERATURE – C

TPC 8. Input Offset Current vs.
Temperature

10

TA = 25C

= 15V

V

S

9

8

7

6

INPUT BIAS CURRENT – nA

5

–7.5 –2.5 2.5 7.5 12.5

–12.5

COMMON-MODE VOLTAGE – V

TPC 9. Input Bias Current vs.
Common-Mode Voltage

–4–

REV. A

OP471

0

130

120

110

100

90

80

70

60

CMR – dB

50

40

30

20

10

10 100 1k 10k 100k 1M

1

FREQUENCY – Hz

TPC 10. CMR vs. Frequency

140
130
120

110
100

90
80

70

60

PSR – dB

50

40

30

20
10

0

10 100 1k 10k 100k 1M 10M 100M

1

+PSR

FREQUENCY – Hz

TPC 13. PSR vs. Frequency

–PSR

TA = 25C

= 15V

V

S

TA = 25C

= 15V

V

S

10

TA = +25C

8

6

4

TOTA L SUPPLY CURRENT – mA

2

0 5 2

TA = +125C

TA = –55C

10 15

SUPPLY VOLTAGE – V

TPC 11. Total Supply Current
vs. Supply Voltage

140
130
120

110
100

90
80

70

60

50

40

OPEN-LOOP GAIN – dB

30

20
10

0

10 100 1k 10k 100k 1M 10M 100M

1

FREQUENCY – Hz

TA = 25C

= 15V

V

S

TPC 14. Open-Loop Gain vs. Frequency

10

VS = 15V

9

8

7

6

5

4

TOTA L SUPPLY CURRENT – mA

3

2

–50 –25 0 25 50 75 100 125

–75

TEMPERATURE – C

TPC 12. Total Supply Current
vs. Temperature

80

60

40

20

CLOSED-LOOP GAIN – dB

0

–20

1k

10k 100k 1M 10M

FREQUENCY – Hz

TA = 25C
V

TPC 15. Closed-Loop Gain
vs. Frequency

= 15V

S

25

20

PHASE

15

10

GAIN

5

0

OPEN-LOOP GAIN – dB

–5

–10

1

2345

FREQUENCY – MHz

PHASE MARGIN

TPC 16. Open-Loop Gain,
Phase Shift vs. Frequency

TA = 25C

= 15V

V

S

= 57

67 89

80

100

120

140

160

180

200

220

10

2000

PHASE SHIFT – Degrees

1500

1000

OPEN-LOOP GAIN – V/mV

TA = 25C

= 10k

R

L

500

0

5 10 15 20

0

SUPPLY VOLTAGE – V

TPC 17. Open-Loop Gain vs.
Supply Voltage

80

GBW

70

60

VS = 15V



50

PHASE MARGIN – Degrees

40

–50 –25 0 25 50 75 100 125 150

–75

TEMPERATURE – C

TPC 18. Gain-Bandwidth Product,
Phase Margin vs. Temperature

8

6

4

2

GAIN-BANDWIDTH PRODUCT – MHz

0

REV. A

–5–

OP471

28

24

20

16

12

8

PEAK-TO-PEAK AMPLITUDE – V

4

0

1k

10k 100k 1M 10M

FREQUENCY – Hz

TA = 25C

= 15V

V

S

THD = 1%

TPC 19. Maximum Output Swing
vs. Frequency

9.0

8.5

8.0

7.5

7.0

SLEW RATE – V/s

6.5

6.0
–50 –25 0 25 5075100125

–75

–SR

+SR

TEMPERATURE – C

TPC 22. Slew Rate vs. Temperature

20

TA = 25C

18

= 15V

V

S

16

14

12

10

8

6

MAXIMUM OUTPUT – V

4

2

0

100

POSITIVE

SWING

NEGATIVE
SWING

LOAD RESISTANCE – 

1k 10k

TPC 20. Maximum Output Voltage
vs. Load Resistance

170

160

150

140

130

120

110

100

90

80

CHANNEL SEPARATION – dB

70

60

50

10

100 1k 10k 100k 1M 10M

TA = 25C

= 15V

V

S

= 20V p-p TO 100kHz

V

O

FREQUENCY – Hz

TPC 23. Channel Separation vs.
Frequency

360

TA = 25C

= 15V

V

S

300

240

180

120

OUTPUT IMPEDANCE – 

60

0

100

AV = 100

AV = 1

1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

TPC 21. Closed-Loop Output
Impedance vs. Frequency

1

TA = 25C

= 15V

V

S

= 10V p-p

V

O

= 2k

R

L

0.1

0.01

AV = 10

TOTA L HARMONIC DISTORTION – %

0.001
10

100 1k 10k

FREQUENCY – Hz

AV = 1

TPC 24. Total Harmonic Distortion
vs. Frequency

TA = 25C

= 15V

V

100

90

10

0%

5V

A

5µs

S

= 1

V

TPC 25. Large-Signal Transient
Response

TA = 25C

= 15V

V

100

90

10

0%

50mV

S

A

V

0.2µs

= 1

TPC 26. Small-Signal Transient
Response

–6–

REV. A

OP471

5k

500

1/4
OP471

50k

50

1/4
OP471

CHANNEL SEPARATION = 20 LOG

V

20V p-p

1

V

2

V

1

V2 / 1000

Figure 2. Channel Separation Test Circuit

+18V

+1V

–1V

2

4

1

A

3

11

–18V

9

C

10

+1V

8

–1V

6

5

13

12

7

B

14

D

Figure 3. Burn-In Circuit

APPLICATIONS INFORMATION
Voltage and Current Noise

The OP471 is a very low-noise quad op amp, exhibiting a typical
voltage noise of only 6.5

Hz @ 1 kHz. The low noise character-

istic of the OP471 is, in part, achieved by operating the input
transistors at high collector currents since the voltage noise is
inversely proportional to the square root of the collector current.
Current noise, however, is directly proportional to the square
root of the collector current. As a result, the outstanding voltage
noise performance of the OP471 is gained at the expense of current
noise performance which is typical for low noise amplifiers.

To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (e
noise (i

), and resistor noise (et).

n

), current

n

Total Noise and Source Resistance

The total noise of an op amp can be calculated by:

EeiRe

nnnSt

222

=

()+()

+

()

where:

E

= total input referred noise

n

e

= op amp voltage noise

n

= op amp current noise

i

n

e

= source resistance thermal noise

t

R

= source resistance

S

The total noise is referred to the input and at the output would
be amplified by the circuit gain.

100

OP11

OP400

10

OP471

TOTAL NOISE – nV/ Hz

OP470

RESISTOR
NOISE ONLY

1

100 100k

RS – SOURCE RESISTANCE – 

10k1k

Figure 4. Total Noise vs. Source Resistance (Including
Resistor Noise) at 1 kHz

100

OP11

OP400

10

OP471

TOTAL NOISE – nV/ Hz

OP470

RESISTOR
NOISE ONLY

1

100 100k

RS – SOURCE RESISTANCE – 

10k1k

Figure 5. Total Noise vs. Source Resistance (Including
Resistor Noise) at 10 Hz

Figure 4 shows the relationship between total noise at 1 kHz
and source resistance. For R
nated by the voltage noise of the OP471. As R

< 1 kW the total noise is domi-

S

rises above 1 kW,

S

total noise increases and is dominated by resistor noise rather
than by voltage or current noise of the OP471. When R

exceeds

S

20 kW, current noise of the OP471 becomes the major contributor
to total noise.

Figure 5 also shows the relationship between total noise and source
resistance, but at 10 Hz. Total noise increases more quickly
than shown in Figure 4 because current noise is inversely pro­portional to the square root of frequency. In Figure 5, current
noise of the OP471 dominates the total noise when R

> 5 kW.

S

From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP400, with lower current
noise than the OP471, will provide lower total noise.

REV. A

–7–

OP471

1000

OP11

OP400

OP471

100

OP470

RESISTOR

PEAK-TO-PEAK NOISE – nV

10

100 100k

NOISE ONLY

RS – SOURCE RESISTANCE – 

10k1k

Figure 6. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source
Resistance (Includes Resistor Noise)

Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10 Hz range. Once again, at low values of R

, the

S

voltage noise of the OP471 is the major contributor to peak-to-peak
noise. Current noise becomes the major contributor as R

increases.

S

The crossover point between the OP471 and the OP400 for
peak-to-peak noise is at R

= 17 W.

S

The OP470 is a lower noise version of the OP471, with a typical
noise voltage density of 3.2 nV/÷Hz @ 1 kHz. The OP470 offers
lower offset voltage and higher gain than the OP471, but is a slower
speed device, with a slew rate of 2 V/ms compared to a slew rate
of 8 V/ms for the OP471.

For reference, typical source resistances of some signal sources
are listed in Table I.

TABLE I.

Source

Device Impedance Comments

Strain gauge < 500 W Typically used in

low-frequency applications.

Magnetic < 1,500 W Low I

very important to reduce

B

tapehead self-magnetization problems

when direct coupling is used.
OP471 IB can be neglected.

Magnetic < 1,500 W Similar need for low I

in direct

B

phonograph coupled applications. OP471
cartridges will not introduce any

self -magnetization problem.

Linear variable < 1,500 W Used in rugged servo-feedback
differential applications. Bandwidth of
transformer interest is 400 Hz to 5 kHz.

*For further information regarding noise calculations, see “Minimization of

Noise in Op Amp Applications,” Application Note AN-15.

5

R2
5

R3

1.24k

R1

OP471
DUT

200

OP27E

909

R4

C1

2F

R11

C4

0.22F

C3

0.22F

R12

10k

OP15E

R13

5.9k

GAIN = 50,000
V

S

= 15V

R14

4.99k

C5
1F

e

OUT

R5

R6
600k

D1

1N4148D21N4148

R8
10k

OP15E

306k

0.032F

R10

65.4k

R9

C2

65.4k

Figure 7. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

–8–

REV. A

Noise Measurements - Peak-to-Peak Voltage Noise

FREQUENCY – Hz

100

0.01

GAIN – dB

80

60

40

20

0

0.1 1 10 100

The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 500 nV peak-to-peak noise speci­fication of the OP471 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:

1. The device must be warmed up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 13 mV due to increasing chip temperature after
power-up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens-of-nanovolts.

2. For similar reasons, the device must be well-shielded from
air currents. Shielding also minimizes thermocouple effects.

3.

Sudden motion in the vicinity of the device can also “feedthrough”

to increase the observed noise.

4. The test time to measure 0.1 Hz to 10 Hz noise should not exceed
10 seconds. As shown in the noise-tester frequency-response curve
of Figure 8, the 0.1 Hz corner is defined by only one pole. The
test time of 10 seconds acts as an additional pole to eliminate
noise contribution from the frequency band below 0.1 Hz.

5. A noise voltage density test is recommended when measuring
noise on a large number of units. A 10 Hz noise voltage density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1/f corner frequency.

6. Power should be supplied to the test circuit by well bypassed,
low noise supplies, e.g, batteries. These will minimize output
noise introduced through the amplifier supply pins.

OP471

Figure 8. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response

Noise Measurement - Noise Voltage Density

The circuit of Figure 9 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series connected and is in unity-gain, save
the final amplifier which is in a noninverting gain of 101. Since
the ac noise voltages of each amplifier are uncorrelated, they
add in rms fashion to yield:

Ê

e=101 e + e e e

OUT nA nB nC nD

222 2

Ë

++

The OP471 is a monolithic device with four identical amplifiers.
The noise voltage density of each individual amplifier will
match, giving:

ˆ
¯

1/4
OP471

e 101 4e = 101 2e

OUT n n

R2

10k

1/4
OP471

(nV Hz) = 101(2en)

= 15V

TO SPECTRUM ANALYZER

1/4
OP471

1/4
OP471

R1

100

e
V

OUT

S

Figure 9. Noise Voltage Density Test Circuit

Ê

=

Ë

e

OUT

ˆ

2

¯

()

REV. A

–9–

OP471

Noise Measurement - Current Noise Density

The test circuit shown in Figure 10 can be used to measure current
noise density. The formula relating the voltage output to current
noise density is:

nOUT

G

2

ˆ

40nV / Hz

-

˜

()

¯

R

S

e

Ê
Á

Ë

i

=

n

2

where:

G = gain of 10,000
R

= 100 kW source resistance

S

Capacative Load Driving and Power Supply Considerations

The OP471 is unity-gain stable and is capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP471.

R3

1.24k

R2

R1

100k

5

OP471
DUT

200

OP27E

R5

8.06k

R4

en OUT TO
SPECTRUM ANALYZER

GAIN = 10,000
V

= 15V

S

Figure 10. Current Noise Density Test Circuit

V

IN

R1

100*

*SEE TEXT

V+

OP471

*

V–

C2

10F

+

C3

0.1F

R2

C1

200pF

0.1F

R3

50

C4

10F

+

C5

PLACE SUPPLY DECOUPLING
CAPACITORS AT OP471

V

OUT

C

L

1000pF

Figure 11. Driving Large Capacitive Loads

In the standard feedback amplifier, the op amp’s output resistance
combines with the load capacitance to form a lowpass filter that

adds phase shift in the feedback network and reduces stability. A
simple circuit to eliminate this effect is shown in Figure 11. The
added components, C1 and R3, decouple the amplifier from the
load capacitance and provide additional stability. The values of
C1 and R3 shown in Figure 11 are for load capacitances of up
to 1,000 pF when used with the OP471.

In applications where the OP471’s inverting or noninverting inputs
are driven by a low source impedance (under 100 W) or connected
to ground, if V+ is applied before V–, or when V– is disconnected,
excessive parasitic currents will flow.

Most applications use dual tracking supplies and with the device
supply pins properly bypassed, power-up will not present a
problem. A source resistance of at least 100 W in series with all
inputs (Figure 11) will limit the parasitic currents to a safe level
if V– is disconnected. It should be noted that any source resistance,
even 100 W, adds noise to the circuit. Where noise is required to
be kept at a minimum, a germanium or Schottky diode can be
used to clamp the V– pin and eliminate the parasitic current
flow instead of using series limiting resistors. For most applica­tions, only one diode clamp is required per board or system.

R

f

OP471

8V/s

Figure 12. Pulsed Operation

Unity-Gain Buffer Applications

When Rf £ 100 W and the input is driven with a fast, large signal
pulse (>1 V), the output waveform will look as shown in Figure 12.

During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With R
is capable of handling the current requirements (I

≥ 500 W , the output

f

£ 20 mA at

L

10 V); the amplifier will stay in its active mode and a smooth
transition will occur.

When R

> 3 kW, a pole created by Rf and the amplifier’s input

f

capacitance (2.6 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel with

helps eliminate this problem.

R

f

APPLICATIONS
Low Noise Amplifier

A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 13. Amplifier noise, depicted in
Figure 14, is around 5 nV/÷Hz @ 1 kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200 W
resistors limit circulating currents and provide an effective output
resistance of 50 W. The amplifier is stable with a 10 nF capacitive
load and can supply up to 30 mA of output drive.

–10–

REV. A

High-Speed Differential Line Driver

The circuit of Figure 15 is a unique line driver widely used in
professional audio applications. With ± 18 V supplies, the line
driver can deliver a differential signal of 30 V p-p

into a 1.5 kW

load. The output of the differential line driver looks exactly like
a transformer. Either output can be shorted to ground without
changing the circuit gain of 5, so the amplifier can easily be set
for inverting, noninverting, or differential operation. The line
driver can drive unbalanced loads, like a true transformer.

+15V

V

IN

R1

50

R4

50

R7

50

R10
50

1/4
OP471E

–15V

1/4
OP471E

1/4
OP471E

1/4
OP471E

R2

5k

R5

5k

R8

5k

R11
5k

R3

200

R6

200

R9

200

R12

200

V

= 100V

OUT

IN

OP471

100

90

REFERRED TO INPUT

10

0%

NOISE DENSITY – 0.58nV/ Hz/DIV

Figure 14. Noise Density of Low-Noise Amplifier, G = 100

R4

10k

R11

R8

10k

R5

10k

50

R10
50

R14
1k

R13
10k

R12
1k

–OUT

+OUT

1/4
OP471

R2

2k

R3

2k

R7
2k

R6
2k

R9

10k

1/4
OP471

IN

R1

1/4

10k

OP471

Figure 13. Low-Noise Amplifier

High-Output Amplifier

The amplifier shown in Figure 16 is capable of driving 20 V p-p
into a floating 400 W load. Design of the amplifier is based on a
bridge configuration. A1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain inverter
which drives the load with help from A4. Gain of the high output
amplifier with the component values shown is 10, but can
easily be changed by varying R1 or R2.

+15V

C1

10F

+

C2

0.1F

R1

1k

1/4
OP471E

V

IN

C3

0.1F

C4

10F
+

A1

–15V

R2

9k

1/4
OP471E
A2

R3

50

R4

50

Figure 15. High-Speed Differential Line Driver

R5

5k

R6

5k

R7

50

R8

R

50

L

1/4

OP471E

A4

1/4

OP471E

A3

REV. A

Figure 16. High-Output Amplifier

–11–

OP471

Quad Programmable Gain Amplifier

The combination of the quad OP471 and the DAC8408, a quad
8-bit CMOS DAC, creates a space-saving quad programmable gain
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the fixed
DAC feedback resistor and the impedance the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is:

V

OUT

V

IN

= –

VINA

VINB

256

n

DAC-8408ET

RFBA

RFBB

V

DD

DAC A

DAC B

where n equals the decimal equivalent of the 8-bit digital code
present at the DAC. If the digital code present at the DAC
consists of all zeros, the feedback loop will be open causing the
op amp output to saturate. The 20 MW resistors placed in parallel
with the DAC feedback loop eliminates this problem with a very
small reduction in gain accuracy.

V

A

REF

+15V

1/4
OP470E

–15V

1/4
OP470E

V

A

OUT

B

V

OUT

I

OUT1A

I

OUT2A/2B

V

REF

I

OUT1B

R1
20M

B

R2
20M

VINC

VIND

DAC DATA BUS

PINS 9 (LSB) – 16 (MSB)

RFBC

DAC C

RFBD

DAC D

DGND

V

REF

I

OUT1C

I

OUT2C/2D

V

REF

I

OUT1D

C

R3
20M

1/4
OP470E

D

R4
20M

1/4
OP470E

Figure 17. Quad Programmable Gain Amplifier

V

C

OUT

V

D

OUT

–12–

REV. A

OP471

Low Phase Error Amplifier

The simple amplifier depicted in Figure 18 utilizes monolithic
matched operational amplifiers and a few resistors to substan­tially reduce phase error compared to conventional amplifier
designs. At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.

The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the feed­back loop of A1. Both op amps must be extremely well matched
in frequency response. At low frequencies, the A1 feedback loop
forces V2/(K1 + 1) = VIN. The A2 feedback loop forces Vo/(K1 +1)
= V

/(K1 + 1) yielding an overall transfer function of VO/VIN =

2

K1 + 1. The dc gain is determined by the resistor divider at
the output, V

, and is not directly affected by the resistor divider

O

around A2. Note that similar to a conventional single op amp
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10.

Figure 19 compares the phase error performance of the low
phase error amplifier with a conventional single op amp amplifier
and a cascaded two-stage amplifier. The low phase error amplifier
shows a much lower phase error, particularly for frequencies where
␻/␤␻

< 0.1. For example, phase error of –0.1∞ occurs at 0.002 ␻/␤␻

T

T

for the single op amp amplifier, but at 0.11 ␻/␤␻T for the low
phase error amplifier.

For more detailed information on the low phase error amplifier,
see Application Note AN-107.

R2

R2
K1

1/4
OP471E
A2

1/4
OP471E

(s) =

A1



T

s

V

IN

ASSUME: A1 AND A2 ARE MATCHED.

A

O

R1

VO = (K1 + 1) V

Figure 18. Low Phase Error Amplifier

0

–1

–2

–3

–4

SINGLE OP AMP

(CONVENTIONAL

DESIGN)

CASCADED

(TWO STAGES)

R2 = R1

V2

R1
K1

V

O

IN

–5

PHASE SHIFT – Degrees

–6

–7

0.001

LOW-PHASE ERROR

AMPLIFIER

0.01 0.1 10.005 0.05 0.5

FREQUENCY RATIO – 1/, /

Figure 19. Phase Error Comparison



T

REV. A

–13–

OP471

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead PDIP Package

0.795 (20.19)

0.725 (18.42)

14

1

PIN 1

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.100 (2.54)

0.022 (0.558)

0.014 (0.356)

14-Lead CERDIP Package

0.005 (0.13) MIN 0.098 (2.49) MAX

BSC

0.070 (1.77)

0.045 (1.15)

(N-14)

8

0.280 (7.11)

0.240 (6.10)

7

0.060 (1.52)

0.015 (0.38)

(Q-14)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.200 (5.08)

0.200 (5.08)

0.125 (3.18)

16

1

PIN 1

14

PIN 1

0.785 (19.94) MAX

MAX

0.023 (0.58)

0.014 (0.36)

0.4133 (10.50)

0.3977 (10.00)

0.050 (1.27)
BSC

8

0.310 (7.87)

17

0.100 (2.54) BSC

0.070 (1.78)

0.030 (0.76)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

16-Lead SOIC Package

(R-16)

9

0.2992 (7.60)

0.2914 (7.40)

8

0.1043 (2.65)

0.0926 (2.35)

0.4193 (10.65)

0.3937 (10.00)

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

15

0.008 (0.20)

0

0.0291 (0.74)

0.0098 (0.25)

 45

0.0118 (0.30)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

–14–

0.0125 (0.32)

0.0091 (0.23)

8
0

0.0500 (1.27)

0.0157 (0.40)

REV. A

OP471

Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Deleted WAFER TEST CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

REV. A

–15–

C00307–0–4/02(A)

–16–

PRINTED IN U.S.A.