Datasheet OP2177, OP4177 Datasheet (ANALOG DEVICES)

ⴚIN A
ⴙIN A

Vⴚ

OUT B
–IN B
+IN B

V+

1

45

8

OP2177

OUT A

查询OP1177供应商

Precision Low Noise, Low Input

a

FEATURES
Low Offset Voltage: 60 ␮V Max
Very Low Offset Voltage Drift: 0.7 ␮V/ⴗC Max
Low Input Bias Current: 2 nA Max

√

Low Noise: 8 nV/
CMRR, PSRR, and A
Low Supply Current: 400 ␮A/Amp
Dual Supply Operation: ⴞ2.5 V to ⴞ15 V
Unity Gain Stable
No Phase Reversal
Inputs Internally Protected Beyond Supply Voltage

APPLICATIONS
Wireless Base Station Control Circuits
Optical Network Control Circuits
Instrumentation
Sensors and Controls

Thermocouples
RTDs
Strain Bridges
Shunt Current Measurements

Precision Filters

Hz

> 120 dB Min

VO

Bias Current Operational Amplifiers

OP1177/OP2177/OP4177

FUNCTIONAL BLOCK DIAGRAM

8-Lead MSOP

(RM-Suffix)

1

NC

ⴚIN

OP1177

ⴙIN

Vⴚ

45

NC = NO CONNECT

8-Lead MSOP

(RM-Suffix)

8

NC
V+
OUT

NC

8-Lead SOIC

(R-Suffix)

NC

1

ⴚIN

2

+IN

3

Vⴚ

4

NC = NO CONNECT

8-Lead SOIC

(R-Suffix)

OUT A

1

ⴚIN A

2

3

+IN A

4

Vⴚ

OP1177

OP2177

NC

8

V+

7

OUT

6

NC

5

V+

8

7

OUT B

6

ⴚIN B

+IN B

5

GENERAL DESCRIPTION

The OPx177 family consists of very high-precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power con­sumption. Outputs are stable with capacitive loads of over
1,000 pF with no external compensation. Supply current is less
than 500 µA per amplifier at 30 V. Internal 500 Ω series resis-
tors protect the inputs, allowing input signal levels several volts
beyond either supply without phase reversal.

Unlike previous high-voltage amplifiers with very low offset voltages, the
OP1177 and OP2177 are available in the tiny MSOP 8-lead sur­face-mount package, while the OP4177 is available in TSSOP14.
Moreover, specified performance in the MSOP/TSSOP package is
identical to performance in the SOIC package.

OPx177 family offers the widest specified temperature range of
any high-precision amplifier in surface-mount packaging. All
versions are fully specified for operation from –40°C to +125°C for
the most demanding operating environments.

Applications for these amplifiers include precision diode power
measurement, voltage and current level setting, and level detec­tion in optical and wireless transmission systems. Additional
applications include line powered and portable instrumentation

14-Lead TSSOP

(RU-Suffix)

OUT A

–IN A
+IN A

+IN B
–IN B

OUT B

1

OP4177

V+

7

OUT D

14

–IN D
+IN D
V–
+IN C
–IN C

8

OUT C

OUT A

ⴚIN A

+IN A

+IN B

ⴚIN B

OUT B

1

2

3

4

V+

5

6

7

14-Lead SOIC

(R-Suffix)

OP4177
OP4177

OUT D

14

ⴚIN D

13

+IN D

12

Vⴚ

11

+IN C

10

9

ⴚIN C

8

OUT C

and controls—thermocouple, RTD, strain-bridge, and other
sensor signal conditioning—and precision filters.

The OP1177 (single) and the OP2177 (dual) amplifiers are
available in the 8-lead MSOP and 8-lead SOIC packages. The
OP4177 (quad) is available in 14-lead narrow SOIC and 14-lead
TSSOP packages. MSOP and TSSOP packages are available in
tape and reel only.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(@ VS = ⴞ5.0 V, VCM = 0 V, TA = 25ⴗC, unless

OP1177/OP2177/OP4177–SPECIFICATIONS

otherwise noted.)

Parameter Symbol Conditions Min Typ* Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP1177 V
OP2177/4177 V
OP1177/2177 V

OP4177 V
Input Bias Current I
Input Offset Current I

B

OS

OS

OS

OS

OS

–40°C < TA < +125°C 25 100 µV
–40°C < TA < +125°C 25 120 µV
–40°C < TA < +125°C –2 +0.5 +2 nA
–40°C < TA < +125°C –1 +0.2 +1 nA

15 60 µV
15 75 µV

Input Voltage Range –3.5 +3.5 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A

VO

= –3.5 V to +3.5 V 120 126 dB

CM

–40°C < T

< +125°C 118 125 dB

A

RL = 2 kΩ , VO = –3.5 V to +3.5 V 1,000 2,000 V/mV

Offset Voltage Drift

OP1177/OP2177 ∆V

/∆T –40°C < TA < +125°C 0.2 0.7 µV/°C

OS

OP4177 ∆VOS/∆T –40°C < TA < +125°C 0.3 0.9 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V
Output Voltage Low V
Output Current I

OH

OL

OUT

IL = 1 mA, –40°C < TA < +125°C +4 +4.1 V
IL = 1 mA, –40°C < TA < +125°C –4.1 –4 V
V

DROPOUT

< 1.2 V ±10 mA

POWER SUPPLY

Power Supply Rejection Ratio

OP1177 PSRR V

OP2177/OP4177 PSRR V

Supply Current/Amplifier I

SY

= ±2.5 V to ±15 V, 120 130 dB

S

–40°C < T

= ±2.5 V to ±15 V, 118 121 dB

S

–40°C < T

< +125°C 115 125 dB

A

< +125°C 114 120 dB

A

VO = 0 V 400 500 µA
–40°C < TA < +125°C 500 600 µA

DYNAMIC PERFORMANCE

Slew Rate SR R

= 2 kΩ 0.7 V/µs

L

Gain Bandwidth Product GBP 1.3 MHz

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

f = 1 kHz 7.9 8.5 nV/√Hz
f = 1 kHz 0.2 pA/√Hz

MULTIPLE AMPLIFIERS
CHANNEL SEPARATION C

S

DC 0.01 µV/V
f = 100 kHz –120 dB

*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors ’ data sheets as “typical,” give unrealistically

low estimates for parameters that can have both positive and negative values.

Specifications subject to change without notice.

–2–

REV. B

OP1177/OP2177/OP4177

ELECTRICAL CHARACTERISTICS

(@ VS = ⴞ15 V, VCM = 0 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ* Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP1177 V
OP2177/OP4177 V
OP1177/OP2177 V

OP4177 V
Input Bias Current I
Input Offset Current I

B

OS

OS

OS

OS

OS

–40°C < TA < +125°C 25 100 µV
–40°C < TA < +125°C 25 120 µV
–40°C < TA < +125°C –2 +0.5 +2 nA
–40°C < TA < +125°C –1 +0.2 +1 nA

15 60 µV
15 75 µV

Input Voltage Range –13.5 +13.5 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A

VO

= –13.5 V to +13.5 V

CM

–40°C < T

< +125°C 120 125 dB

A

RL = 2 kΩ , VO = –13.5 V to +13.5 V 1,000 3,000 V/mV

Offset Voltage Drift

OP1177/OP2177 ∆V

/∆T –40°C < TA < +125°C 0.2 0.7 µV/°C

OS

OP4177 ∆VOS/∆T –40°C < TA < +125°C 0.3 0.9 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage High V
Output Voltage Low V
Output Current I
Short Circuit Current I

OH

OL

OUT

SC

IL = 1 mA, –40°C < TA < +125°C +14 +14.1 V
IL = 1 mA, –40°C < TA < +125°C –14.1 –14 V
V

DROPOUT

< 1.2 V ±10 mA

±35 mA

POWER SUPPLY

Power Supply Rejection Ratio

OP1177 PSRR V

OP2177/OP4177 PSRR V

Supply Current/Amplifier I

SY

= ±2.5 V to ±15 V, 120 130 dB

S

–40°C < T

= ±2.5 V to ±15 V, 118 121 dB

S

–40°C < T

< +125°C 115 125 dB

A

< +125°C 114 120 dB

A

VO = 0 V 400 500 µA
–40°C < TA < +125°C 500 600 µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 0.7 V/µs
Gain Bandwidth Product GBP 1.3 MHz

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

f = 1 kHz 7.9 8.5 nV/√Hz
f = 1 kHz 0.2 pA/√Hz

MULTIPLE AMPLIFIERS
CHANNEL SEPARATION C

S

DC 0.01 µV/V
f = 100 kHz –120 dB

*Typical values cover all parts within one standard deviation of the average value. Average values, given in many competitors ’ data sheets as “typical,” give unrealistically

low estimates for parameters that can have both positive and negative values.

Specifications subject to change without notice.

REV. B

–3–

OP1177/OP2177/OP4177

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

S–

to V

S+

Differential Input Voltage . . . . . . . . . . . . . . ±Supply Voltage

Storage Temperature Range

R, RM, and RU Packages . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP1177/OP2177/OP4177 . . . . . . . . . . . –40°C to +125°C

Junction Temperature Range

R, RM, and RU Packages . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 10 sec) . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

OP1177ARM –40°C to +125°C 8-Lead MINI_SOIC RM-8 AZA
OP1177AR –40°C to +125°C 8-Lead SOIC SO-8
OP2177ARM –40°C to +125°C 8-Lead MINI_SOIC RM-8 B2A
OP2177AR –40°C to +125°C 8-Lead SOIC SO-8
OP4177AR –40°C to +125°C 14-Lead SOIC R-14
OP4177ARU –40°C to +125°C 14-Lead TSSOP RU-14

Package Type ␪

8-Lead MSOP (RM)

2

1

JA

␪

JC

Unit

190 44 °C/W
8-Lead SOIC (R) 158 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 240 43 °C/W

NOTES

1

θJA is specified for worst-case conditions, i.e., θ

in circuit board for surface-mount packages.

2

MSOP is only available in tape and reel.

is specified for device soldered

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP1177/OP2177/OP4177 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

Typical Performance Characteristics–

OP1177/OP2177/OP4177

50

VSY = ⴞ15V

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

ⴚ30 ⴚ20 ⴚ10

ⴚ40

INPUT OFFSET VOLTAGE – ␮V

02030

10

40

TPC 1. Input Offset Voltage
Distribution

1.8

VSY = ⴞ15V

1.6
T

= 25ⴗC

A

1.4

1.2

1.0

SOURCE

0.8

0.6

⌬OUTPUT VOLTAGE – V

0.4

0.2

SINK

0

0.001 0.01 10

0.1 1

LOAD CURRENT – mA

TPC 4. Output Voltage to Supply
Rail vs. Load Current

90

80

70

60

50

40

30

20

NUMBER OF AMPLIFIERS

10

0

0.05

0.15 0.25 0.35
TCVOS – ␮V/ⴗC

VSY = ⴞ15V

0.45 0.55

TPC 2. Input Offset Voltage
Drift Distribution

INPUT BIAS CURRENT – nA

ⴚ1

ⴚ2

ⴚ3

3

2

1

0

ⴚ50

0 50 100

TEMPERATURE – ⴗC

VSY = ⴞ15V

TPC 5. Input Bias Current vs.
Temperature

150

140

VSY = ⴞ15V

120

100

80

60

40

NUMBER OF AMPLIFIERS

20

0

0.1 0.2 0.3 0.5

00.4
INPUT BIAS CURRENT – nA

0.6

0.7

TPC 3. Input Bias Current
Distribution

60

50

40

30

GAIN

20

10

OPEN-LOOP GAIN – dB

0

ⴚ10

ⴚ20

100k 1M 10M

FREQUENCY – Hz

VSY = ⴞ15V

= 0

C

L

=

R

L

PHASE

TPC 6. Open-Loop Gain and
Phase Shift vs. Frequency

0

45

90

135

180

PHASE SHIFT – Degrees

120

100

80

60

= 100

A

V

40

AV = 10

20

0

AV = 1

ⴚ20

CLOSED-LOOP GAIN – dB

ⴚ40

ⴚ60

ⴚ80

1k 10k 100M

100k 1M 10M

FREQUENCY – Hz

VSY = ⴞ15V

= 4mV p-p

V

IN

= 0

C

L

=

R

L

TPC 7. Closed-Loop Gain vs.
Frequency

500

450

400

350

300

250

200

150

OUTPUT IMPEDANCE – ⍀

100

50

0

100 1k 10k

A

FREQUENCY – Hz

= 100

V

AV = 10

VSY = ⴞ15V

= 50mV p-p

V

IN

AV = 1

100k 1M

TPC 8. Output Impedance vs.
Frequency

VSY = ⴞ15V
C

= 300pF

L

= 2k⍀

R

L

= 4V

V

IN

A

= 1

V

VOLTAGE – 1V/DIV

GND

TIME – 100␮s/DIV

TPC 9. Large Signal Transient
Response

REV. B

–5–

OP1177/OP2177/OP4177

k

VSY = ⴞ15V
C

= 1,000pF

L

= 2k⍀

R

L

= 100mV

V

IN

A

= 1

V

GND

VOLTAGE – 100mV/DIV

TIME – 100␮s/DIV

TPC 10. Small Signal Transient
Response

15V

0V

OUTPUT

VSY = ⴞ15V

= 10k⍀

R

L

A

= ⴚ100

V

= 200mV

V

IN

0V

50

VSY = ⴞ15V

45

R

= 2k⍀

L

= 100mV p-p

V

IN

40

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT – %

5

0

110 10

CAPACITANCE – pF

100

+OS

ⴚOS

1k

TPC 11. Small Signal Overshoot vs.
Load Capacitance

CMRR – dB

140

120

100

80

60

40

VSY = ⴞ15V

VSY = ⴞ15V

= 10k⍀

R

L

= ⴚ100

A

V

V

= 200mV

0V

IN

ⴚ15V

OUTPUT

+200mV

0V

INPUT

TIME – 10␮s/DIV

TPC 12. Positive Overvoltage
Recovery

PSRR – dB

140

120

100

80

60

40

+PSRR

VSY = ⴞ15V

ⴚPSRR

ⴚ200mV

INPUT

TIME – 4␮s/DIV

TPC 13. Negative Overvoltage
Recovery

VSY = ⴞ15V

– 0.2␮V/DIV

NOISE

V

TIME – 1s/DIV

TPC 16. 0.1 Hz to 10 Hz Input
Voltage Noise

20

0

100 1k 100k 1M

10 10k 10M

FREQUENCY – Hz

TPC 14. CMRR vs. Frequency

18

VSY = ⴞ15V

16

14

12

10

8

6

4

VOLTAGE NOISE DENSITY – nV/ Hz

2

0 25050 100 150 200

FREQUENCY – Hz

TPC 17. Voltage Noise Density

20

0

100 1k 100k 1M

10 10k 10M

FREQUENCY – Hz

TPC 15. PSRR vs. Frequency

SHORT CIRCUIT CURRENT – mA

35

30

25

20

15

10

5

0

ⴚ50

ⴙI

SC

ⴚI

SC

0 50 100

TEMPERATURE – ⴗC

V

SY

= ⴞ15V

TPC 18. Short Circuit Current vs.
Temperature

150

–6–

REV. B

OP1177/OP2177/OP4177

14.40

14.35

14.30

14.25

14.20

14.15

14.10

OUTPUT VOLTAGE SWING – V

14.05

14.00
ⴚ50

V

= ⴞ15V

SY

ⴙV

OH

0 50 100

TEMPERATURE – ⴗC

ⴚV

OL

150

TPC 19. Output Voltage Swing vs.
Temperature

133

VSY = ⴞ15V

150

CMRR – dB

132

131

130

129

128

127

126

125

124

123

ⴚ50

0 50 100

TEMPERATURE – ⴗC

TPC 22. CMRR vs. Temperature

0.5

0.4

0.3

0.2

0.1

0

ⴚ0.1

ⴚ0.2

⌬OFFSET VOLTAGE – ␮V

ⴚ0.3

ⴚ0.4

ⴚ0.5

20 40 60 80 120

0 140

TIME FROM POWER SUPPLY TURN-ON – Sec

VSY = ⴞ15V

100

TPC 20. Warm-Up Drift

PSRR – dB

133

132

131

130

129

128

127

126

125

124

123

ⴚ50

0 50 100

TEMPERATURE – ⴗC

VSY = ⴞ15V

TPC 23. PSRR vs. Temperature

150

18

16

14

12

10

8

6

4

INPUT OFFSET VOLTAGE – ␮V

2

0
ⴚ50

TPC 21.|V

50

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

ⴚ4040ⴚ30 ⴚ20 ⴚ10

0 50 100

TEMPERATURE – ⴗC

|

OS

VSY = ⴞ5V

VSY = ⴞ15V

INPUT OFFSET VOLTAGE – ␮V

VSY = ⴞ15V

vs. Temperature

02030

10

TPC 24. Input Offset Voltage
Distribution

150

1.4

VSY = ⴞ5V

1.2
= 25ⴗC

T

A

1.0

0.8

0.6

0.4

⌬OUTPUT VOLTAGE – V

0.2

0

0.001 0.01 10

SINK

SOURCE

0.1 1

LOAD CURRENT – mA

TPC 25. Output Voltage to
Supply Rail vs. Load Current

60

50

40

30

GAIN

20

10

OPEN-LOOP GAIN – dB

0

ⴚ10

ⴚ20

100k 1M

FREQUENCY – Hz

VSY = ⴞ5V

= 0

C

L

=

R

L

PHASE

0

45

90

135

180

225

270

10M

TPC 26. Open-Loop Gain and Phase
Shift vs. Frequency

PHASE SHIFT – Degrees

120

100

80

60

AV = 100

40

AV = 10

20

0

AV = 1

ⴚ20

CLOSED-LOOP GAIN – dB

ⴚ40

ⴚ60

ⴚ80

1k 10k 100M

100k

FREQUENCY – Hz

VSY = ⴞ5V

= 4mV p-p

V

IN

= 0

C

L

=

R

L

1M 10M

TPC 27. Closed-Loop Gain vs.
Frequency

REV. B

–7–

OP1177/OP2177/OP4177

k

500

450

400

350

300

250

200

150

OUTPUT IMPEDANCE – ⍀

100

50

0

100 1k 10k

A

V

FREQUENCY – Hz

AV = 10

= 100

VSY = ⴞ5V
V

= 50mV p-p

IN

AV = 1

100k 1M

TPC 28. Output Impedance vs.
Frequency

50

VSY = ⴞ5V

45

= 2k⍀

R

L

= 100mV

V

IN

40

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT – %

5

0

110 10

CAPACITANCE – pF

100

+OS

ⴚOS

1k

VSY = ⴞ5V
C

= 300pF

L

= 2k⍀

R

L

= 1V

V

IN

A

= 1

V

VOLTAGE – 1V/DIV

GND

TIME – 100␮s/DIV

TPC 29. Large Signal
Transient Response

VSY = ⴞ5V

= 10k⍀

R

L

A

= ⴚ100

V

0V

= 200mV

V

IN

ⴚ5V

OUTPUT

+200mV

0V

INPUT

TIME – 4␮s/DIV

VSY = ⴞ5V
C

= 1,000pF

L

= 2k⍀

R

L

V

= 100mV

IN

= 1

A

V

GND

VOLTAGE – 50mV/DIV

TIME – 10␮s/DIV

TPC 30. Small Signal
Transient Response

VSY = ⴞ5V

= 10k⍀

R

L

= ⴚ100

A

V

V

= 200mV

IN

ⴚ200mV

5V

0V

0V

OUTPUT

INPUT

TIME – 4␮s/DIV

TPC 31. Small Signal Overshoot vs.
Load Capacitance

OUTPUT

VS = ⴞ5V

= 1

A

V

= 10k⍀

R

L

INPUT

GND

VOLTAGE – 2V/DIV

TIME – 200␮s/DIV

TPC 34. No Phase Reversal

TPC 32. Positive Overvoltage
Recovery

140

120

100

80

60

CMRR – dB

40

20

0

100 1k 100k 1M

10 10k 10M

FREQUENCY – Hz

VSY = ⴞ5V

TPC 35. CMRR vs. Frequency

TPC 33. Negative Overvoltage
Recovery

200

180

160

140

120

100

80

PSRR – dB

60

40

20

0

10 10k 10M

100 1k 100k 1M

ⴚPSRR

+PSRR

FREQUENCY – Hz

VSY = ⴞ5V

TPC 36. PSRR vs. Frequency

–8–

REV. B

OP1177/OP2177/OP4177

VSY = ⴞ5V

– 0.2␮V/DIV

NOISE

V

TIME – 1s/DIV

TPC 37. 0.1 Hz to 10 Hz Input Voltage
Noise

4.40

4.35

4.30

4.25

4.20

4.15

4.10

OUTPUT VOLTAGE SWING – V

4.05

4.00
ⴚ50

V

= ⴞ5V

SY

ⴙV

OH

0 50 100

TEMPERATURE – ⴗC

ⴚV

OL

150

TPC 40. Output Voltage Swing vs.
Temperature

18

VSY = ⴞ5V

16

14

12

10

8

6

4

VOLTAGE NOISE DENSITY – nV/ Hz

2

0 25050 100 150 200

FREQUENCY – Hz

TPC 38. Voltage Noise Density

25

VSY = ⴞ5V

20

15

10

5

INPUT OFFSET VOLTAGE – ␮V

0

ⴚ50

TPC 41.|V

0 50 100

TEMPERATURE – ⴗC

|

vs. Temperature

OS

150

SHORT CIRCUIT CURRENT – mA

35

30

25

20

15

10

5

0

ⴚ50

ⴙI

SC

ⴚI

SC

0 50 100

TEMPERATURE – ⴗC

V

= ⴞ5V

SY

TPC 39. Short Circuit Current vs.
Temperature

600

500

400

300

200

SUPPLY CURRENT – ␮A

100

0

ⴚ50

VSY = ⴞ15V

VSY = ⴞ5V

0 50 100

TEMPERATURE – ⴗC

TPC 42. Supply Current vs.
Temperature

150

150

450

TA = 25ⴗC

400

350

300

250

200

150

SUPPLY CURRENT – ␮A

100

50

0

05 35

10 15 20 25 30

SUPPLY VOLTAGE – V

TPC 43. Supply Current vs. Supply
Voltage

0

ⴚ20

ⴚ40

ⴚ60

ⴚ80

ⴚ100

ⴚ120

CHANNEL SEPARATION – dB

ⴚ140

ⴚ160

10 100 1M

1k 10k 100k

FREQUENCY – Hz

TPC 44. Channel Separation vs.
Frequency

REV. B

–9–

OP1177/OP2177/OP4177

FUNCTIONAL DESCRIPTION

OP1177 is the fourth generation of ADI’s industry standard OP07
amplifier family. OP1177 is a very high-precision, low-noise opera­tional amplifier with the highly desirable combination of extremely
low offset voltage and very low input bias currents. Unlike JFET
amplifiers, the low bias and offset currents are relatively insensitive
to ambient temperatures, even up to 125°C.

For the first time, Analog Devices’ proprietary process technology
and linear design expertise have produced a high-voltage
amplifier with superior performance to the OP07, OP77, and
OP177 in a tiny MSOP 8-lead package. Despite its small size
the OP1177 offers numerous improvements including low wide­band noise, very wide input and output voltage range, lower
input bias current, and complete freedom from phase inversion.

OP1177 has the widest specified operating temperature range of
any similar device in a plastic surface-mount package. This is
increasingly important as PC board and overall system sizes
continue to shrink, causing internal system temperatures to rise.
Power consumption is reduced by a factor of four from the OP177

Where BW is the bandwidth in Hertz.

NOTE: The above analysis is valid for frequencies larger than
50 Hz. When considering lower frequencies, flicker noise (also
known as 1/f noise) must be taken into account.

For a reference on noise calculations refer to Bandpass KRC or
Sallen-Key Filter section.

Gain Linearity

Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range will be. This is especially true for circuits with
high closed-loop gains.

The OP1177 has excellent gain linearity even with heavy loads,
shown in Figure 1. Compare its performance to the OPA277,
shown in Figure 2. Both devices were measured under identical
conditions with R
distortion at lower voltages. It was compared to the OPA277 at
several supply voltages and various loads. Its performance exceeded
that of its counterpart by far.

while bandwidth and slew rate increase by a factor of two. The low
power dissipation and very stable performance versus temperature
also act to reduce warm-up drift errors to insignificant levels.

Open-loop gain linearity under heavy loads is superior to competitive
parts like OPA277, improving dc accuracy and reducing distortion
in circuits with high closed-loop gains. Inputs are internally protected
from overvoltage conditions referenced to either supply rail.

Like any high-performance amplifier, maximum performance is
achieved by following appropriate circuit and PC board guidelines.
The following sections provide practical advice on getting the most
out of the OP1177 under a variety of application conditions.

Total Noise Including Source Resistors

The low input current noise and input bias current of the OP1177
make it useful for circuits with substantial input source resistance.
Input offset voltage increases by less than 1 µV max per 500 Ω
of source resistance.

The total noise density of the OP1177 is:

e e i R kTR

n

TOTAL

,

2

=+

nnS S

2

+

()

4

Where, en is the input voltage noise density

i

is the input current noise density

n

is the source resistance at the noninverting terminal

R

S

k is Boltzman’s constant (1.38  10

–23

J/K)

T is the ambient temperature in Kelvin (T = 273 + °C)

For R

< 3.9 kΩ, en dominates and

S

ee

n TOTAL n,

≈

For 3.9 kΩ < RS < 412 kΩ, voltage noise of the amplifier, current
noise of the amplifier translated through the source resistor, and
thermal noise from the source resistor all contribute to the total
noise.

For R

> 412 kΩ, the current noise dominates and

S

eiR

n TOTAL n S,

≈

The total equivalent rms noise over a specific bandwidth is
expressed as:

Input Overvoltage Protection

When their input voltage exceeds the positive or negative supply
voltage, most amplifiers require external resistors to protect them
from damage.

The OP1177 has internal protective circuitry that allows volt­ages as high as 2.5 V beyond the supplies to be applied at the
input of either terminal without any harmful effects.

Ee BW

=

()

n n TOTAL

,

SCALE – ␮V

SCALE – ␮V

NEED LABEL FOR THIS AXIS

= 2 kΩ. The OP2177 (dual) has virtually no

L

VSY = ⴞ15V

= 2k⍀

R

L

OP1177

SCALE – V

Figure 1. Gain Linearity

VSY = ⴞ15V

= 2k⍀

R

L

OPA277

SCALE – V

Figure 2. Gain Linearity

–10–

REV. B

OP1177/OP2177/OP4177

Use an additional resistor in series with the inputs if the voltage
will exceed the supplies by more than 2.5 V. The value of the
resistor can be determined from the formula:

VV

−

()

R

IN S

+≤5005Ω

S

mA

With the OP1177’s low input offset current of <1 nA max, placing
a 5 kΩ resistor in series with both inputs adds less than 5 µV to
input offset voltage and has a negligible impact on the overall
noise performance of the circuit.

5 kΩ will protect the inputs to more than 27 V beyond either supply.
Refer to the THD + N section for additional information on
noise versus source resistance.

Output Phase Reversal

Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase reversal
when the voltage applied to the input is greater than the maxi­mum common-mode voltage. In some instances this can cause
permanent damage to the amplifier. In feedback loops, it can
result in system lockups or equipment damage. The OP1177 is
immune to phase reversal problems even at input voltages beyond
the supplies.

V

= ⴞ10V

SY

= 1

A

V

V

IN

V

OUT

VO LTAG E – 5V/DIV

demanded by the circuit’s transfer function lies beyond the maxi­mum output voltage capability of the amplifier. A 10 V input
applied to an amplifier in a closed-loop gain of 2 will demand an
output voltage of 20 V. This is beyond the output voltage range of
the OP1177 when operating at ±15 V supplies and will force the
output into saturation.

Recovery time is important in many applications, particularly where
the op amp must amplify small signals in the presence of large
transient voltages.

R2

100k⍀

Vⴚ

200mV

R1

1k⍀

+

ⴚ

2

3

4

OP1177

7

V+

1

10k⍀

V

OUT

Figure 4. Test Circuit for Overload Recovery Time

TPC 12 shows the positive overload recovery time of the OP1177.
The output recovers in less than 4 µs after being overdriven by
more than 100%.

The negative overload recovery of the OP1177 is 1.4 µs as seen
in TPC 13.

THD + Noise

The OP1177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OP1177 a great choice for
high closed-loop gain precision circuits.

Figure 5 shows that the OP1177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.

0.1
VSY = ⴞ15V

= 10k⍀

R

L

BW = 22kHz

TIME – 400␮s/DIV

Figure 3. No Phase Reversal

Settling Time

Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in mea­surement and control circuits where amplifiers buffer A/D inputs
or DAC outputs.

To minimize settling time in amplifier circuits, use proper bypassing
of power supplies and an appropriate choice of circuit components.
Resistors should be metal film types as these have less stray
capacitance and inductance than their wire-wound counterparts.
Capacitors should be polystyrene or polycarbonate types to
minimize dielectric absorption.

The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OP1177
has a settling time of about 45 µs to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.

Overload Recovery Time

Overload recovery is defined as the time it takes the output voltage
of an amplifier to recover from a saturated condition to its linear
response region. A common example is where the output voltage

REV. B

–11–

0.01

THD + N – %

0.001

0.0001
20 100

FREQUENCY – Hz

1k

6k

Figure 5. THD + N vs. Frequency

Capacitive Load Drive

OP1177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external com­pensation, the OP1177 will safely drive capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.

In this case, a “snubber network” is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the resistor R

is not inside the feedback loop.

S

OP1177/OP2177/OP4177

Figure 6 is a scope photograph of the output of the OP1177 in
response to a 400 mV pulse. The load capacitance is 2 nF. The
circuit is configured in positive unity gain, the worst-case condition
for stability.

Placing an R-C network, as shown in Figure 8, parallel to the
load capacitance C
values of C

L

There is no ringing and overshoot is reduced from 27% to 5%
using the snubber network.

Optimum values for R
capacitive loads up to 200 nF. Values for other capacitive loads
can be determined experimentally.

Table I. Optimum Values for Capacitive Loads

CL (nF) RS (⍀)C

10 20 0.33 µF
50 30 6.8 nF
200 200 0.47 µF

0

0

0

0

0

0

GND

VO LTAG E – 200mV/DIV

0

0

0

000

Figure 6. Capacitive Load Drive without Snubber

0

0

0

0

0

0

GND

VO LTAG E – 200mV/DIV

0

0

0

000

Figure 7. Capacitive Load Drive with Snubber

will allow the amplifier to drive higher

L

without causing oscillation or excessive overshoot.

and CS are tabulated in Table I for several

S

S

V

= ⴞ5V

SY

= 10k⍀

R

L

= 2nF

C

L

00000000

00000000

TIME – 10␮s/DIV

TIME – 10␮s/DIV

V

SY

= 10k⍀

R

L

= 200⍀

R

S

= 2nF

C

L

= 0.47␮F

C

S

= ⴞ5V

Vⴚ

4

2

400mV

1

3

+

ⴚ

OP1177

7

V+

R

S

C

S

V

OUT

C

L

Figure 8. Snubber Network Configuration

CAUTION: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.

Stray Input Capacitance Compensation

The effective input capacitance in an op amp circuit, Ct, con­sists of three components. These are: the internal differential
capacitance between the input terminals, the internal common
mode capacitance of each input to ground, and the external
capacitance including parasitic capacitance. In the circuit of
Figure 9, the closed-loop gain increases as the signal frequency
increases.

The transfer function of the circuit is:

2

R

1

11++

sC R

()

1

R

t

indicating a zero at:

RR

+

s

=

21

RRC

21

=

t

1

RRC

2π 1// 2

()

t

Depending on the value of R1 and R2, the cutoff frequency of the
closed-loop gain may be well below the crossover frequency. In
this case, the phase margin, Φ

can be severely degraded resulting

m,

in excessive ringing or even oscillation.

A simple way to overcome this problem is to insert a capacitor in
the feedback path as shown in Figure 10.

The resulting pole can be positioned to adjust the phase margin.

Setting C

= (R1/R2)Ct, achieves a phase margin of 90°.

f

R1

+

V1

–

C

t

R2

Vⴚ

4

2

1

3

OP1177

7

V+

V

OUT

Figure 9. Stray Input Capacitance

C

f

R1

R2

–12–

+

V1

–

C

t

Vⴚ

4

2

1

3

7

OP1177

V+

V

OUT

Figure 10. Compensation Using Feedback Capacitor

REV. B

OP1177/OP2177/OP4177

Reducing Electromagnetic Interference

A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.

In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the amplifier’s CMRR.

This is usually achieved by inserting a capacitor between the inputs
of the amplifier as shown in Figure 11. However, this method may
also cause instability depending on the value of capacitance.

R1

+

V1

–

C

R2

Vⴚ

4

2

1

3

OP1177

7

V+

V

OUT

Figure 11. EMI Reduction

Placing a resistor in series with the capacitor (Figure 12) increases
the dc loop gain and reduces the output error. Positioning the
breakpoint (introduced by R-C) below the secondary pole of the
op amp improves the phase margin and hence stability.

R can be chosen independently of C for a specific phase margin
according to the formula

=−+

ajf




2



R

2

R



R

2

1




R

1

where a is the open-loop gain of the amplifier and f2 is the frequency
at which the phase of a = Φ

– 180°.

m

R2

A variation in temperature across the PC board can cause a
mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in thermal
voltage errors. To minimize these thermocouple effects, resistors
should be oriented so heat sources warm both ends equally.
Input signal paths should contain matching numbers and types
of components where possible in order to match the number
and type of thermocouple junctions. For example, dummy com­ponents such as zero value resistors can be used to match real
resistors in the opposite input path. Matching components
should be located in close proximity and should be oriented in
the same manner. Leads should be of equal length so that ther­mal conduction is in equilibrium. Heat sources on the PC board
should be kept as far away from amplifier input circuitry as
practical.

The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.

Difference Amplifiers

Difference amplifiers are used in high-accuracy circuits to improve
the common-mode rejection ratio (CMRR).

R2

100k⍀

Vⴚ

V1

V2

R1

R3 = R1

R4
R3

4

2

1

3

OP1177

7

V+

R4 = R1

R2

=

R1

V

OUT

R1

R

+

V1

C

–

Vⴚ

4

2

1

3

7

OP1177

V+

V

OUT

Figure 12. Compensation Using Input RC Network

Proper Board Layout

The OP1177 is a high-precision device. In order to ensure optimum
performance at the PC board level, care must be taken in the design
of the board layout.

To avoid leakage currents, the surface of the board should be kept
clean and free of moisture. Coating the surface creates a barrier to
moisture accumulation and helps reduce parasitic resistance on
the board.

Keeping supply traces short and properly bypassing the power
supplies will minimize power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as pos­sible to the device supply pins. Stray capacitances are a concern
at the output and the inputs of the amplifier. It is recommended
that signal traces be kept at least 5 mm from supply lines to
minimize coupling.

Figure 13. Difference Amplifier

In the single amplifier instrumentation amplifier (circuit of
Figure 13), where:

RRR

4

=

R

321

R

V

2

VV

=−

O

()

21

R

1

a mismatch between the ratio R2/R1 and R4/R3 will cause the
common-mode rejection ratio to be reduced. To better under­stand this effect, consider the following:

By definition:

CMRR

A

DM

=

A

CM

where ADM is the differential gain and ACM is the common-mode gain.

V

A

DM

VVVV VV

=− = +

DIFF CM

O

==and

V

DIFF

12 12

A

and

V

CM

O

V

CM

1

()

2

REV. B

–13–

OP1177/OP2177/OP4177

In order for this circuit to act as a difference amplifier, its output
must be proportional to the differential input signal.

From Figure 13,





1









R

=−

2









R

1

V

O





V

+

12





1












R

2

+







R

1



V





R

3

+






R

4



Arranging terms and combining the equations above yields:

RR RR RR

++

CMRR

41 32242

=

RR RR

241223

−

(1)

The sensitivity of CMRR with respect to the R1 is obtained by
taking the derivative of CMRR, in Equation 1, with respect to R1.

δ

CMRR

=

δ

RR

δ



δ

δδCMRR

RR




214 22 3

14

RR R R

−

=

R

1

RR RR

224 23

+

RR R R11

214 22 3

+

−

1

RR

223

()

2

−

RR

14






Assuming that: R1 ≈ R2 ≈ R3 ≈ R4 ≈ R and
R(1 – δ) < R1, R2, R3, R4 < R(1 + δ).

The worst-case CMRR error arises when:

R1

= R4 = R(1 + δ) and R2 = R3 = R(1 – δ). Plugging these

values into Equation 1 yields:

CMRR

MIN

1

≅

2δ

where δ is the tolerance of the resistors.

Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the op amp).

Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. On the other hand, using 0.1% tolerance
resistors would result in a common-mode rejection ratio of at
least 54 dB (assuming that the op amp CMRR  54 dB).

With the CMRR of OP1177 at 120 dB minimum, the resistor
match will be the limiting factor in most circuits. A trimming
resistor can be used to further improve resistor matching and
CMRR of the difference amp circuit.

A High-Accuracy Thermocouple Amplifier

A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage

VTT

=−

α

()

TC R

J

where TJ is the temperature at the measurement of the hot junction,
T

is the one at the cold junction, and  is the Seebeck coefficient

R

specific to the dissimilar metals used in the thermocouple. V

TC

is the

thermocouple voltage. VTC becomes larger with increasing temperature.

Maximum measurement accuracy requires cold junction compen­sation of the thermocouple as described below.

To perform the cold junction compensation, apply a copper
wire short across the terminating junctions (inside the isothermal
block) simulating a 0°C point. Adjust the output voltage to zero
using the trimming resistor R5 and then remove the copper wire.

The OP1177 is an ideal amplifier for thermocouple circuits since
it has a very low offset voltage, excellent PSSR and CMRR, and
low noise at low frequencies.

It can be used to create a thermocouple circuit with great linearity.
Resistors R1 and R2 and diode D1 shown in Figure 14 are
mounted in an isothermal block.

V

CC

2

3

ⴚ15V

R9

200k⍀

+15V

4

7

OP1177

0.1␮F

10␮F

1

10␮F

0.1␮F

V

OUT

2.2␮F

(ⴚ)

T

J

(+)

C1

ADR293

D1

D1

TR

V

TC

TR

ISOTHERMAL

BLOCK

R3
47k⍀

R2

4.02k⍀

Cu

Cu

10␮F

R1
50⍀

R8

1k⍀

R5

100⍀

R7

80.6k⍀

R6
50⍀

R4
50⍀

10␮F

Figure 14. Type K Thermocouple Amplifier Circuit

Low Power Linearized RTD

A common application for a single element varying bridge is an
RTD thermometer amplifier as shown in Figure 15. The excita­tion is delivered to the bridge by a 2.5 V reference applied at the
top of the bridge.

RTDs may have thermal resistance as high as 0.5°C to 0.8°C
per mW. In order to minimize errors due to resistor drift, the
current through each leg of the bridge must be kept low. In this
circuit, the amplifier supply current flows through the bridge.

However, at the OP1177 maximum supply current of 600 µA,
the RTD dissipates less than 0.1 mW of power even at the high­est resistance. Errors due to power dissipation in the bridge are
kept under 0.1°C.

Calibration of the bridge can be made at the minimum value of
temperature to be measured by adjusting R

until the output is zero.

P

To calibrate the output span, set the full-scale and linearity pots
to midpoint and apply a 500°C temperature to the sensor or
substitute the equivalent 500°C RTD resistance.

Adjust the full-scale pot for a 5 V output. Finally, apply 250°C
or the equivalent RTD resistance and adjust the linearity pot for

2.5 V output.
The circuit achieves better than ±0.5°C accuracy after adjustment.

–14–

REV. B

OP1177/OP2177/OP4177

+15V

0.1␮F

100⍀

RTD

ADR421

4.12k⍀

2

3

4.12k⍀

100⍀

100⍀ 20⍀

ⴚ15V

4

1

1/2 OP2177

8

+15V

4.37k⍀

6

5

V

OUT

ⴚ15V

4

7

1/2 OP2177

8

+15V

49.9k⍀

500⍀

200⍀

V

5k⍀

OUT

Figure 15. Low Power Linearized RTD Circuit

Single Op Amp Bridge

The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal condi­tioning. It is often more economical to use a single bridge op amp
as opposed to an instrumentation amplifier.

In the circuit of Figure 16, the output voltage at the op amp is:




R

2

V

O REF



=



R











V






R

1

R



R

++

1




R



1




2

















+

1δδ



()








where δ = ∆R/R is the fractional deviation of the RTD resis­tance with respect to the bridge resistance due to the change in
temperature at the RTD.

For δ << 1, the expression above becomes:









2

R

V

O REF REF

With V

V

≅











R

constant, the output voltage is linearly proportional to

REF

RRR



1

++






δ

11

=






2

R









2

R











R





1

R

1

+









2

R







1

R

+









2

R

δ

V




δ with a gain factor of:







R

1











R

2



R

F

Vⴚ

4

2

1

3

7

OP1177

V+

R

F

V

OUT

0.1␮F

V

15V

ADR421

REF



R




R(1+␦)







2











R





R

1

+

1

RR

R

+




R

2

REALIZATION OF ACTIVE FILTERS
Bandpass KRC or Sallen-Key Filter

The low offset voltage and the high CMRR of the OP1177 make
it an excellent choice for precision filters such as the KRC filter
shown in Figure 17. This filter type offers the capability to tune
the gain and the cutoff frequency independently.

Since the common-mode voltage into the amplifier varies with the
input signal in the KRC filter circuit, a high CMRR is required to
minimize distortion. Also, the low offset voltage of the OP1177 allows
a wider dynamic range when the circuit gain is chosen to be high.

The circuit of Figure 17 consists of two stages. The first stage is
a simple high-pass filter whose corner frequency f

is:

C

1

2 1212π CC RR

(2)

and whose

R

QK

=

1

R

2

(3)

where K is the dc gain.

Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to:

1

π

CRR

212

The value of Q determines the peaking of the gain versus frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.

1

Setting

Q =

,

2

yields minimum gain peaking and minimum ringing.

Determine values for R1 and R2 by use of Equation 3.

For

, R1/R2 = 2 in the circuit example. Pick R1 = 5 kΩ

2

1

Q =

and R2 = 10 kΩ for simplicity.

The second stage is a low-pass filter whose corner frequency can
be determined in a similar fashion. For R3

1

==

f

C

π

2

R

and

3

C

4

C

Q

= R4 = R.

123

C

4

C

Channel Separation

Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to prevent
feedthrough of signals from one amplifier channel to the other. As
a result the OP2177 has an impressive channel separation of
greater than –120 dB for frequencies up to 100 kHz and greater
than –115 dB for signals up to 1 MHz.

REV. B

Figure 16. Single Bridge Amplifier

–15–

OP1177/OP2177/OP4177

R2

10k⍀

C3

680pF

V1

C2

10nFC110nF

+

–

R1
20k⍀

6

5

Figure 17. Two-Stage Band-Pass Filter

10k⍀

50mV

Vⴚ

4

6

7

5

+

V1

–

1/2 OP2177

8

V+

1/2 OP2177

Vⴚ

4

1

8

V+

Figure 18. Channel Separation Test Circuit

Vⴚ

4

8

V+

100⍀

2

3

7

1/2 OP2177

Vⴚ

4

R3

33k⍀

R4

33k⍀

330pF

C4

2

3

1

1/2 OP2177

8

V+

V

OUT

SPICE Model

The spice macro-model for the OP1177 can be downloaded from
the Analog Devices web site at www.analog.com. This model will
accurately simulate a number of parameters, both dc and ac.

References on Noise Dynamics and Flicker Noise

S. Franco, Design with Operational Amplifiers and Analog Integrated
Circuits, McGraw-Hill 1998.

The Best of Analog Dialogue, from Analog Devices.

–16–

REV. B

14 8

71

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.3444 (8.75)

0.3367 (8.55)

0.050 (1.27)
BSC

SEATING
PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

8ⴗ
0ⴗ

0.0196 (0.50)

0.0099 (0.25)

ⴛ 45ⴗ

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead MINI_SOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

OP1177/OP2177/OP4177

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

85

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

0.199 (5.05)

0.187 (4.75)

41

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

14-Lead SOIC

(R-14)

0.120 (3.05)

0.112 (2.84)

33ⴗ
27ⴗ

0.028 (0.71)

0.016 (0.41)

REV. B

–17–

OP1177/OP2177/OP4177

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead TSSOP

(RU-14)

0.201 (5.10)

0.193 (4.90)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

14

0.0256

PIN 1

PLANE

(0.65)

BSC

0.1968 (5.00)

0.1890 (4.80)

8

0.0500
(1.27)

BSC

8

0.177 (4.50)

0.169 (4.30)

71

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

8-Lead SOIC

5

0.2440 (6.20)

41

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

(R-8)

0.0098 (0.25)

0.0075 (0.19)

8ⴗ
0ⴗ

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.028 (0.70)

0.020 (0.50)

x 45°

0.0500 (1.27)

0.0160 (0.41)

–18–

REV. B

OP1177/OP2177/OP4177

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Added OP4177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Global

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ELECTRICAL CHARACTERISTICS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

11/01—Data Sheet changed from REV. 0 to REV. A.

Edit to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

REV. B

–19–

C02627–0–4/02(B)

–20–

PRINTED IN U.S.A.

REV. B