Datasheet OP285 Datasheet (Analog Devices)

Dual 9 MHz Precision

8

7

6

5

V+

–IN B

+IN B

OUT B

1

2

3

4

–IN A

+IN A

V–

OUT A

+–

+–

OP285

a

FEATURES
Low Offset Voltage: 250 V
Low Noise: 6 nV/√ Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Current: 2 nA
Unity-Gain Stable
SO-8 Package

APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators

GENERAL DESCRIPTION

The OP285 is a precision high-speed amplifier featuring the
Butler Amplifier front-end. This new front-end design com­bines the accuracy and low noise performance of bipolar
transistors with the speed of JFETs. This yields an amplifier
with high slew rates, low offset and good noise performance
at low supply currents. Bias currents are also low compared
to bipolar designs.

The OP285 offers the slew rate and low power of a JFET
amplifier combined with the precision, low noise and low
drift of a bipolar amplifier. Input offset voltage is laser-trimmed
and guaranteed less than 250 µV. This makes the OP285 useful
in dc-coupled or summing applications without the need for
special selections or the added noise of additional offset
adjustment circuitry. Slew rates of 22 V/µs and a bandwidth
of 9 MHz make the OP285 one of the most accurate medium
speed amplifiers available.

Operational Amplifier

OP285

PIN CONNECTIONS

8-Lead Narrow-Body SO (S-Suffix)

OUT A

1

–IN A

2

OP285

3

4

TOP VIEW

(Not to Scale)

+IN A

V–

8-Lead Epoxy DIP (P-Suffix)

The combination of low noise, speed and accuracy can be used
to build high speed instrumentation systems. Circuits such as
instrumentation amplifiers, ramp generators, bi-quad filters and
dc-coupled audio systems are all practical with the OP285. For
applications that require long term stability, the OP285 has a
guaranteed maximum long term drift specification.

The OP285 is specified over the XIND—extended industrial—
(–40°C to +85°C) temperature range. OP285s are available in
8-pin plastic DIP and SOIC-8 surface mount packages.

8

7

6

5

V+

OUT B

–IN B

+IN B

*

*Patents pending

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

OP285–SPECIFICATIONS

(@ Vs = 15.0 V, TA = 25C, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current I

Input Offset Current I

Input Voltage Range V

OS

V

OS

B

I

B

OS

I

OS

CM

Common-Mode Rejection CMRR V

Large-Signal Voltage Gain A

VO

A

VO

A

VO

–40°C ≤ TA ≤ +85°C 600 µV
VCM = 0 V 100 350 nA
VCM = 0 V, –40°C ≤ TA ≤ +85°C 400 nA
VCM = 0 V 2 ±50 nA
VCM = 0 V, –40°C ≤ TA ≤ +85°C2±100 nA

–10.5 10.5 V

= ±10.5 V,

CM

–40°C ≤ T

≤ +85°C 80 106 dB

A

RL = 2 kΩ 250 V/mV
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C 175 V/mV
RL = 600 Ω 200 V/mV

35 250 µV

Common-Mode Input Capacitance 7.5 pF
Differential Input Capacitance 3.7 pF
Long-Term Offset Voltage ∆V
Offset Voltage Drift ∆V

OS

/∆T1µV/°C

OS

Note 1 300 µV

OUTPUT CHARACTERISTICS

Output Voltage Swing V

O

V

O

RL = 2 kΩ –13.5 +13.9 +13.5 V
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C –13 +13.9 +13 V
RL = 600 Ω, V

= ±18 V –16/+14 V

S

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

PSRR V

Supply Current I

SY

I

SY

= ±4.5 V to ±18 V 85 111 dB

S

= ±4.5 V to ±18 V,

S

–40°C ≤ T

≤ +85°C80 dB

A

VS = ±4.5 V to ±18 V, VO = 0 V,

= x, –40°C ≤ TA ≤ +85°C45mA

R

L

VS = ±22 V, VO, = 0 V, RL = x
–40°C ≤ T

≤ +85°C 5.5 mA

A

Supply Voltage Range VS ±4.5 ± 22 V

DYNAMIC PERFORMANCE

Slew Rate SR R

= 2 kΩ 15 22 V/µs

L

Gain Bandwidth Product GBP 9 MHz
Phase Margin ␪o 62 Degrees
Settling Time t

s

t

s

Distortion A

Voltage Noise Density e

Current Noise Density i

n

e

n

n

To 0.1%, 10 V Step 625 ns
To 0.01%, 10 V Step 750 ns

= 1, V

V

f = 1 kHz, R

= 8.5 V p-p,

OUT

= 2 kΩ –104 dB

L

f = 30 Hz 7 nV/√Hz
f = 1 kHz 6 nV/√Hz
f = 1 kHz 0.9 pA/√Hz

Headroom THD + Noise ≤ 0.01%,

RL = 2 kΩ, VS = ±18 V >12.9 dBu

NOTE

1

Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

–2–

REV. A

OP285

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V

Input Voltage
Differential Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

2

. . . . . . . . . . . . . . . . . . . . . . ±7.5 V

Output Short-Circuit Duration to Gnd
Storage Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP285G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

1

3

. . . . . . . . . Indefinite

Package Type 

8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W

NOTES

1

Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.

2

For supply voltages less than ± 7.5 V, the absolute maximum input voltage is
equal to the supply voltage.

3

Shorts to either supply may destroy the device. See data sheet for full details.

4

␪JA is specified for the worst case conditions, i.e., ␪JA is specified for device in

socket for cerdip, P-DIP, and LCC packages; ␪JA is specified for device soldered
in circuit board for SOIC package.

Lead Temperature Range (Soldering 60 Sec) . . . . . . . . 300°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP285GP* –40°C to +85°C 8-Pin Plastic DIP N-8
OP285GS –40°C to +85°C 8-Pin SOIC S0-8
OP285GSR –40°C to +85°C S0-8 Reel, 2500 pcs.

*Not for new designs. Obsolete April 2002.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP285 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

4

JA

WARNING!



JC

ESD SENSITIVE DEVICE

Unit

REV. A

–3–

OP285

25

T

= 25C

A

20

= 2k

R

L

15

10

5

0

–5

–10

–15

OUTPUT VOLTAGE SWING – V

–20

–25

0 5 10 15 20 25

SUPPLY VOLTAGE – V

+VOM

–VOM

TPC 1. Output Voltage Swing vs.
Supply Voltage

50

VS = 15V

VS = 15V

= 2k

R

R

= 2k

L

L

45

40

35

30

SLEW RATE – V/s

25

20

TEMPERATURE – C

–SR

+SR

0

100–25–50 755025

TPC 4. Slew Rate vs. Temperature

1500

VS = 15V

= 10V

V

O

1250

1000

750

500

OPEN-LOOP GAIN – V/MV

250

0
–50

R

+GAIN

= 600

L

–25

+GAIN

= 2k

R

L

–GAIN

= 2k

R

L

–GAIN

= 600

R

L

0

TEMPERATURE – C

755025

TPC 2. Open-Loop Gain
vs. Temperature

CLOSED-LOOP GAIN – dB

–10

–20

–30

50

40

A

= +100

VCL

30

20

A

= +10

VCL

10

0

1k

= +1

A

VCL

10k 100k 1M 10M 100M

FREQUENCY – Hz

VS = 15V
T

= +25C

A

TPC 5. Closed-Loop Gain
vs. Frequency

100

30

VS = 15V
R

= 2k

L

25

20

15

+SR

–SR

10

SLEW RATE – V/s

5

0

0

DIFFERENTIAL INPUT VOLTAGE – V

1.0

0.80.60.40.2

TPC 3. Slew Rate vs. Differential
Input Voltage

60

50

40

A

= +10

30

A

VCL

20

IMPEDANCE – 

10

0

1k 10k 100k 1M 10M

100

VCL

= +100

FREQUENCY – Hz

VS = 15V
T

= 25C

A

A

= +1

VCL

TPC 6. Closed-Loop Output Imped
ance vs. Frequency

120

V

= 15V

S

T

= 25C

A

COMMON MODE REJECTION – dB

100

80

60

40

20

0

1k 10k 100k 1M 10M

100

FREQUENCY – Hz

TPC 7. Common-Mode Rejection
vs. Frequency

120

POWER SUPPLY REJECTION – dB

100

80

60

40

20

VS = 15V
T

= 25C

A

–PSRR

0

10

100 1k 10k 100k 1M

FREQUENCY – Hz

+PSRR

TPC 8. Power Supply Rejection
vs. Frequency

–4–

100

80

60

– dB

40

MIN

PHASE

20

0

OPEN-LOOP G

–20

–40

–60

1k

GAIN

10k 100k 1M 10M 100M

FREQUENCY – Hz

V

= 15V

S

R

= 2k

L

= 25C

T

A

= 58

0

N

TPC 9. Open-Loop Gain, Phase
vs. Frequency

REV. A

0

45

90

135

180

225

270

PHASE – Degrees

Typical Performance Characteristics–OP285

11

10

9

8

GAIN BANDWIDTH PRODUCT – MHz

7

–50 100

–25 755025

TEMPERATURE – C

GBW

0

ø

M

65

60

55

50

40

TPC 10. Gain Bandwidth Product,
Phase Margin vs. Temperature

30

25

20

15

10

TA = 25C

= 15V

V

S

= +1

A

VCL

5

MAXIMUM OUTPUT SWING – V

= 2k

R

L

0

1k

10k 10M1M100k

FREQUENCY – Hz

TPC 13. Maximum Output Swing
vs. Frequency

100

PHASE MARGIN – Degrees

90

80

70

60

50

40

OVERSHOOT – %

30

20

10

0

0

A = +1

VCL

NEGATIVE EDGE

A = +1

VCL

POSITIVE EDGE

VS = 15V

= 2k

R

L

= 100mV p-p

V

IN

100

LOAD CAPACITANCE – pF

300

TPC 11. Small-Signal Overshoot vs.|
Load Capacitance

5.0

4.5

TA = +85C

4.0

TA = +25C

TA = –40C

3.5

SUPPLY CURRENT – mA

3.0
0

5

SUPPLY VOLTAGE – V

TPC 14. Supply Current vs.
Supply Voltage

16

14

–VOM

12

10

8

6

4

2

MAXIMUM OUTPUT SWING – Volts

0

500

400200

100 1k 10k

+VOM

TA = 25C

= 15V

V

S

LOAD RESISTANCE – 

TPC 12. Maximum Output Voltage
vs. Load Resistance

120

110

100

90

SINK

80

70

60

50

40

SOURCE

30

ABSOLUTE OUTPUT CURRENT – mA

20

1510

25

–50

0

–25

TEMPERATURE – C

VS = 15V

7525 50

100

TPC 15. Short Circuit Current vs.
Temperature

300

VS = 15V

250

200

150

100

INPUT BIAS CURRENT – nA

50

0

–25

–50

0

TEMPERATURE – C

755025

TPC 16. Input Bias Current vs.
Temperature

REV. A

100

5

Hz

CURRENT NOISE DENSITY – pA/

4

3

2

1

10

100 100k1k

FREQUENCY – Hz

VS = 15V

= 25C

T

A

TPC 17. Current Noise Density vs.
Frequency

–5–

250

–40C TA +85C

TC V

402 OP AMPS

– V/ C

OS

200

150

UNITS

100

50

0

0

1

TPC 18. tC VOS Distribution

10

98765432

OP285

250

TA= 25C

200

150

UNITS

100

50

–250

0

–

00

–150

–

2

–50

100

INPUT OFFSET – V

402  OP AMPS

0

15050

TPC 19. Input Offset (VOS)
Distribution

100

90

10

8

6

4

2

0

–2

STEP SIZE – V

–4

–6

–8

250

200100

–10

100

0

+0.1%

–0.1% –0.01%

SETTLING TIME – ns

+0.01%

800500 600300 400 700200

900

TPC 20. Settling Time vs. Step Size

50

45

40

35

30

SLEW RATE – V/S

25

20

0

–SR

+SR

100

CAPACITIVE LOAD – pF

TA = 25C

= 15V

V

S

400300200

TPC 21. Slew Rate vs.

500

Capacitive Load

100

90

100

90

10

0%

5V

200nS

TPC 22. Negative Slew Rate

=2 kΩ, VS = ±15 V, AV = +1

R

L

CH A: 80.0 V FS 10.0 V/DIV

MKR: 6.23 V/

0 Hz

Hz

2.5 KHz

BW: 15.0 MHzMKR: 1 000 Hz

TPC 25. OP285 Voltage Noise Density
vs. Frequency V

= ±15 V, AV = 1000

S

10

0%

5V

200nS

TPC 23. Positive Slew Rate

Ω

RL = 2 k

, VS = ±15 V, AV = +1

10

0%

50mV

100nS

TPC 24. Small Signal Response

=2 kΩ, VS = ±15 V, AV = +1

R

L

–6–

REV. A

OP285

APPLICATIONS
Short-Circuit Protection

The OP285 has been designed with inherent short-circuit
protection to ground. An internal 30 Ω resistor, in series with
the output, limits the output current at room temperature to

+ = 40 mA and ISC- = –90 mA, typically, with ±15 V supplies.

I

SC

However, shorts to either supply may destroy the device when
excessive voltages or current are applied. If it is possible for a
user to short an output to a supply, for safe operation, the out­put current of the OP285 should be design-limited to ±30 mA,
as shown in Figure 1.

R

FB

R

–

A1

+

X

332

A1 = 1/2 OP285

FEEDBACK

V

OUT

Figure 1. Recommended Output Short-Circuit Protection

Input Over Current Protection

The maximum input differential voltage that can be applied
to the OP285 is determined by a pair of internal Zener diodes
connected across the inputs. They limit the maximum differ­ential input voltage to ±7.5 V. This is to prevent emitter-base
junction breakdown from occurring in the input stage of the
OP285 when very large differential voltages are applied. How­ever, in order to preserve the OP285’s low input noise
voltage, internal resistance in series with the inputs were not
used to limit the current in the clamp diodes. In small-signal
applications, this is not an issue; however, in industrial appli­cations, where large differential voltages can be inadvertently
applied to the device, large transient currents can be made to
flow through these diodes. The diodes have been designed to
carry a current of ±8 mA; and, in applications where the
OP285’s differential voltage were to exceed ±7.5 V, the resis­tor values shown in Figure 2 safely limit the diode current to
±8 mA.

909

909

–

A1

+

A1 = 1/2

Figure 2. OP285 Input Over Current Protection

Output Voltage Phase Reversal

Since the OP285’s input stage combines bipolar transistors
for low noise and p-channel JFETs for high speed performance,
the output voltage of the OP285 may exhibit phase reversal if
either of its inputs exceed its negative common-mode input
voltage. This might occur in very severe industrial applications
where a sensor or system fault might apply very large voltages on
the inputs of the OP285. Even though the input voltage range of
the OP285 is ±10.5 V, an input voltage of approximately –13.5 V
will cause output voltage phase reversal. In inverting amplifier
configurations, the OP285’s internal 7.5 V input clamping
diodes will prevent phase reversal; however, they will not prevent
this effect from occurring in noninverting applications. For these

applications, the fix is a simple one and is illustrated in Figure 3.
A 3.92 kΩ resistor in series with the noninverting input of the
OP285 cures the problem.

RFB*

V

IN

RS

3.92k

IS OPTIONAL

*R

FB

–

+

RL
2k

V

OUT

Figure 3. Output Voltage Phase Reversal Fix

Overload or Overdrive Recovery

Overload or overdrive recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time is
important in applications where the amplifier must recover quickly
after a large abnormal transient event. The circuit shown in Figure
4 was used to evaluate the OP285’s overload recovery time. The
OP285 takes approximately 1.2 µs to recover to V

R2

= –10 V.

OUT

1

RL

2.43k

and approximately 1.5 µs to recover to V

V

IN

4V p-p

@100 Hz

R1

1k

R

909

A1 = 1/2 OP285

S

10k

2

A1

3

OUT

V

OUT

= +10 V

Figure 4. Overload Recovery Time Test Circuit

Driving the Analog Input of an A/D Converter

Settling characteristics of operational amplifiers also include the
amplifier’s ability to recover, i.e., settle, from a transient output
current load condition. When driving the input of an A/D
converter, especially successive-approximation converters, the
amplifier must maintain a constant output voltage under
dynamically changing load current conditions. In these types of
converters, the comparison point is usually diode clamped, but
it may deviate several hundred millivolts resulting in high
frequency modulation of the A/D input current. Amplifiers that
exhibit high closed-loop output impedances and/or low unity-gain
crossover frequencies recover very slowly from output load
current transients. This slow recovery leads to linearity errors or
missing codes because of errors in the instantaneous input voltage.
Therefore, the amplifier chosen for this type of application should
exhibit low output impedance and high unity-gain bandwidth so
that its output has had a chance to settle to its nominal value
before the converter makes its comparison.

The circuit in Figure 5 illustrates a settling measurement circuit
for evaluating the recovery time of an amplifier from an output
load current transient. The amplifier is configured as a follower
with a very high speed current generator connected to its output.
In this test, a 1 mA transient current was used. As shown in
Figure 6, the OP285 exhibits an extremely fast recovery time of
139 ns to 0.01%. Because of its high gain-bandwidth product,
high open-loop gain, and low output impedance, the OP285 is
ideally suited to drive high speed A/D converters.

REV. A

–7–

OP285

+15V

+

2

3

8

1

4

V

IN

V

OUT

–15V

10F

0.1F

R

L

15k

0.1F

10F

+

–

1/2

OP285

+15V

0.1F

8

3

+

1

1/2

OP285

2

–

4

–15V

300pF

15V

TTL

INPUT

1N4148

15V

*NOTE

DECOUPLE CLOSE
TOGETHER ON GROUND PLAN
WITH SHORT LEAD LENGTHS.

1.5k

1.8k

0.1F

2N2907

220

0.1F

*

1k

2N3904

1k

0.01F

10F

V

REF

(–1V)

I

OUT

+

0.47F

+ 7A13 PLUG-IN

– 7A13 PLUG-IN

|V

|

REF

1k

Figure 5. Transient Output Load Current Test Fixture

Measuring Settling Time

The design of OP285 combines high slew rate and wide gain­bandwidth product to produce a fast-settling (ts < l µs) amplifier
for 8- and 12-bit applications. The test circuit designed to measure
the settling time of the OP285 is shown in Figure 7. This test
method has advantages over false-sum node techniques in that
the actual output of the amplifier is measured, instead of an
error voltage at the sum node. Common-mode settling effects
are exercised in this circuit in addition to the slew rate and
bandwidth effects measured by the false-sum-node method. Of
course, a reasonably flat-top pulse is required as the stimulus.

The output waveform of the OP285 under test is clamped by
Schottky diodes and buffered by the JFET source follower.
The signal is amplified by a factor of ten by the OP260 and
then Schottky-clamped at the output to prevent overloading
the oscilloscope’s input amplifier. The OP41 is configured as
a fast integrator which provides overall dc offset nulling.

High Speed Operation

As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement. Rec­ommended circuit configurations for inverting and noninverting
applications are shown in Figures 8 and Figure 9.

NS

50NS

TTL CTRL

(5V/ DIV)

10V

V

OUT

(2MV/ DIV)

A1 1,2 V T 138.9

100

90

10

0%

5V

2MV

Figure 6. OP285’s Output Load Current Recovery Time

16–20V

– +

0.1F

V+

DUT

+ –

16–20V

5V

V–

0.1F

R

L

1k

D1 D2

1N4148

Figure 7. OP285’s Settling Time Test Fixture

–15V

15k

+15V

2N4416

2N2222A

1/2 OP260AJ

R

F

2k

R

G

222

SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ

Figure 8. Unity Gain Follower

1k

D3

10k

10k

750

D4

1F

IC2

OUTPUT
(TO SCOPE)

–8–

REV. A

+15V

10F

+

0.1F

10pF

4.99k

V

IN

2.49k

2

–

OP285

3

+

4.99k

1/2

–15V

8

4

0.1F

10F

V

1

OUT

2k

+

Figure 9. Unity-Gain Inverter

In inverting and noninverting applications, the feedback resis­tance forms a pole with the source resistance and capacitance
(R

and CS) and the OP285’s input capacitance (CIN), as

S

shown in Figure 10. With R

and RF in the kilohm range, this

S

pole can create excess phase shift and even oscillation. A small
capacitor, C
setting R

, in parallel with RFB eliminates this problem. By

FB

(CS + CIN) = RFBCFB, the effect of the feedback pole

S

is completely removed.

C

FB

R

FB

V

R

S

C

S

C

IN

OUT

OP285

R3

2k

2

A2

3

R1

2k

V

3

IN

1

A1

2

2k

R4
2k

R5
2k

R2

A1 = 1/2OP285
A2, A3 = 1/2 OP285
GAIN = SET R2, R4, R5 = R1 AND R, R7, R8 = R2

2k

6

A3

5

Figure 11. High-Speed, Low-Noise Differential Line Driver

Low Phase Error Amplifier

The simple amplifier configuration of Figure 12 uses the OP285
and resistors to reduce phase error substantially over a wide
frequency range when compared to conventional amplifier designs.
This technique relies on the matched frequency characteristics
of the two amplifiers in the OP285. Each amplifier in the circuit
has the same feedback network which produces a circuit gain of

10. Since the two amplifiers are set to the same gain and are
matched due to the monolithic construction of the OP285, they
will exhibit identical frequency response. Recall from feedback
theory that a pole of a feedback network becomes a zero in the
loop gain response. By using this technique, the dominant pole
of the amplifier in the feedback loop compensates for the domi­nant pole of the main amplifier,

R9

1

50

R11

R7

2k

R6

R10

7

50

R8

2k

1k

10k

R12

1k

P1

V

O2

V

O1

– VO1 = V

V

O2

IN

Figure 10. Compensating the Feedback Pole

High-Speed, Low-Noise Differential Line Driver

The circuit of Figure 11 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The
high slew rate and wide bandwidth of the OP285 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/√Hz. The design is a transformerless, balanced
transmission system where output common-mode rejection of
noise is of paramount importance. Like the transformer-based
design, either output can be shorted to ground for unbalanced
line driver applications without changing the circuit gain of 1.
Other circuit gains can be set according to the equation in the
diagram. This allows the design to be easily set to noninverting,
inverting, or differential operation.

REV. A

–9–

R2

R3

499

4.99k

2

A1

3

6

A2

5

A1, A2 = 1/2 OP285

1

R5

549

R4

4.99

7

V

OUT

V

IN

R1

549

Figure 12. Cancellation of A2’s Dominant Pole by A1

OP285

thereby reducing phase error dramatically. This is shown in
Figure 13 where the 10x composite amplifier’s phase response
exhibits less than 1.5° phase shift through 500 kHz. On the other
hand, the single gain stage amplifier exhibits 25° of phase shift
over the same frequency range. An additional benefit of the low
phase error configuration is constant group delay, by virtue of
constant phase shift at all frequencies below 500 kHz. Although
this technique is valid for minimum circuit gains of 10, actual
closed-loop magnitude response must be optimized for the
amplifier chosen.

LOW PHASE ERROR

0

–5

–10

–15

–20

–25

PHASE – Degrees

–30

–35

–40

–45

SINGLE STAGE

AMPLIFIER RESPONSE

10k 100k 10M1M

START 10,000.000Hz STOP 10,000,000.000Hz

AMPLIFIER RESPONSE

Figure 13. Phase Error Comparison

A Low Noise, High Speed Instrumentation Amplifier

A high speed, low noise instrumentation amplifier, constructed
with a single OP285, is illustrated in Figure 15. The circuit exhibits
less than 1.2 µV p-p noise (RTI) in the 0.1 Hz to 10 Hz band
and an input noise voltage spectral density of 9 nV/√Hz (1 kHz)
at a gain of 1000. The gain of the amplifier is easily set by R

G

according to the formula:

V

OUT

V

IN G

k

9982. Ω

=+

R

The advantages of a two op amp instrumentation amplifier
based on a dual op amp is that the errors in the individual am­plifiers tend to cancel one another. For example, the circuit’s
input offset voltage is determined by the input offset voltage
matching of the OP285, which is typically less than 250 µV.

+

V

IN

–

AC CMRR TRIM

C1

5pF–40pF

DC CMRR TRIM

3

A1

2

4.99

R1

4.99k

P1
500

1

R2

R3

4.99k

R

G

5

7

A2

6

R4

4.99k

A1, A2 = 1/2 OP285

9.98k

GAIN =

R

GAIN

2

10

100

1000

Q

()

R

G

OPEN

1.24k
102

10

V

OUT

+2

For a more detailed treatment on the design of low phase error
amplifiers, see Application Note AN-107.

Fast Current Pump

A fast, 30 mA current source, illustrated in Figure 14, takes
advantage of the OP285’s speed and high output current drive.
This is a variation of the Howland current source where a sec­ond amplifier, A2, is used to increase load current accuracy and
output voltage compliance. With supply voltages of ±15 V, the
output voltage compliance of the current pump is ±8 V. To
keep the output resistance in the MΩ range requires that 0.1%
or better resistors be used in the circuit. The gain of the current
pump can be easily changed according to the equations shown
in the diagram.

R1

V

V

2k

IN1

R3

2k

IN2

A1, A2 = 1/2 OP285

R2

GAIN = , R4 = R2, R3 = R1

R1

R2

2k

2

A1

3

R4

2k

R5

50

1

V

– V

V

IN1

5

7

A2

6

IN2

I

=

OUT

I

= (MAX) = 30mA

OUT

R5

IN

=

R5

Figure 14. A Fast Current Pump

Figure 15. A High-Speed Instrumentation Amplifier

Common-mode rejection of the circuit is limited by the matching
of resistors R1 to R4. For good common-mode rejection, these
resistors ought to be matched to better than 1%. The circuit was
constructed with 1% resistors and included potentiometer P1
for trimming the CMRR and a capacitor C1 for trimming the
CMRR. With these two trims, the circuit’s common-mode
rejection was better than 95 dB at 60 Hz and better than 65 dB
at 10 kHz. For the best common-mode rejection performance,
use a matched (better than 0.1%) thin-film resistor network for
R1 through R4 and use the variable capacitor to optimize the
circuit’s CMR.

The instrumentation amplifier exhibits very wide small- and
large-signal bandwidths regardless of the gain setting, as shown
in the table. Because of its low noise, wide gain-bandwidth
product, and high slew rate, the OP285 is ideally suited for high
speed signal conditioning applications.

Circuit R
Gain () V

G

OUT

Circuit Bandwidth

= 100 mV p-p V

= 20 V p-p

OUT

2 Open 5 MHz 780 kHz
10 1.24 k 1 MHz 460 kHz
100 102 90 kHz 85 kHz
1000 10 10 kHz 10 kHz

–10–

REV. A

OP285

R1

95.3k

2

A1

V

3

IN

C1

2200pF

1

1

A2

R2

787

C2

2200pF

R3

1.82k

2

2200pF

C3

3

5

6

R6

4.12k

A3

7

2200pF

5

C4

100k

6

R7

R9

1k

A4

1k

7

V

OUT

R8

R4

1.87k

R5

1.82k

Figure 16. A 3-Pole, 40 kHz Low-Pass Filter

A 3-Pole, 40 kHz Low-Pass Filter

The closely matched and uniform ac characteristics of the OP285
make it ideal for use in GIC (Generalized Impedance Converter)
and FDNR (Frequency Dependent Negative Resistor) filter appli­cations. The circuit in Figure 16 illustrates a linear-phase,
3-pole, 40 kHz low-pass filter using an OP285 as an inductance
simulator (gyrator). The circuit uses one OP285 (A2 and A3)
for the FDNR and one OP285 (Al and A4) as an input buffer
and bias current source for A3. Amplifier A4 is configured in a
gain of 2 to set the pass band magnitude response to 0 dB. The
benefits of this filter topology over classical approaches are
that the op amp used in the FDNR is not in the signal path and
that the filter’s performance is relatively insensitive to compo­nent variations. Also, the configuration is such that large signal
levels can be handled without overloading any of the filter’s
internal nodes. As shown in Figure 17, the OP285’s symmetric
slew rate and low distortion produce a clean, well-behaved
transient response.

100

90

V

OUT

10V p-p

10kHz

A1, A4 = 1/2 OP285
A2, A3 = 1/2 OP285

Driving Capacitive Loads

The OP285 was designed to drive both resistive loads to 600 Ω
and capacitive loads of over 1000 pF and maintain stability. While
there is a degradation in bandwidth when driving capacitive loads,
the designer need not worry about device stability. The graph in
Figure 18 shows the 0 dB bandwidth of the OP285 with capacitive
loads from 10 pF to 1000 pF.

10

9

8

7

6

5

4

BANDWIDTH – MHz

3

2

1

0

0

200 400 600 800 1000

Figure 18. Bandwidth vs. C

C

LOAD

– pF

LOAD

10

0%

SCALE: VERTICAL – 2V/ DIV
HORIZONTAL – 10S/ DIV

Figure 17. Low-Pass Filter Transient Response

REV. A

–11–

OP285

OP285 SPICE Model

* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
*
*

.SUBCKT OP285 1 2 99 50 34

*
* INPUT STAGE & POLE AT 100 MHZ
*

R3 5 51 2.188
R4 6 51 2.188
CIN 1 2 1.5E-12
C2 5 6 364E-12
I1 97 4 100E-3
IOS 1 2 1E-9
EOS 9 3 POLY(1) 26 28 35E-6 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 1.672
R6 8 4 1.672
D1 2 36 DZ
D2 1 36 DZ
EN 3 1 100 1
GN1 0 2 13 0 1
GN20 1 16 0 1

*

EREF 98 0 28 0 1
EP 97 0 99 0 l
EM 510 50 0 1

*
* VOLTAGE NOISE SOURCE
*

DN1 35 10 DEN
DN2 10 11 DEN
VN1 35 0 DC 2
VN2 0 11 DC 2

*
* CURRENT NOISE SOURCE
*

DN3 12 13 DIN
DN4 13 14 DIN
VN3 12 0 DC 2
VN4 0 14 DC 2
CN1 13 0 7.53E-3

*
* CURRENT NOISE SOURCE
*

DN5 15 16 DIN
DN6 16 17 DIN
VN5 15 0 DC 2
VN6 0 17 DC2
CN2 16 0 7.53E-3

*
* GAIN STAGE & DOMINANT POLE AT 32 HZ *

R7 18 98 1.09E6
C3 18 98 4.55E-9
G1 98 18 5 6 4.57E-1
V2 97 19 1.4
V3 20 51 1.4
D3 18 19 DX
D4 20 18 DX

*

* POLE/ZERO PAIR AT 1.5MHz/2.7MHz
*

R8 21 98 1E3
R9 21 22 1.25E3
C4 22 98 47.2E-12
G2 98 21 18 28 1E-3

*
* POLE AT 100 MHZ
*

R10 23 98 1
C5 23 98 1.59E-9
G3 98 23 21 28 1

*
* POLE AT 100 MHZ
*

R11 24 98 l
C6 24 98 1.59E-9
G4 98 24 23 28 1

*
* COMMON-MODE GAIN NETWORK WITH ZERO AT

1 kHZ *
R12 25 26 1E6
C7 25 26 1.59E-12
R13 26 98 1
E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506

*
* POLE AT 100 MHZ
*

R14 27 98 1
C8 27 98 1.59E-9
G5 98 27 24 28 1

*
* OUTPUT STAGE
*

Rl5 28 99 100E3
R16 28 50 100E3
C9 28 50 1 E-6
ISY 99 50 1.85E-3
R17 29 99 100
R18 29 50 100
L2 29 34 1E-9
G6 32 50 27 29 10E-3
G7 33 50 29 27 10E-3
G8 29 99 99 27 10E-3
G9 50 29 27 50 10E-3
V4 30 29 1.3
V5 29 31 3.8
F1 29 0 V4 1
F2 0 29 V5 1
D5 27 30 DX
D6 31 27 DX
D7 99 32 DX
D8 99 33 DX
D9 50 32 DY
D10 50 33 DY

*
* MODELS USED
*

.MODEL QX PNP(BF = 5E5)
.MODEL DX D(IS = lE-12)
.MODEL DY D(IS = lE-15 BV = 50)
.MODEL DZ D(IS = lE-15 BV = 7.0)
.MODEL DEN D(IS = lE-12 RS = 4.35K KF = 1.95E-15
AF = l) .MODEL DIN D(IS = lE-12 RS = 77.3E-6
KF = 3.38E-15 AF = 1) .ENDS OP-285

–12–

REV. A

–IN

+IN

OP285

97

E

I1

4

R5

2

C

IN

I

OS

1

7

Q1

D1

36

D2

E

N

56

R3

R6

8

Q2

E

OS

3

C2

R4

Figure 19a. Spice Diagram

P

9

E

M

35

V

D

N1

N1

10

D

N2

V

N2

11

12

V

D

N3

N3

13

C

N1

D

V

N4

N4

14

15

V

D

N5

N5

16

D

V

N6

N6

17

C

N2

G1

97

V2

19

D3

21

R9

C3

R7

51

G2

D4

20

V3

R8

G3

C4

23

G4

C5

R10

24

C6

R11

E2

C7

R12

26

R13

25

Figure 19b. Spice Diagram

99

32 33

G6

G7

D8

G8

V4

F1

V5

F2

D10

G3

R17

L2

29

34

OUTPUT

R18

D7

R15

I

SY

28

27

G5

98

R14

C8

R16

C9

50

D5

30

D6

31

D9

REV. A

Figure 19c. Spice Diagram

–13–

OP285

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead PDIP Package

(N-8)

0.200 (5.05)

0.125 (3.18)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

0.210
(5.33)

MAX

8

1

0.430 (10.92)

0.348 (8.84)

0.022 (0.558)

0.014 (0.356)

8

1

0.1968 (5.00)

0.1890 (4.80)

5

0.280 (7.11)

0.240 (6.10)

4

0.070 (1.77)

0.045 (1.15)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)

MIN

SEATING

0.100

(2.54)

BSC

PLANE

0 - 15

8-Lead SOIC Package

(R-8)

5

0.1574 (4.00)

0.1497 (3.80)

4

0.2440 (6.20)

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0196 (0.50)

0.0099 (0.25)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.0500 (1.27)

0.0160 (0.41)

× 45

0

- 8

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)
SEATING

PLANE

–14–

0.0098 (0.25)

0.0075 (0.19)

SEE DETAIL

ABOVE

REV. A

OP285

Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

REV. A

–15–

(A)

C00306–0–1/02

–16–

PRINTED IN U.S.A.