Datasheet OP282 Datasheet (Analog Devices)

Dual/Quad Low Power, High Speed

O

A

A

FEATURES

High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier max
Low offset voltage: 3 mV max
Low bias current: 100 pA max
Fast settling time
Common-mode range includes V+
Unity-gain stable

APPLICATIONS

Active filters
Fast amplifiers
Integrators
Supply current monitoring

GENERAL DESCRIPTION

The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current under 250 µA per
amplifier. These unity-gain stable amplifiers have a typical gain
bandwidth of 4 MHz.

The JFET input stage of the OP282/OP482 ensures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.

With a wide output swing, within 1.5 V of each supply, low
power consumption, and high slew rate, the OP282/OP482
are ideal for battery-powered systems or power restricted
applications. An input common-mode range that includes the
positive supply makes the OP282/OP482 an excellent choice for
high-side signal conditioning.

The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead narrow SOIC and MSOP packages. The OP482 is
available in PDIP and narrow SOIC packages.

JFET Operational Amplifiers

OP282/OP482

PIN CONNECTIONS

+–

+–

V+

8

OUT B

7

–IN B

6

+IN B

5

8
7
6
5

14
13
12
11
10

14
13
12
11
10

9
8

V+
OUT B
–IN B
+IN B

9
8

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

00301-001

00301-002

00301-003

00301-004

1

UT

–IN A

2
3
4

OP282

OP-482

+IN A

V–

Figure 1. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8]

OUT

1

V–

OP282

2

TOP VIEW

3

(Not to Scale)

4

–IN A
+IN A

Figure 2. 8-Lead MSOP [RM-8]

1

OUT A

2

–IN A

+IN A

V+
+IN B
–IN B

OUT B

– +

3

OP482

4
5

– +

6
7

Figure 3. 14-Lead PDIP (P-Suffix) [N-14]

OUT A

1

–IN A

2

+IN A

3
4
5
6
7

OP482

V+

+IN B

–IN B

OUT B

Figure 4. 14-Lead Narrow-Body SOIC (S-Suffix) [R-14]

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

OP282/OP482

TABLE OF CONTENTS

Specifications..................................................................................... 3

High-Side Signal Conditioning ................................................ 12

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Typical Performance Characteristics............................................. 5

Applications Information .............................................................. 12

REVISION HISTORY

10/04—Data Sheet Changed from Rev. E to Rev. F

Deleted 8-Lead PDIP .........................................................Universal

Added 8-Lead MSOP .........................................................Universal

Changes to Format and Layout.........................................Universal

Changes to Features.......................................................................... 1

Changes to Pin Configurations....................................................... 1

Changes to General Description .................................................... 1

Changes to Specifications................................................................ 3

Changes to Absolute Maximum Ratings ....................................... 4

Changes to Table 3............................................................................ 4

Added Figure 5 through Figure 20; Renumbered

Successive Figures............................................................................. 5

Updated Figure 21 and Figure 22 ................................................... 7

Updated Figure 23 and Figure 27 ................................................... 8

Updated Figure 29............................................................................ 9

Updated Figure 35 and Figure 36 ................................................. 10

Updated Figure 43.......................................................................... 11

Changes to Applications Information.......................................... 12

Changes to Figure 44...................................................................... 12

Deleted OP282/OP482 Spice Macro Model Section.................... 9

Deleted Figure 4................................................................................ 9

Deleted OP282 Spice Marco Model............................................. 10

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

Phase Inversion........................................................................... 12

Active Filters ............................................................................... 12

Programmable State-Variable Filter......................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 16

10/02—Data Sheet Changed from Rev. D to Rev. E

Edits to 8-Lead Epoxy DIP (P-Suffix) Pin......................................1

Edits to Ordering Guide...................................................................3

Edits to Outline Dimensions......................................................... 11

9/02—Data Sheet Changed from Rev. C to Rev. D

Edits to 14-Lead SOIC (S-Suffix) Pin .............................................1

Replaced 8-Lead SOIC (S-Suffix)................................................. 11

4/02—Data Sheet changed from Rev. B to Rev. C

Wafer Test Limits Deleted ................................................................2

Edits to Absolute Maximum Ratings ..............................................3

Dice Characteristics Deleted............................................................3

Edits to Ordering Guide...................................................................3

Edits to Figure 1.................................................................................7

Edits to Figure 3.................................................................................8

20-Position Chip Carrier (RC Suffix) Deleted ........................... 11

Rev. F | Page 2 of 16

OP282/OP482

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grade.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

OP282, −40°C ≤ TA ≤ +85°C 4.5 mV
V

OS

OP482, −40°C ≤ TA ≤ +85°C 6 mV
Input Bias Current I

B

V
Input Offset Current I

OS

V
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large Signal Voltage Gain A

VO

R
Offset Voltage Drift ∆VOS/∆T 10 µV/°C
Bias Current Drift ∆IB/∆T 8 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V
Output Voltage Low V
Short-Circuit Limit I

OH

OL

SC

Sink −12 −8 mA
Open-Loop Output Impedance Z

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier I
Supply Voltage Range V

SY

S

DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BW
Settling Time t

P

S

Gain Bandwidth Product GBP 4 MHz
Phase Margin Ø

O

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density e
Current Noise Density i

n

n

OP282 0.2 3 mV

OP482 0.2 4 mV

VCM = 0 V 3 100 pA

1

CM

= 0 V

500 pA

VCM = 0 V 1 50 pA

= 0 V1 250 pA

CM

RL = 10 kΩ 20 V/mV

= 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV

L

RL = 10 kΩ +13.5 +13.9 V
RL = 10 kΩ −13.9 −13.5 V
Source 3 10 mA

f = 1 MHz 200 Ω

VO = 0 V, −40°C ≤ TA ≤ 85°C 210 250 µA
±4.5 ±18 V

1% distortion 125 kHz
To 0.01% 1.6 µs

55 Degrees

f = 1 kHz 36

0.01

nV/√
pA/√

Hz
Hz

1

The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.

Rev. F | Page 3 of 16

OP282/OP482

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameters Ratings

Supply Voltage ±18 V
Input Voltage ±18 V
Differential Input Voltage

1

36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range

P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C

Operating Temperature Range

OP282G, OP282A, OP482G −40°C to +85°C

Junction Temperature Range

P-Suffix (N), S-Suffix (R), RM Packages −65°C to +150°C

Lead Temperature Range (Soldering 60 sec) 300°C

1

For supply voltages less than ±18 V, the absolute maximum input voltage is

equal to the supply voltage.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 3.

Package Type θ

8-Lead MSOP [RM] 206 44 °C/W
8-Lead SOIC (S-Suffix) [R] 157 56 °C/W
14-Lead PDIP (P-Suffix) [N] 83 39 °C/W
14-Lead SOIC (S-Suffix) [R] 104 36 °C/W

1

θJA is specified for the worst-case conditions; i.e., θJA is specified for device in

socket for CERDIP, PDIP; θ
for SOIC or MSOP package.

1

JA

is specified for device soldered in circuit board

JA

θ

Unit

JC

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. F | Page 4 of 16

OP282/OP482

TYPICAL PERFORMANCE CHARACTERISTICS

80

60

40

20

0

OPEN-LOOP GAIN (dB)

–20

–40

1k

10k 1M 10M

100k

FREQUENCY (Hz)

Figure 5. OP282 Open-Loop Gain and Phase vs. Frequency

VS = ±15V

= 25°C

T

A

180

135

90

45

0

–45

–90

PHASE (Degree)

00301-005

70

60

50

A

= 1

00

VCL

40

30

A

= 1

0

VCL

20

10

A

= 1

VCL

0

CLOSED-LOOP GAIN (dB)

–10

–20

–30

1k

10k 1M 10M

100k

FREQUENCY (Hz)

Figure 8. OP282 Closed-Loop Gain vs. Frequency

VS = ±15V

= 25°C

T

A

00301-008

OPEN-LOOP GAIN (V/mV)

45

40

35

30

25

20

15

10

5

0

–75

–25 100 125

25

TEMPERATURE (°C)

75500–50

VS = ±15V

= 10kΩ

R

L

Figure 6. OP282 Open-Loop Gain vs. Temperature

80

VS = ±15V

= 2kΩ

R

L

70

= 100mV p-p

V

IN

A

= 1

VCL

TA = 25°C

60

50

40

30

OVERSHOOT (%)

20

10

0

0

LOAD CAPACITANCE (pF)

+OS

–OS

200 400 500

300100

Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance

00301-006

00301-007

30

25

20

15

10

SLEW RATE (V/µs)

5

0

–75

–25 100 125

TEMPERATURE (°C)

–SR

+SR

25

Figure 9. OP282 Slew Rate vs. Temperature

1000

VS = ±15V

= 0V

V

CM

100

10

1

INPUT BIAS CURRENT (pA)

0.1
–75

–25 100 125

25

TEMPERATURE (°C)

Figure 10. OP282 Input Bias Current vs. Temperature

75500–50

75500–50

VS = ±15V

= 10kΩ

R

L

= 50pF

C

L

00301-009

00301-010

Rev. F | Page 5 of 16

OP282/OP482

1000

100

VS = ±15V

= 25°C

T

A

20

15

10

5

0

TA = 25°C

= 10kΩ

R

L

V

OH

10

VOLTAGE NOISE DENSITY (nV/ Hz)

1

10

100 10k

FREQUENCY (Hz)

1k

Figure 11. OP282 Voltage Noise Density vs. Frequency

1000

VS = ±15V
T

= 25°C

A

100

10

1

INPUT BIAS CURRENT (pA)

0.1
–15

–5

COMMON-MODE VOLTAGE (V)

50–10

10 15

Figure 12. OP282 Input Bias Current vs. Common-Mode Voltage

00301-011

00301-012

–5

–10

OUTPUT VOLTAGE SWING (V)

–15

–20

0

SUPPLY VOLTAGE (V)

±10

V

OL

±15±5

Figure 14. OP282 Output Voltage Swing vs. Supply Voltage

1000

VS = ±15V

= 25°C

T

A

100

)

Ω

A

= 100

VCL

10

A

= 10

VCL

1

OUTPUT IMPEDANCE (

A

= 1

VCL

0.1
1k

10k 1M100

FREQUENCY (Hz)

100k

Figure 15. OP282 Closed-Loop Output Impedance vs. Frequency

±20

00301-014

00301-015

480

TA = 25°C

475

A)

µ

470

465

460

SUPPLY CURRENT (

455

450

0

±10

SUPPLY VOLTAGE (V)

Figure 13. OP282 Supply Current vs. Supply Voltage

480

475

470

465

460

SUPPLY CURRENT (µA)

455

00301-013

±15±5

±20

450

–50

–25 50 100

25

TEMPERATURE (°C)

750

125

00301-016

Figure 16. OP282 Supply Current vs. Temperature

Rev. F | Page 6 of 16

OP282/OP482

16

14

12

10

8

VS = ±15V

= 25°C

T

A

V

OL

V

OH

30

25

20

15

VS = ±15V

= 25°C

T

A

R

= 10kΩ

L

= 1

A

VCL

6

4

ABSOLUTE OUTPUT VOLTAGE (V)

2

0

LOAD RESISTANCE (Ω)

1k 10k100

Figure 17. OP282 Absolute Output Voltage vs. Load Resistance

140

VS = ±15V

T

= 25°C

A

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

–60

1k

10k 1M100

FREQUENCY (Hz)

+PSRR

–PSRR

100k

Figure 18. OP282 PSRR vs. Frequency

00301-017

00301-018

10

5

MAXIMUM OUTPUT SWING (V p-p)

0

100

1k 100k 1M

10k

FREQUENCY (Hz)

Figure 20. OP282 Maximum Output Swing vs. Frequency

140

120

100

80

60

40

20

CMRR (dB)

0

–20

–40

–60

1k

10k 1M100

FREQUENCY (Hz)

100k

Figure 21. OP282 CMRR vs. Frequency

VS = ±15V

= 25°C

T

A

00301-020

00301-021

14

12

10

SHORT-CIRCUIT CURRENT (mA)

8

6

4

2

0

–50

–25 50 100

25

TEMPERATURE (°C)

SINK

SOURCE

750

Figure 19. OP282 Short-Circuit Current vs. Temperature

VS = ±15V

00301-019

125

Rev. F | Page 7 of 16

200

160

120

UNITS

80

40

0

–2000

–1200

Figure 22. OP282 V

0

–400

OS

400 1200 2000

VOS (µV)

Distribution SOIC Package

VS = ±15V
T

= 25°C

A

300 × OP282
(600 OP AMPS)

00301-022

OP282/OP482

400

360

320

280

240

200

UNITS

160

120

80

40

0

0

4128

Figure 23. OP282 TCV

VS = ±15V
300 × OP282
(600 OP AMPS)

20

16

TCVOS (µV/°C)

Distribution SOIC Package

OS

28 32 3624

00301-023

70

60

50

40

30

OVERSHOOT (%)

20

10

0

VS = ±15V

= 2k

Ω

R

L

VIN = 100mV p-p

100 200 400

LOAD CAPACITANCE (pF)

A

= 1

VCL

NEGATIVE EDGE

A

= 1

VCL

POSITIVE EDGE

300

Figure 26. OP482 Small Signal Overshoot vs. Load Capacitance

00301-026

5000

80

60

40

20

OPEN-LOOP GAIN (dB)

0

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 24. OP482 Open-Loop Gain, Phase vs. Frequency

35

30

25

20

15

10

OPEN-LOOP GAIN (V/mV)

5

VS = ±15V

= 25°C

T

A

VS = ±15V
R

= 10kΩ

L

0

45

90

135

180

PHASE (Degrees)

00301-024

60

50

A

= 100

VCL

40

30

A

= 10

VCL

20

10

A

= 1

VCL

CLOSED-LOOP GAIN (dB)

0

–10

–20

1k 10k 100k 1M 100M10M

FREQUENCY (Hz)

Figure 27. OP482 Closed-Loop Gain vs. Frequency

25

–SR

20

15

10

+SR

SLEW RATE (V/µs)

5

VS = ±15V

T

= 25°C

A

VS = ±15V
R

= 10kΩ

L

C

= 50pF

L

00301-027

0

TEMPERATURE (°C)

Figure 25. OP482 Open-Loop Gain (V/mV)

00301-025

12510050 75250–75 –50 –25

Rev. F | Page 8 of 16

0

–75

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 28. OP482 Slew Rate vs. Temperature

00301-028

OP282/OP482

1000

VS = ±15V

= 0V

V

CM

1000

VS = ±15V

= 25°C

T

A

100

10

1.0

INPUT BIAS CURRENT (pA)

0.1
050

TEMPERATURE (°C)

Figure 29. OP482 Input Bias Current vs. Temperature

60

55

50

PHASE MARGIN (Degrees)

45

GBW

VS= ±15V

= 10kΩ

R

L

00301-029

125–25–50 250 75 100

5.0

4.5

4.0

3.5

GAIN BANDWIDTH PRODUCT (MHz)

100

10

1

INPUT BIAS CURRENT (pA)

0.1

COMMON-MODE VOLTAGE (V)

Figure 32. OP482 Input Bias Current vs. Common-Mode Voltage

1.15

1.10

1.05

1.00

0.95

0.90

RELATIVE SUPPLY CURRENT (ISY)

TA = 25°C

00301-032

15–15 0 5 10–10 –5

40

–75

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

3.0

Figure 30. OP482 Phase Margin and Gain Bandwidt h Product vs. Temperature

80

70

60

50

40

30

GE NOISE DENSITY (nV/ Hz)

20

VOLTA

10

0

10 100 1k 10k

FREQUENCY (Hz)

VS = ±15V

= 25°C

T

A

00301-031

Figure 31. OP482 Voltage Noise Density vs. Frequency

00301-030

0.85

SUPPLY VOLTAGE (V)

±150±±10±5

Figure 33. OP482 Relative Supply Current vs. Supply Voltage

20

RL = 10k

Ω

TA = 25°C

15

10

5

0

–5

–10

OUTPUT VOLTAGE SWING (V)

–15

–20

SUPPLY VOLTAGE (V)

±150±10±5 ±20

Figure 34. OP482 Output Voltage Swing vs. Supply Voltage

00301-033

20

00301-034

Rev. F | Page 9 of 16

OP282/OP482

600

500

VS = ±15V

T

= 25°C

A

100

+PSRR

80

VS = ±15V

∆

V = 100mV

T

= 25°C

A

400

)

Ω

300

IMPEDANCE (

200

A

= 100

100

VCL

0

FREQUENCY (Hz)

A

= 10

VCL

A

= 1

VCL

Figure 35. OP482 Closed-Loop Output Impedance vs. Frequency

1.20

1.15

1.10

1.05

1.00

0.95

0.90

RELATIVE SUPPLY CURRENT (ISY)

0.85

0.80
–50–75 1251007550250–25

TEMPERATURE (°C)

VS = ±15V

Figure 36. OP482 Relative Supply Current vs. Temperature

60

40

PSRR (dB)

20

0

00301-035

1M1k100 100k10k

20

–PSRR

FREQUENCY (Hz)

00301-038

1M1k100 100k10k

Figure 38. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency

00301-036

20

15

10

5

SHORT-CIRCUIT CURRENT (mA)

0

SINK

SOURCE

TEMPERATURE (°C)

VS = ±15V

00301-039

75–75 0 25 50–50 –25 100 125

Figure 39. OP482 Short-Circuit Current vs. Temperature

16

VS = ±15V

= 25°C

T

A

14

12

10

8

6

4

ABSOLUTE OUTPUT VOLTAGE (V)

2

0

POSITIVE
SWING

NEGATIVE
SWING

LOAD RESISTANCE (Ω)

10k1k100

Figure 37. OP482 Maximum Output Voltage vs. Load Resistance

00301-037

Rev. F | Page 10 of 16

30

25

20

15

10

MAXIMUM OUTPUT SWING (V)

5

0

1K

FREQUENCY (Hz)

100K10K

Figure 40. OP482 Maximum Output Swing vs. Frequency

VS = ±15V
T

= 25°C

A

= 1

A

VCL

= 10kΩ

R

L

1M

00301-040

OP282/OP482

100

320

80

60

40

CMRR (dB)

20

0

VS = ±15V
T

= 25°C

A

= 100mV

V

–20

CM

FREQUENCY (Hz)

00301-041

1M1k100 100k10k

Figure 41. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency

700

600

500

400

UNITS

300

200

VS = ±15V
T

= 25°C

A

300 × OP482
(1200 OP AMPS)

280

240

200

160

UNITS

120

80

40

0

0

TCV

(µV/°C)

Figure 43. OP482 TCV

OS

Distribution P Package

OS

32282412 201684

00301-043

100

0

–1600–2000

Figure 42. OP482 V

–400–800–1200

(µV)

V

OS

Distribution P Package

OS

160012008004000

00301-045

2000

Rev. F | Page 11 of 16

OP282/OP482

APPLICATIONS INFORMATION

The OP282 and OP482 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.

HIGH-SIDE SIGNAL CONDITIONING

There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s were tested and are
guaranteed over a common-mode range (−11 V ≤ V
that includes the positive supply.

One application where this is commonly used is in the sensing
of power supply currents. This enables it to be used in current
sensing applications, such as the partial circuit shown in Figure 44.
In this circuit, the voltage drop across a low value resistor, such
as the 0.1 Ω shown here, is amplified and compared to 7.5 V.
The output can then be used for current limiting.

15V

100k

0.1

Ω

500k

Ω

100k

Ω

Ω

≤ +15 V)

CM

R

L

PHASE INVERSION

Most JFET-input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
OP282/OP482, negative signals in excess of approximately 14 V
cause phase inversion. The cause of this effect is saturation of
the input stage leading to the forward-biasing of a drain-gate
diode. A simple fix for this in noninverting applications is to
place a resistor in series with the noninverting input. This limits
the amount of current through the forward-biased diode and
prevents the shutting down of the output stage. For the
OP282/OP482, a value of 200 kΩ has been found to work;
however, this adds a significant amount of noise.

15

10

5

0

OUT

V

–

5

–

10

–

15

–15 –10 –5 5 10 15

Figure 45. OP282 Phase Reversal

0

V

IN

ACTIVE FILTERS

The wide bandwidth and high slew rates of the OP282/OP482

500k

Ω

Figure 44. High-Side Signal Conditioning

1/2

OP282

00301-046

make either an excellent choice for many filter applications.

There are many active filter configurations, but the four most
popu lar configu rat ions are Butterworth, E lliptical, Bess el, and
Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table 4.

Table 4.

Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band)

Butterworth Moderate Good Maximum Flat
Chebyshev Good Moderate Nonlinear Equal Ripple
Elliptical Best Poor Equal Ripple Equal Ripple
Bessel (Thompson) Poor Best Linear

00301-047

Rev. F | Page 12 of 16

OP282/OP482

PROGRAMMABLE STATE-VARIABLE FILTER

The circuit shown in Figure 46 can be used to accurately
program the Q, the cutoff frequency f
state variable filter. OP482s have been used in this design
because of their high bandwidths, low power, and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.

The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC’s resistive ladders. This makes
this circuit unusually accurate for a programmable filter.

Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the amount
of signal current that charges the integrating capacitor, C1. This
cutoff frequency can now be expressed as

V

IN

DAC8408

1/4

1/4

OP482

R5

2kΩ

, and gain of a 2-pole

C

R4

2kΩ

1/4

OP482

HIGH PASS

1/4

DAC8408

OP482

1/4

1 D1

=

fc

R1C1

where

D1 is the digital code for the DAC.

The gain of this circuit is set by adjusting

R4

⎛

=

Gain

R5

⎜
⎝

⎛
⎜

⎝

D3

256

⎞
⎟

2562π

⎠

D3. The gain equation is

⎞
⎟
⎠

DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.

256

R2

⎛
⎜
⎝

D2R3

R7

2kΩ

DAC8408

⎞
⎟
⎠

C1

1000pF

1/4

1/4

OP482

R1

2kΩ

1/4

OP482

R1

2kΩ

Q

=

C1

1000pF

1/4

OP482

LOW

PASS

2kΩ

R6

R3

2kΩ

R2

2kΩ

1/4

OP482

1/4

OP482

Figure 46.

1/4

DAC8408

BAND PASS

00301-048

Rev. F | Page 13 of 16

OP282/OP482

OUTLINE DIMENSIONS

4.00 (0.1574)

3.80 (0.1497)

5.00 (0.1968)

4.80 (0.1890)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 47. 8-Lead Standard Small Outline Package [SOIC]

Narrow-Body S-Suffix (R-8)

Dimensions shown in millimeters and (inches)

3.00

BSC

8

5

4

SEATING
PLANE

4.90

BSC

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 48. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

× 45°

Rev. F | Page 14 of 16

OP282/OP482

Y

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14
1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

8

6.20 (0.2441)

7

5.80 (0.2283)

SEATING
PLANE

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8°
0°

Figure 49. 14-Lead Standard Small Outline Package [SOIC]

Narrow-Body S-Suffix (R-14)

Dimensions shown in millimeters and (inches)

0.685 (17.40)

0.665 (16.89)

0.645 (16.38)

14
17

0.100 (2.54)
BSC

0.015 (0.38)

0.180 (4.57)
MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

COMPLIANT TO JEDEC STANDARDS MO-095-AB

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

8

MIN

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

SEATING
PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

Figure 50. 14-Lead Plastic Dual-in-Line Package [PDIP]

P-Suffix (N-14)

Dimension shown in inches and (millimeters)

1.27 (0.0500)

0.40 (0.0157)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

× 45°

Rev. F | Page 15 of 16

OP282/OP482

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

OP282ARMZ-R2
OP282ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 A0B
OP282GS −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GS-REEL −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GS-REEL7 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ1 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ-REEL1 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP282GSZ-REEL71 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
OP482GP −40°C to +85°C 14-Lead PDIP P-Suffix (N-14)
OP482GS −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GS-REEL −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GS-REEL7 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ1 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ-REEL1 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)
OP482GSZ-REEL71 −40°C to +85°C 14-Lead SOIC S-Suffix (R-14)

1

Z = Pb-free part.

1

−40°C to +85°C 8-Lead MSOP RM-8 A0B

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C00301–0–10/04(F)

Rev. F | Page 16 of 16