Datasheet OP481, OP281, OP181 Datasheet (Analog Devices)

Ultralow Power, Rail-to-Rail Output

NC = NO CONNECT

8
7
6
5

1
2
3
4

NULL

V+

NULL

NC

OUT A

–IN A
+IN A

V–

OP181

NC = NO CONNECT

NULL

V+

NULL

NC

OUT A

–IN A
+IN A

V–

1

4

5

8

OP181

8
7
6
5

1
2
3
4

OP281

OUT A

V+

+IN B

–IN B

OUT B

–IN A
+IN A

V–

OUT A

V+
OUT B–IN A

+IN A

V–

+IN B

–IN B

1

4

5

8

OP281

14
13
12
11
10

9
8

1
2
3
4

7

6

5

OUT A

V–

+IN D

–IN D

OUT D
–IN A
+IN A

V+

OUT C

–IN C

+IN C

+IN B
–IN B

OUT B

OP481

1

7

8

14

OP481

a

FEATURES
Low Supply Current: 4 mA/Amplifier max
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Offset Voltage: 1.5 mV
No Phase Reversal

APPLICATIONS
Comparator
Battery Powered Instrumentation
Safety Monitoring
Remote Sensors
Low Voltage Strain Gage Amplifiers

GENERAL DESCRIPTION

The OP181, OP281 and OP481 are single, dual and quad
ultralow power, single-supply amplifiers featuring rail-to-rail
outputs. All operate from supplies as low as 2.0 V and are
specified at +3 V and +5 V single supply as well as ±5 V dual
supplies.

Fabricated on Analog Devices’ CBCMOS process, the OP181
family features a precision bipolar input and an output that
swings to within millivolts of the supplies and continues to sink
or source current all the way to the supplies.

Applications for these amplifiers include safety monitoring,
portable equipment, battery and power supply control, and
signal conditioning and interface for transducers in very low
power systems.

The output’s ability to swing rail-to-rail and not increase supply
current, when the output is driven to a supply voltage, enables
the OP181 family to be used as comparators in very low power
systems. This is enhanced by their fast saturation recovery time.
Propagation delays are 250 µs.

The OP181/OP281/OP481 are specified over the extended
industrial (–40°C to +85°C) temperature range. The OP181,
single, and OP281, dual, amplifiers are available in 8-pin plastic
DIPs and SO surface mount packages. The OP281 is also
available in 8-lead TSSOP. The OP481 quad is available in 14­pin DIPs, narrow 14-pin SO and TSSOP packages.

Operational Amplifiers

OP181/OP281/OP481

PIN CONFIGURATIONS

8-Lead SO 8-Lead Epoxy DIP

(S Suffix) (P Suffix)

8-Lead SO 8-Lead Epoxy DIP

(S Suffix) (P Suffix)

8-Lead TSSOP

(RU Suffix)

1

8

OP281

4

5

14-Lead Epoxy DIP 14-Lead

(P Suffix) Narrow-Body SO

14-Lead TSSOP

NOTE: PIN ORIENTATION IS EQUIVALENT FOR
EACH PACKAGE VARIATION

(S Suffix)

(RU Suffix)

1

14

OP481

78

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1996

OP181/OP281/OP481–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ VS = +3.0 V, VCM = 1.5 V, TA = +258C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current I
Input Offset Current I

OS

B
OS

Note 1 1.5 mV
–40°C ≤ T

≤ +85°C 2.5 mV

A

–40°C ≤ TA ≤ +85°C310nA
–40°C ≤ TA ≤ +85°C 0.1 7 nA

Input Voltage Range 0 2 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A
Offset Voltage Drift ∆V

Bias Current Drift ∆I

VO

/∆T10µV/°C

OS

/∆T 20 pA/°C

B

= 0 V to 2.0 V,

CM

–40°C ≤ T
R

= 1 MΩ, V

L

–40°C ≤ T

≤ +85°C6595 dB

A

= 0.3 V to 2.7 V 5 13 V/mV

O

≤ +85°C 2 V/mV

A

Offset Current Drift ∆IOS/∆T 2 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short Circuit Limit I

OH

OL

SC

R

= 100 kΩ to GND,

L

–40°C ≤ T
R

= 100 kΩ to V+,

L

–40°C ≤ T

≤ +85°C 2.925 2.96 V

A

≤ +85°C2575mV

A

±1.1 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

Supply Current/Amplifier I

SY

= 2.7 V to 12 V

S

–40°C ≤ T
V

= 0 V 3 4 µA

O

≤ +85°C7695 dB

A

–40°C ≤ TA ≤ +85°C5µA

DYNAMIC PERFORMANCE

Slew Rate SR R
Turn On Time A
Turn On Time A

= 100 kΩ, C

L

= 1, V

V

= 20, V

V

= 1 40 µs

O

O

= 50 pF 25 V/ms

L

= 1 50 µs

Saturation Recovery Time 65 µs
Gain Bandwidth Product GBP 95 kHz
Phase Margin φo 70 Degrees

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e
Current Noise Density i

NOTES

1

VOS is tested under no load condition.

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 10 µV p-p

n
n

n

f = 1 kHz 75 nV/√Hz

<1 pA/√Hz

–2–

REV. 0

OP181/OP281/OP481

ELECTRICAL SPECIFICATIONS

(@ VS = +5.0 V, VCM = 2.5 V, TA = +258C unless otherwise noted1)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current I
Input Offset Current I

OS

B
OS

Note 1 0.1 1.5 mV
–40°C ≤ T

≤ +85°C 2.5 mV

A

–40°C ≤ TA ≤ +85°C310nA
–40°C ≤ TA ≤ +85°C 0.1 7 nA

Input Voltage Range 0 4 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A
Offset Voltage Drift ∆V

Bias Current Drift ∆I

VO

/∆T –40°C to +85°C10µV/°C

OS

/∆T20pA/°C

B

= 0 V to 4.0 V,

CM

–40°C ≤ T
R

= 1 MΩ , V

L

–40°C ≤ T

≤ +85°C6590 dB

A

= 0.5 V to 4.5 V 5 15 V/mV

O

≤ +85°C 2 V/mV

A

Offset Current Drift ∆IOS/∆T2pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High V

Output Voltage Low V

Short Circuit Limit I

OH

OL

SC

R

= 100 kΩ to GND,

L

–40°C ≤ T
R

= 100 kΩ to V+,

L

–40°C ≤ T

≤ +85°C 4.925 4.96 V

A

≤ +85°C2575mV

A

±3.5 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

Supply Current/Amplifier I

SY

= 2.7 V to 12 V,

S

–40°C ≤ T
V

= 0 V 3.2 4 µA

O

≤ +85°C7695 dB

A

–40°C ≤ TA ≤ +85°C5µA

DYNAMIC PERFORMANCE

Slew Rate SR R

= 100 kΩ, C

L

= 50 pF 27 V/ms

L

Saturation Recovery Time 120 µs
Gain Bandwidth Product GBP 100 kHz
Phase Margin φo 74 Degrees

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e
Current Noise Density i

NOTES

1

VOS is tested under a no load condition.

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 10 µV p-p

n
n

n

f = 1 kHz 75 nV/√Hz

<1 pA/√Hz

REV. 0

–3–

OP181/OP281/OP481–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ VS = ±5 V, TA = +258C unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current I
Input Offset Current I

OS

B
OS

Note 1 0.1 1.5 mV
–40°C ≤ T

≤ +85°C 2.5 mV

A

–40°C ≤ TA ≤ +85°C310nA
–40°C ≤ TA ≤ +85°C 0.1 7 nA

Input Voltage Range –5 +4 V
Common-Mode Rejection CMRR V

Large Signal Voltage Gain A
Offset Voltage Drift ∆V

Bias Current Drift ∆I

VO

/∆T –40°C to +85°C10µV/°C

OS

/∆T 20 pA/°C

B

= –5.0 V to +4.0 V,

CM

–40°C ≤ T
R

= 1 MΩ, VO = ±4.0 V, 5 13 V/mV

L

–40°C ≤ T

≤ +85°C6595dB

A

≤ +85°C 2 V/mV

A

Offset Current Drift ∆IOS/∆T 2 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing V

Short Circuit Limit I

O

SC

R

= 100 kΩ to GND,

L

–40°C ≤ T

≤ +85°C ±4.925 ±4.98 V

A

12 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

Supply Current/Amplifier I

SY

= ±1.35 V to ±6V,

S

–40°C ≤ T
V

= 0 V 3.3 5 µA

O

≤ +85°C7695dB

A

–40°C ≤ TA ≤ +85°C6µA

DYNAMIC PERFORMANCE

Slew Rate ±SR R

= 100 kΩ, C

L

= 50 pF 28 V/ms

L

Gain Bandwidth Product GBP 105 kHz
Phase Margin φo 75 Degrees

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e
Voltage Noise Density e
Current Noise Density i

NOTES

1

VOS is tested under no load condition.

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 10 µV p-p

n
n
n

n

f = 1 kHz 85 nV/√Hz
f = 10 kHz 75 nV/√Hz

<1 pA/√Hz

–4–

REV. 0

OP181/OP281/OP481

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . Gnd to V

+ 10 V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.5 V

Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite

Storage Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP181/OP281/OP481G . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C

Package Type uJA* u

JC

Units

8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W
8-Pin TSSOP (RU) 240 43 °C/W
14-Pin Plastic DIP (P) 76 33 °C/W
14-Pin SOIC (S) 120 36 °C/W
14-Pin TSSOP (RU) 240 43 °C/W

*θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket

for P-DIP packages; θJA is specified for device soldered in circuit board for TSSOP
and SOIC packages.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP181GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP181GS –40°C to +85°C 8-Pin SOIC SO-8
OP281GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP281GS –40°C to +85°C 8-Pin SOIC SO-8
OP281GRU –40°C to +85°C 8-Pin TSSOP RU-8
OP481GP –40°C to +85°C 14-Pin Plastic DIP N-14
OP481GS –40°C to +85°C 14-Pin SOIC SO-14
OP481GRU –40°C to +85°C 14-Pin TSSOP RU-14

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP181/OP281/OP481 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau­tions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

OP181/OP281/OP481–Typical Characteristics

45

VS = +2.7V

40

T

= +258C

A

35
30
25
20
15

QUANTITY – Amplifiers

10

5
0

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

INPUT OFFSET VOLTAGE – mV

Figure 1. Input Offset Voltage
Distribution

0

–0.5

VS = +5V

–1.0
–1.5

–2.0
–2.5

–3.0
–3.5

INPUT BIAS CURRENT – nA

–4.0
–4.5

–5.0

–40

–20020406080

TEMPERATURE – 8C

100 120

50

VS = +5V

45

T

= +258C

A

40
35
30
25
20
15

QUANTITY – Amplifiers

10

5
0

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

INPUT OFFSET VOLTAGE – mV

Figure 2. Input Offset Voltage
Distribution

1.0
VS = +5V

0.5
T

= +258C

A

0.0

–0.5
–1.0

–1.5

–2.0
–2.5

INPUT BIAS CURRENT – nA

–3.0
–3.5

0.0

0.5 1.0 1.5 2.0 2.5 3.0

COMMON-MODE VOLTAGE – Volts

3.5 4.0

4.5 5.0

2000
1800

VS = +5V

1600
1400
1200
1000

800
600
400

INPUT OFFSET VOLTAGE – µV

200

0

–40

–20020406080

TEMPERATURE – 8C

100 120

Figure 3. Input Offset Voltage vs.
Temperature

0.5

0.4

0.3

0.2

0.1

0

–0.1
–0.2

INPUT OFFSET CURRENT – nA

–0.3
–0.4

–40

–20 0 20 40 60 80

TEMPERATURE – 8C

VS = +5V

100 120

Figure 4. Input Bias Current vs.
Temperature

10,000

VS = +3V
TA = +258C

1,000

100

10

1.0

OUTPUT VOLTAGE – mV

0.1
1 1000

SOURCE

SINK

10 100

LOAD CURRENT – µA

Figure 7. Output Voltage to Supply
Rail vs. Load Current

Figure 5. Input Bias Current vs.
Common-Mode Voltage

1,000

VS = +5V
TA = +258C

100

10

1.0

OUTPUT VOLTAGE – mV

0.1
1 1000

SOURCE

SINK

10 100

LOAD CURRENT – µA

Figure 8. Output Voltage to Supply
Rail vs. Load Current

Figure 6. Input Offset Current vs.
Temperature

1,000

VS = ±5V
TA = +258C

100

10

1.0

OUTPUT VOLTAGE – mV

0.1
1 1000

SOURCE

SINK

10 100

LOAD CURRENT – µA

Figure 9. Output Voltage to Supply
Rail vs. Load Current

–6–

REV. 0

OP181/OP281/OP481

FREQUENCY – Hz

OPEN-LOOP GAIN – dB

70
60

–30

100 1k 1M

10k 100k

20

50
40
30

10

0
–10
–20

VS = +2.7V
T

A

= +258C

R

L

= 100kΩ

90

0
45

135
180
225
270

PHASE SHIFT – Degrees

FREQUENCY – Hz

VS = +5V
T

A

= +258C

MARKER @ 67nV/√Hz

02k4k6k8k10k

50nV/√Hz/Div

70
60
50
40
30
20
10

0

OPEN-LOOP GAIN – dB

–10
–20

–30

100 1k 1M

FREQUENCY – Hz

VS = +5V
T

A

R

L

10k 100k

= +258C
= 100kΩ

0
45
90
135
180
225
270

Figure 10. Open-Loop Gain and Phase
vs. Frequency

70
60
50
40
30
20
10

0

OPEN-LOOP GAIN – dB

–10
–20

–30

100 1k 1M

VS = ±5V
T

= +258C

A

R

= 100kΩ TO GROUND

L

10k 100k

FREQUENCY – Hz

0
45
90
135
180
225
270

70
60
50
40
30
20
10

0

OPEN-LOOP GAIN – dB

–10

PHASE SHIFT – Degrees

–20
–30

100 1k 1M

FREQUENCY – Hz

VS = +3V
T

A

R

L

10k 100k

= +258C
= 100kΩ

Figure 11. Open-Loop Gain and Phase
vs. Frequency

60
50
40
30
20
10

0

–10

CLOSED-LOOP GAIN – dB

PHASE SHIFT – Degrees

–20
–30
–40

10 100 1M1k 10k 100k

FREQUENCY – Hz

VS = +5V

= +258C

T

A

= INFINITE

R

L

0
45
90
135
180
225

PHASE SHIFT – Degrees

270

Figure 12. Open-Loop Gain and Phase
vs. Frequency

Figure 13. Open-Loop Gain and Phase
vs. Frequency

90

VS = ±5V

80
70
60
50
40
30

CMRR – dB

20
10

–10

VS = +5V

VS = +3V

0

1k 10k 10M100k 1M

FREQUENCY – Hz

Figure 16. CMRR vs. Frequency

REV. 0

TA = +258C

Figure 14. Closed-Loop Gain vs.
Frequency

160
140
120
100

80
60
40

PSRR – dB

20

0
–20
–40

10 100 1M1k 10k 100k

VS = ±5V, +5V, +3V, +2.7V
T

= +258C

A

R

= INFINITE

L

FREQUENCY – Hz

Figure 17. PSRR vs. Frequency

–7–

Figure 15. Voltage Noise Density vs.
Frequency

50

VS = +5V

45

V

= ±50mV

IN

R

= 100kΩ

L

40

T

= +258C

A

35
30
25
20
15
10

SMALL SIGNAL OVERSHOOT – %

5
0

10 100 1000

CAPACITANCE – pF

–OS

+OS

Figure 18. Small Signal Overshoot vs.
Load Capacitance

OP181/OP281/OP481

TEMPERATURE – 8C

SUPPLY CURRENT/AMPLIFIER – µA

4.0

1.5

0

–40

–20 0 20 40 60 80 100 120

3.5

2.0

1.0

0.5

3.0

2.5

VS = +3V

10

0%

100

90

0mV

A2

100µs

50mV

VS = ±2.5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C

10

0%

100

90

0.50V

A2

100µs

500mV

VS = +2.7V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C

5

4

VS = +5V
V

= 4Vp–p

IN

3

R

= INFINITE

L

T

= +258C

A

2

1

MAXIMUM OUTPUT SWING – Vp-p

0

10 100 100k

1k 10k

FREQUENCY – Hz

Figure 19. Maximum Output Swing
vs. Frequency

4.5
VS = +5V

4.0

3.5

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT/AMPLIFIER – µA

0.5

0

–20 0 20 40 60 80 100 120

–40

TEMPERATURE – 8C

3

2

1

MAXIMUM OUTPUT SWING – Vp-p

0

10 100 100k

FREQUENCY – Hz

VS = +3V
V

= 2Vp–p

IN

R

= INFINITE

L

T

= +258C

A

1k 10k

Figure 20. Maximum Output Swing
vs. Frequency

3.50
TA = +258C

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

SUPPLY CURRENT/AMPLIFIER – µA

0.25

0.00

0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

SUPPLY VOLTAGE – ±Volts

4.55.0 5.5 6.0

Figure 21. Supply Current/Amplifier
vs. Temperature

Figure 22. Supply Current/Amplifier
vs. Temperature

A2

0mV

100

90

10

0%

50mV

Figure 25. Small Signal Transient
Response

100µs

VS = ±1.35V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C

Figure 23. Supply Current/Amplifier
vs. Supply Voltage

100µs1V

VS = +5V
AV = 1
RL = 100kΩ
CL = 50pF
TA = +258C

A2

2.50V

100

90

10
0%

Figure 26. Large Signal Transient
Response

–8–

Figure 24. Small Signal Transient
Response

Figure 27. Large Signal Transient
Response

REV. 0

OP181/OP281/OP481

10
0%

100

90

0.00V

A2

50µs

500mV

VS = 61.35V
RL = ∞

500mV

VIN = 61Vp-p
AT 2kHz

120

A2

2.50V

100

90

VS = +5V
TA = +258C

90
75
60
45
30

105

10

0%

1V

1V

200µs

15

0

CHANNEL SEPARATION – dB

–15
–30

100 1k 1M10k 100k

FREQUENCY – Hz

=

V

+5V

S

=

T

+258C

A

=

R

∞

L

Figure 28. No Phase Reversal

Figure 29. Channel Separation vs.
Frequency

0.00V

500mV

VS = 62.5V
CIRCUIT = A

A2

100

90

10

0%

1V

VOL

100µs

RL = ∞
TA = +258C

Figure 31. Saturation Recovery Time

Figure 30. Saturation Recovery Time

REV. 0

–9–

OP181/OP281/OP481

6

5

7

4

1

2

3

+5V

OP181

V

OUT

20kΩ
POT.

V

EE

= –5V

APPLICATIONS

THEORY OF OPERATION

The OPx81 family of op amps is comprised of extremely low
powered, rail-to-rail output amplifiers, requiring less than 4 µA
of quiescent current per amplifier. Many other competitors’
devices may be advertised as low supply current amplifiers but
draw significantly more current as the outputs of these devices
are driven to a supply rail. The OPx81’s supply current remains
under 4 µA even with the output driven to either supply rail.
Supply currents should meet the specification as long as the inputs
and outputs remain within the range of the power supplies.

Figure 32 shows a simplified schematic of the OP181. A bipolar
differential pair is used in the input stage. PNP transistors are
used to allow the input stage to remain linear with the common­mode range extending to ground. This is an important consider­ation for single supply applications. The bipolar front end also
contributes less noise than a MOS front end with only nano­amps of bias currents. The output of the op amp consists of a
pair of CMOS transistors in a common source configuration.
This setup allows the output of the amplifier to swing to within
millivolts of either supply rail. The headroom required by the
output stage is limited by the amount of current being driven
into the load. The lower the output current, the closer the
output can go to either supply rail. Figures 7, 8 and 9 show the
output voltage headroom versus load current. This behavior is
typical of rail-to-rail output amplifiers.

where: VEE is the negative power supply for the amplifier, and

V

is the lowest input voltage excursion expected

IN, MIN

For example, an OP181 is to be used with a single supply volt­age of 5 V where the input signal could possibly go as low as
–1.0 V. Because the amplifier is powered from a single supply,
V

is ground, so the necessary series resistance should be 2 kΩ.

EE

Input Offset Voltage Nulling

The OPx81 family of op amps was designed for low offset
voltages less than 1 mV. The single OP181 does provide two
offset adjust terminals, should the user require greater precision.
In general, these terminals should be used only to zero amplifier
offsets and should not be used to adjust system offset voltages.

A 20 kΩ potentiometer connected to the offset adjust terminals,
with the wiper connected to V

, can be used to reduce the

EE

offset voltage of the amplifier. The OP181 should be connected
in the unity-gain configuration (as shown in Figure 33) or in a
gain configuration. The potentiometer should be adjusted until
V

is minimized. The wiper of the potentiometer must be

OUT

connected to V

; connecting it to the positive supply rail could

EE

damage the device.

V

CC

+IN

–IN

V

EE

OUT

Figure 32. Simplified Schematic of the OP181

Input Overvoltage Protection

The input stage to the OPx81 family of op amps consists of a
PNP differential pair. If the base voltage of either of these input
transistors drops to more than 0.6 V below the negative supply,
the input ESD protection diodes will become forward biased,
and large currents will begin to flow. In addition to possibly
damaging the device, this will create a phase reversal effect at
the output. To prevent these effects from happening, the input
current should be limited to less than 0.5 mA.

This can be done quite easily by placing a resistor in series with
the input to the device. The size of the resistor should be pro­portional to the lowest possible input signal excursion and can
be found using the following formula:

V

EE−VIN, MIN

R =

0.5×10

−3

Figure 33. Offset Voltage Nulling Circuit

Input Common-Mode Voltage Range

The OPx81 is rated with an input common-mode voltage range
from V

to 1 volt under VCC. However, the op amp can still

EE

operate even with a common-mode voltage that is slightly less
than V

. Figure 34 shows an OP181 configured as a difference

EE

amplifier with a single supply voltage of +3 V. Negative dc
voltages are applied at both input terminals creating a common­mode voltage that is less than ground. A 400 mV p-p input
signal is then applied to the noninverting input. Figure 35 shows
a picture of the input and output waves. Notice how the output
of the amplifier also drops slightly negative without distortion.

100kΩ

100kΩ

+3V

OP181

V

OUT

–0.27V

100kΩ

100kΩ

VIN = 1kHz AT
400mV p-p

–0.1V

Figure 34. OP181 Configured as a Difference Amplifier
Operating at V

–10–

CM

< 0 V

REV. 0

OP181/OP281/OP481

6

7

4

2

3

OP181

10kΩ

0.022µF

V

REF

+1.5V TO +6V1µF

1µF

1MΩ

+3V TO +12V

100Ω

1MΩ

0.2ms

100

90

V

OUT

0V

V

IN

10

0%

0.1V

100

90

10

0%

Figure 35. Input and Output Signals with VCM < 0 V

Overdrive Recovery Time

The amount of time it takes for an amplifier to recover from
saturation can be an important consideration when using an
amplifier as a comparator or when outputs can be driven to the
supplies. The overdrive recovery time for the OP181 is 50 µs
with the amplifier running from a 3 volt supply and increases
to 100 µs with a 10 volt supply. Figure 36 shows the result of
the OP181 running from a 3 V supply with its output being
overdriven.

0.2ms

V

IN

100

SCALE 0.1V

SCALE 1V

90

0V

V

OUT

10

0%

0V

0.1V

VS = +3V
AV = +100

Figure 36. Output of the Op Amp Recovering from
Saturation

Capacitive Loading

Most low supply current amplifiers have difficulty driving
capacitive loads due to the higher currents required from the
output stage for such loads. Higher capacitance at the output
will increase the amount of overshoot and ringing in the
amplifier’s step response and could even affect the stability of
the device. However, through careful design of the output stage
and its high phase margin, the OPx81 family can tolerate some
degree of capacitive loading. Figure 37 shows the step response
of an OP181 with a 10 nF capacitor connected at the output.
Notice that the overshoot of the output does not exceed more
than 10% with such a load, even with a supply voltage of only
+3 V.

Figure 37. Ringing and Overshoot of the Output of the
Amplifier

A Micropower Reference Voltage Generator

Many single supply circuits are configured with the circuit
biased to 1/2 of the supply voltage. In these cases, a false­ground reference can be created by using a voltage divider
buffered by an amplifier. Figure 38 shows the schematic for
such a circuit.

The two 1 MΩ resistors generate the reference voltage while
drawing only 1.5 µA of current from a 3 V supply. A capacitor
connected from the inverting terminal to the output of the op
amp provides compensation to allow for a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
establish an ac ground for the reference output. The entire
reference generator draws less than 5 µA from a 3 V supply
source.

Figure 38. A Micropower Bias Voltage Generator

A Window Comparator

The extremely low power supply current demands of the OPx81
family make it ideal for use in long life battery powered applica­tions such as a monitoring system. Figure 39 shows a circuit
that uses the OP281 as a window comparator.

REV. 0

–11–

OP181/OP281/OP481

5.1kΩ

5.1kΩ

+3V

V

OUT

Q1

+3V

R1

R2

V

IN

2kΩ

+3V

R3

R4

+3V

V

H

A1

D1

10kΩ

OP281-A

+3V

A2

V

L

D2

OP281-B

Figure 39. Using the OP281 as a Window Comparator

The threshold limits for the window are set by VH and VL,
provided that V

> VL. The output of A1 will stay at the

H

negative rail, in this case ground, as long as the input voltage is
less than V
long the input voltage is higher than V
between V

. Similarly, the output of A2 will stay at ground as

H

and VH, the outputs of both op amps will be 0 V.

L

. As long as VIN remains

L

With no current flowing in either D1 or D2, the base of Q1 will
stay at ground, putting the transistor in cutoff and forcing V

OUT

to the positive supply rail. If the input voltage rises above VH,
the output of A2 stays at ground, but the output of A1 will go to
the positive rail, and D1 will conduct current. This creates a
base voltage that will turn on Q1 and drive V
condition occurs if V

falls below VL with A2’s output going

IN

high, and D2 conducting current. Therefore, V
if the input voltage is between V

and VH, and V

L

low. The same

OUT

will be high

OUT

will be low

OUT

if the input voltage moves outside of that range.
The R1 and R2 voltage divider sets the upper window voltage,

and the R3 and R4 voltage divider sets the lower voltage for the
window. For the window comparator to function properly, V

H

must be a greater voltage than VL.

VH=

VL=

R2

R1+R2

R4

R3 + R4

The 2 kΩ resistor connects the input voltage to the input termi­nals to the op amps. This protects the OP281 from possible
excess current flowing into the input stages of the devices. D1
and D2 are small-signal switching diodes (1N4446 or equiva­lent), and Q1 is a 2N2222 or equivalent NPN transistor.

A Low-Side Current Monitor

In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. Figure 40 shows an example
of a +5 V, single-supply current monitor that can be incorpo­rated into the design of a voltage regulator with fold-back
current limiting or a high current power supply with crowbar
protection. The design capitalizes on the OP181’s common­mode range that extends to ground. Current is monitored in the
power supply return path where a 0.1 Ω shunt resistor, R

SENSE

,

creates a very small voltage drop. The voltage at the inverting
terminal becomes equal to the voltage at the noninverting
terminal through the feedback of Q1, which is a 2N2222 or
equivalent NPN transistor. This makes the voltage drop across
R1 equal to the voltage drop across R

. Therefore, the

SENSE

current through Q1 becomes directly proportional to the current
through R

, and the output voltage is given by:

SENSE



V

OUT

= VEE−

R2

× R

R1

SENSE





× I



L





The voltage drop across R2 increases with IL increasing, so
V

decreases with higher supply current being sensed. For

OUT

the element values shown, the V
–2.5 V/A, decreasing from V

V

OUT

+5V

Q1

R2

2.49kΩ

R1
100Ω

0.1Ω

R

SENSE

EE

transfer characteristic is

OUT

.

+5V

OP181

RETURN TO
GROUND

Figure 40. A Low-Side Load Current Monitor

Low Voltage Half-Wave and Full-Wave Rectifiers

Because of its quick overdrive recovery time, an OP281 can be
configured as a full-wave rectifier for low frequency (<500 Hz)
applications. Figure 41 shows the schematic.

R1 = 100kΩ R2 = 100kΩ

+3V

A2

OP281-B

FULL-WAVE
RECTIFIED
OUTPUT

HALF-WAVE
RECTIFIED
OUTPUT

VIN = 2V p-p

+3V

2kΩ

A1

OP281-A

Figure 41. Single Supply Full- and Half-Wave Rectifiers
Using an OP281

100

90

10

0%

SCALE 0.1V/DIV

SCALE 0.1ms/DIV

Figure 42. Full-Wave Rectified Signal

–12–

REV. 0

OP181/OP281/OP481

Amplifier A1 is used as a voltage follower that will only track the
input voltage when it is greater than 0 V. This provides a half­wave rectification of the input signal to the noninverting
terminal of amplifier A2. When A1’s output is following the
input, the inverting terminal of A2 will also follow the input
from the virtual ground between the inverting and noninverting
terminals of A2. With no potential difference across R1, no
current flows through either R1 or R2, therefore the output of
A2 will also follow the input. Now, when the input voltage goes
below 0 V, the noninverting terminal of A2 becomes 0 V. This
makes A2 work as an inverting amplifier with a gain of 1 and
provides a full-wave rectified version of the input signal. A 2 kΩ
resistor in series with A1’s noninverting input protects the
device when the input signal becomes less than ground.

A Battery Powered Telephone Headset Amplifier

Figure 43 shows how the OP281 can be used as a two-way
amplifier in a telephone headset. One side of the OP281 can be
used as an amplifier for the microphone, while the other side
can be used to drive the speaker. A typical telephone headset
uses a 600 Ω speaker and an electret microphone that requires a
supply voltage and a biasing resistor.

0.1µF

11kΩ 300kΩ

+3V

2.2kΩ

INPUT

+3V

1MΩ 1MΩ

ELECTRET
MIC

1µF

1µF

10kΩ

POT.

1µF

1µF

+3V

1MΩ

1MΩ

50kΩ10kΩ

+3V

+3V

20kΩ

OP281-B

20kΩ

1µF

OP281-A

+3V

Q1

Q2

SPEAKER

MIC OUT

1µF

600Ω

Figure 43. A Battery Powered Telephone Headset
Two-Way Amplifier

The OP281-A op amp provides about 29 dB of gain for audio
signals coming from the microphone. The gain is set by the
300 kΩ and 11 kΩ resistors. The gain bandwidth product of the
amplifier is 95 kHz, which, for the set gain of 28, yields a –3 dB
rolloff at 3.4 kHz. This is acceptable since telephone audio is
band limited for 300 kHz to 3 kHz signals. If higher gain is
required for the microphone, an additional gain stage should be
used, as adding any more gain to the OP281 would limit the
audio bandwidth. A 2.2 kΩ resistor is used to bias the electret
microphone. This resistor value may vary depending on the
specifications on the microphone being used. The output of the
microphone is ac coupled to the noninverting terminal of the op
amp. Two 1 MΩ resistors are used to provide the dc offset for
single supply use.

The OP281-B amplifier can provide up to 15 dB of gain for the
headset speaker. Incoming audio signals are ac coupled to a
10 kΩ potentiometer that is used to adjust the volume. Again,
two 1 MΩ resistors provide the dc offset with a 1 µF capacitor
establishing an ac ground for the volume control potentiometer.
Because the OP281 is a rail-to-rail output amplifier, it would
have difficulty driving a 600 Ω speaker directly. Here, a class AB
buffer is used to isolate the load from the amplifier and also
provide the necessary current drive to the speaker. By placing
the buffer in the feedback loop of the op amp, crossover
distortion can be minimized. Q1 and Q2 should have minimum
betas of 100. The 600 Ω speaker is ac coupled to the emitters to
prevent any quiescent current from flowing in the speaker. The
1 µF coupling capacitor makes an equivalent high pass filter
cutoff at 265 Hz with a 600 Ω load attached. Again, this does
not pose a problem, as it is outside the frequency range for
telephone audio signals.

The circuit in Figure 43 draws around 250 µA of current. The
class AB buffer has a quiescent current of 140 µA while roughly
100 µA is drawn by the microphone itself. A CR2032 3 V
lithium battery has a life expectancy of 160 mA hours, which
means this circuit could run continuously for 640 hours on a
single battery.

SPICE Macro-Model

* OP181 SPICE Macro-model
* 9/96, Ver. 1
*
* Copyright 1996 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of this
* model indicates your acceptance of the terms and provisions in
* the License Statement.
*
* Node Assignments
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
*|| | | |
*|| | | |
.SUBCKT OP181 1 2 99 50 45
*
* INPUT STAGE
*
Q1 413PIX
Q2 675PIX
I1 99 8 1.28E-6
EOS 7 2 POLY(1) (12, 98) 80E-6 1
IOS 1 2 1E-10
RC1 4 50 500E3
RC2 6 50 500E3
RE1 3 8 108
RE2 5 8 108
V1 99 13 DC .9
V2 99 14 DC .9
D1 3 13 DX
D2 5 14 DX
*
* CMRR76dB, ZERO AT 1kHz
*

REV. 0

–13–

OP181/OP281/OP481

ECM1 11 98 POLY(2) (1, 98) (2, 98) 0 .5 .5
R1 11 12 1.59E6
C1 11 12 100E-12
R2 12 98 283
*
* POLE AT 900kHz
*
EREF 98 0 (90, 0) 1
G1 98 20 (4, 6) 1E-6
R3 20 98 1E6
C2 20 98 177E-15
*
* POLE AT 500kHz
*
E2 21 98 (20, 98) 1
R4 21 22 1E6
C3 22 98 320E-15
*
* GAIN STAGE
*
CF 45 40 8. 5E-12
R5 40 98 65. 65E6
G3 98 40 (22, 98) 4.08E-7
D3 40 41 DX
D4 42 40 DX
V3 99 41 DC 0.5
V4 42 50 DC 0.5
*
* OUTPUT STAGE
*
ISY 99 50 1.375E-6
RS1 99 90 10E6
RS2 90 50 10E6
M1 45 46 99 99 POX L=1.5u W=300u
M2 45 47 50 50 NOX L=1.5u W=300u
EG1 99 46 POLY(1) (98, 40) 0.77 1
EG2 47 50 POLY(1) (40, 98) 0.77 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01)
.MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01)
.MODEL PIX PNP (BF=200)
.MODEL DX D(IS=1E-14)
.ENDS

–14–

REV. 0

14 8

7

1

0.201 (5.10)

0.193 (4.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256
(0.65)

BSC

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°
0°

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

OP181/OP281/OP481

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

8-Lead Plastic DIP

0.430 (10.92)

0.348 (8.84)

8

14

PIN 1

0.100
(2.54)

BSC

5

0.070 (1.77)

0.045 (1.15)

8-Lead SOIC

0.1968 (5.00)

0.1890 (4.80)

8

5

41

PIN 1

0.0688 (1.75)

0.0532 (1.35)

(N-8)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

(SO-8)

0.2440 (6.20)

0.2284 (5.80)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.0196 (0.50)

0.0099 (0.25)

0.195 (4.95)

0.115 (2.93)

x 45°

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

14-Lead Plastic DIP

(N-14)

0.795 (20.19)

0.725 (18.42)

14

17

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

8

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

14-Lead Narrow Body SOIC

(SO-14)

0.3444 (8.75)

0.3367 (8.55)

14 8

71

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.130
(3.30)
MIN

SEATING
PLANE

0.2440 (6.20)

0.2284 (5.80)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.0196 (0.50)

0.0099 (0.25)

0.195 (4.95)

0.115 (2.93)

x 45°

SEATING

PLANE

0.177 (4.50)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.0500
(1.27)

BSC

0.122 (3.10)

0.114 (2.90)

8

0.169 (4.30)

1

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

8-Lead TSSOP

(RU-8)

5

0.256 (6.50)

0.246 (6.25)

4

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8°
0°

8°
0°

0.0500 (1.27)

0.0160 (0.41)

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0500

0.0192 (0.49)

(1.27)

0.0138 (0.35)

BSC

14-Lead TSSOP

0.0099 (0.25)

0.0075 (0.19)

(RU-14)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

REV. 0

–15–

C2195–12–10/96

–16–

PRINTED IN U.S.A.