Datasheet OP270 Datasheet (Analog Devices)

Dual Very Low Noise Precision

a

FEATURES
Very Low Noise 5 nV/
Excellent Input Offset Voltage 75 ␮V Max
Low Offset Voltage Drift 1 ␮V/ⴗC Max
Very High Gain 1500 V/mV Min
Outstanding CMR 106 dB Min
Slew Rate 2.4 V/␮s Typ
Gain Bandwidth Product 5 MHz Typ
Industry-Standard 8-Lead Dual Pinout

GENERAL DESCRIPTION

The OP270 is a high performance, monolithic, dual operational
amplifier with exceptionally low voltage noise, 5 nV/÷Hz max at
1 kHz. It offers comparable performance to ADI’s industry
standard OP27.

The OP270 features an input offset voltage below 75 mV and an
offset drift under 1 mV/∞C, guaranteed over the full military tem-
perature range. Open-loop gain of the OP270 is over 1,500,000
into a 10 kW load, ensuring excellent gain accuracy and linearity,
even in high gain applications. Input bias current is under 20 nA,
which reduces errors due to signal source resistance. The OP270’s
CMR of over 106 dB and PSRR of less than 3.2 mV/V signifi-
cantly reduce errors due to ground noise and power supply
fluctuations. Power consumption of the dual OP270 is one-third
less than two OP27s, a significant advantage for power conscious
applications. The OP270 is unity-gain stable with a gain bandwidth
product of 5 MHz and a slew rate of 2.4 V/ms.

÷÷

÷Hz @ 1 kHz Max

÷÷

Operational Amplifier

OP270

CONNECTION DIAGRAMS

16-Lead SOIC

(S-Suffix)

1

–IN A

2

+IN A

3

NC

4

V–

5

NC

+IN B

6

–IN B

7

NC

8

NC = NO CONNECT

OP270

16

15

14

13

12

11

10

9

OUT A

NC

NC

V+

NC

NC

OUT B

NC

The OP270 offers excellent amplifier matching, which is important
for applications such as multiple gain blocks, low noise instru­mentation amplifiers, dual buffers, and low noise active filters.

The OP270 conforms to the industry-standard 8-lead DIP pinout.
It is pin compatible with the MC1458, SE5532/A, RM4558, and
HA5102 dual op amps, and can be used to upgrade systems
using those devices.

For higher speed applications, the OP271, with a slew rate of
8V/ms, is recommended. For a quad op amp, see the OP470.

8-Lead PDIP (P-Suffix)

8-Lead CERDIP

(Z-Suffix)

OUT A

–IN A

+IN A

1

2

A

3

4

V–

OP270

8

V+

7

OUT B

B

6

–IN B

5

+IN B

SIMPLIFIED SCHEMATIC

(One of Two Amplifiers Is Shown)

–IN

+IN

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V+

BIAS

OUT

V–

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

OP270–SPECIFICATIONS

(VS = ⴞ15 V, TA=25ⴗC, unless otherwise noted.)

OP270E OP270F OP270G

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Input Offset Voltage V
Input Offset Current l
Input Bias Current I
Input Noise Voltage e

OS

OS

B

p-p 0.1 Hz to 10 Hz 80 200 80 200 80 nV p-p

n

VCM=0 V 1 10 315 520nA
VCM=0 V 5 20 10 40 15 60 nA

10 75 20 150 50 250 mV

(Note 1)

Input Noise f

Voltage Density f

e

n

= 10 Hz 3.6 6.5 3.6 6.5 3.6 nV/

O

= 100 Hz 3.2 5.5 3.2 5.5 3.2 nV/

O

fO= 1 kHz 3.2 5.0 3.2 5.0 3.2 nV/
(Note 2)

Input Noise f

Current Density i

n

Large-Signal V

Voltage Gain A

VO

= 10 Hz 1.1 1.1 1.1 pA/

O

fO = 100 Hz 0.7 0.7 0.7 pA/
f

= 1 kHz 0.6 0.6 0.6 pA/

O

= ± 10 V

O

RL = 10 kW 1500 2300 1000 1700 750 1500 V/mV
R

=2 kW 750 1200 500 900 350 700 V/mV

L

Input Voltage Range IVR (Note3) ± 12 ±12.5 ± 12 ± 12.5 ± 12 ± 12.5 V
Output Voltage Swing V

O

RL≥ 2kW±12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V

Common-Mode

Rejection CMR V

= ± 11 V 106 125 100 120 90 110 dB

CM

Power Supply

Rejection Ratio PSRR V

= ± 4.5 V 0.56 3.2 1.0 5.6 1.5 6 mV/V

S

to ± 18 V

Slew Rate SR 1.7 2.4 1.7 2.4 1.7 2.4 V/ms
Supply Current I

SY

No Load 4 6.5 4 6.5 4 6.5 mA

(All Amplifiers)

Gain Bandwidth GBP 5 5 5 MHz

Product

Channel Separation CS V

= ± 20 V p-p

O

= 10 Hz 125 175 125 175 175 dB

f

O

(Note 1)
Input Capacitance C
Input Resistance R

IN

IN

33 3pF

0.4 0.4 0.4 MW

Differential-Mode

Input Resistance R

INCM

20 20 20 GW

Common-Mode

Settling Time t

S

AV = +1, 10 V 5 5 5 ms

Step to 0.01%

NOTES

1. Guaranteed but not 100% tested.

2. Sample tested.

3. Guaranteed by CMR test.

Specifications subject to change without notice.

÷÷

÷Hz

÷÷
÷÷

÷Hz

÷÷
÷÷

÷Hz

÷÷

÷÷

÷Hz

÷÷
÷÷

÷Hz

÷÷
÷÷

÷Hz

÷÷

–2–

REV. C

SPECIFICATIONS

OP270

ELECTRICAL SPECIFICATIONS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Input Offset Voltage V

OS

(Vs = ⴞ15 V, –40∞C £ TA£ 85ⴗC, unless otherwise noted.)

OP270E OP270F OP270G

25 150 45 275 100 400 mV

Average Input

Offset Voltage Drift TCV
Input Offset Current I
Input Bias Voltage I

OS

OS

B

Large-Signal V

Voltage Gain A

VO

VCM=0 V 1.5 30 5 40 15 50 nA
VCM=0 V 6 60 15 70 19 80 nA

= ± 10 V

O

RL = 10 kW 1000 1800 600 1400 400 1250 V/mV

=2 kW 500 900 300 700 225 670 V/mV

R

L

0.2 1 0.4 2 0.7 3 mV/∞C

Input Voltage Range* IVR ± 12 ± 12.5 ± 12 ± 12.5 ± 12 ± 12.5 V
Output Voltage Swing V

O

RL≥ 2kW±12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V

Common-Mode

Rejection CMR V

= ± 11 V 100 120 94 115 90 100 dB

CM

Power Supply

Rejection Ratio PSRR V

= ± 4.5 V 0.7 5.6 1.8 10 2.0 1.5 mV/V

S

to ± 18 V

Supply Current I

SY

No Load 4.4 7.2 4.4 7.2 4.4 7.2 mA

(All Amplifiers)

* Guaranteed by CMR test.

Specifications subject to change without notice.

REV. C

–3–

OP270

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Differential Input Voltage
Differential Input Current

2

. . . . . . . . . . . . . . . . . . . . . . ± 1.0 V

2

. . . . . . . . . . . . . . . . . . . . ± 25 mA

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage

Output Short-Circuit Duration . . . . . . . . . . . . . . .Continuous

Storage Temperature Range

P, S, Z Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

Junction Temperature (T

) . . . . . . . . . . . . . –65°C to +150°C

J

1

Operating Temperature Range

OP270E, OP270F, OP270G . . . . . . . . . . . –40°C to +85°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

The OP270’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used, in order to achieve low noise performance. If differential
voltage exceeds +10 V, the input current should be limited to ±25 mA.

ORDERING GUIDE

TA = +25°C

Max θ

V

OS

JC

θJA* Temperature Package Package

Model (␮V) (°C/W) (°C/W) Range Description Option

OP270EZ 75 12 134 XIND 8-Lead CERDIP Q-8 (Z-Suffix)
OP270FZ 150 12 134 XIND 8-Lead CERDIP Q-8 (Z-Suffix)
OP270GP 250 37 96 XIND 8-Lead PDIP N-8 (P-Suffix)
OP270GS 250 27 92 XIND 16-Lead SOIC RW-16 (S-Suffix)

*θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device

in socket for CERDIP and PDIP packages; θJA is specified for device soldered to
printed circuit board for SOIC package.

For military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp.

SMD Part Number ADI Equivalent

5962-8872101PA OP270AZMDA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. C

COMMON-MODE VOLTAGE (V)

INPUT BIAS CURRENT (nA)

7

–12.5

2

4

3

6

TA = 25ⴗC
V

S

= ⴞ15V

5

–10.0

–7.5

–5.0

–2.5

0.0

2.5

5.0

7.5

10.0

12.5

Typical Performance Characteristics–

OP270

10

TA = 25ⴗC

9

VS = ⴞ15V

8
7
6

5

4

3

1/f CORNER = 5Hz

10 100 1k
FREQUENCY (Hz)

VOLTA G E NOISE (nV/ Hz)

2

1

1

TPC 1. Voltage Noise Density
vs. Frequency

10

TA = 25ⴗC

= ⴞ15V

V

S

1.0

CURRENT NOISE (pA/ Hz)

0.1
10 100 10k

1/f CORNER = 200Hz

1k

FREQUENCY (Hz)

TPC 4. Current Noise Density
vs. Frequency

5

T

= 25ⴗC

A

4

AT 10Hz

3

2

VOLTA G E NOISE (nV/ Hz)

1

0 ⴞ5 ⴞ15 ⴞ20

SUPPLY VOLTAGE (V)

AT 1kHz

ⴞ10

TPC 2. Voltage Noise Density
vs. Supply Voltage

40

VS = ⴞ15V

30

20

10

0

–10

VOLTA G E NOISE (nV/ Hz)

–20

–30

–50 –25 0 25 50 75 100 125

–75

TEMPERATURE (ⴗC)

TPC 5. Input Offset Voltage vs.
Temperature

0.1Hz TO 10Hz NOISE

NOISE VOLTAGE (100nV/DIV)

TA = 25ⴗC

= ⴞ15V

V

S

TIME (1sec/DIV)

TPC 3. 0.1 Hz to 10 Hz Input
Voltage Noise

5

TA = 25ⴗC

= ⴞ15V

V

S

4

3

2

1

CHANGE IN OFFSET VOLTAGE (␮A)

0

12345

0

TIME (Minutes)

TPC 6. Warm-Up Offset Voltage
Drift

7

6

5

4

INPUT BIAS CURRENT (nA)

3

2
–75

TPC 7. Input Bias Current vs.
Temperature

REV. C

VS = ⴞ15V

= 0V

V

CM

–50 0 50 100 125

–25 25 75

TEMPERATURE (ⴗC)

5

VS = ⴞ15V

= 0V

V

CM

4

3

2

1

INPUT OFFSET CURRENT (nA)

0
–75

–50 0 50 100 125

–25 25 75

TEMPERATURE (ⴗC)

TPC 8. Input Offset Current vs.
Temperature

–5–

TPC 9. Input Bias Current vs.
Common-Mode Voltage

OP270

TEMPERATURE (ⴗC)

TOTA L SUPPLY CURRENT (mA)

8

0

2

–75 –25 25 75 125

6

4

VS = ⴞ15V

–50 0 50 100

7

1

5

3

130

120

110

100

90

80

70

60

CMR (dB)

50

40

30

20

10

110100 1k 10k 100k 1M

FREQUENCY (Hz)

TA = 25ⴗC
V

TPC 10. CMR vs. Frequency

140

120

100

80

60

PSR (dB)

40

20

–PSR

+PSR

= ⴞ15V

S

TA = 25ⴗC

6

5

4

+125ⴗC

+25ⴗC

–55ⴗC

3

TOTA L SUPPLY CURRENT (mA)

2

0 ⴞ5 ⴞ10 ⴞ15 ⴞ20

SUPPLY VOLTAGE (V)

TPC 11. Total Supply Current
vs. Supply Voltage

140

120

100

80

60

VOLTA GE GAIN (dB)

40

20

TA = 25ⴗC
V

= ⴞ15V

S

TPC 12. Total Supply Current
vs. Temperature

80

60

40

20

CLOSED-LOOP GAIN (dB)

0

TA = 25ⴗC
V

S

= ⴞ15V

0

1 100 10k 1M 100M

10 1k 100k 10M

FREQUENCY (Hz)

TPC 13. PSR vs. Frequency

25

20

15

10

5

GAIN (dB)

0

–5

–10

1

TPC 16. Open-Loop Gain Phase
Shift vs. Frequency

PHASE

GAIN

2345678910

FREQUENCY (Hz)

TA = 25ⴗC

= ⴞ15V

V

S

PHASE

MARGIN = 62ⴗ

80

100

120

140

160

180

5000

4000

3000

2000

PHASE SHIFT (Degrees)

OPEN-LOOP GAIN (V/mV)

1000

TPC 17. Open-Loop Gain vs.
Supply Voltage

0

1 100 10k 1M 100M

10 1k 100k 10M

FREQUENCY (Hz)

TPC 14. Open-Loop Gain vs.
Frequency

0

0

ⴞ5 ⴞ10 ⴞ15 ⴞ20 ⴞ25

SUPPLY VOLTAGE (V)

–6–

–20

1k 10k

100k 10M

FREQUENCY (Hz)

1M

TPC 15. Closed-Loop Gain vs.
Frequency

80

70

60

50

PHASE MARGIN (Degrees)

40

–75

⌽

GBP

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (ⴗC)

TPC 18. Gain-Bandwidth Phase
Margin vs. Temperature

REV. C

8

7

6

5

GAIN BANDWIDTH PRODUCT (MHz)

4

OP270

28

24

20

16

12

8

PEAK-TO-PEAK AMPLITUDE (V)

4

0

1k

10k 100k 1M 10M

FREQUENCY (Hz)

TA = 25ⴗC
VS = ⴞ15V

THD = 1%

TPC 19. Maximum Output
Swing vs. Frequency

100

TA = +25ⴗC

= ⴞ15V

V

S

75

50

AV = 100

25

OUTPUT IMPEDANCE (⍀)

0

1k 100k 10M

10k 1M

FREQUENCY (Hz)

AV = 1

AV = 10

TPC 22. Output Impedance vs.
Frequency

15

TA = 25ⴗC
VS = ⴞ15V

14

13

12

11

10

9

8

MAXIMUM OUTPUT ( V)

7

6

5

1k 10k 100k

POSITIVE
SWING

NEGATIVE
SWING

LOAD RESISTANCE (⍀)

TPC 20. Maximum Output
Voltage vs. Load Resistance

2.8
VS = ⴞ15V

2.7

2.6

2.5

2.4

SLEW RATE (V/␮s)

2.3

2.2

–75 25 125

–25 75

TEMPERATURE (ⴗC)

–SR

+SR

0 100–50 50

TPC 23. Slew Rate vs.
Temperature

50

TA = 25ⴗC

= ⴞ15V

V

S

VIN = 100mV
AV = +1

40

30

20

OVERSHOOT (%)

10

0

200 600 800

0 400 1000

CAPACITIVE LOAD (pF)

TPC 21. Small-Signal Overshoot
vs. Capacitive Load

190

180

170

160

150

140

130

120

110

100

CHANNEL SEPARATION (dB)

90

TA = 25ⴗC
V

= ⴞ15V

80

S

VO = 20V p-p TO 10kHz

70

11k1M

100 100k10

FREQUENCY (Hz)

10k

TPC 24. Channel Separation vs.
Frequency

0.1
TA = 25ⴗC
VS = ⴞ15V
VO = 20V p-p
R

=2k⍀

L

A

V

0.01

DISTORTION (%)

0.001
10 10k

100
FREQUENCY (Hz)

AV = 1

1k

TPC 25. Total Harmonic Distor­tion vs. Frequency

REV. C

= 10

20␮s

TA = 25ⴗC
VS = ⴞ15V
AV = +1
RL = 2k⍀

5V

TPC 26. Large Signal Transcient
Response

–7–

50mV 200nS

TA = 25ⴗC
VS = ⴞ15V
AV = +1
RL = 2k⍀

TPC 27. Small-Signal
Transient Response

OP270

5k⍀

500⍀

50⍀

1/2

OP270

5k⍀

1/2

OP270

CHANNEL SEPARATION = 20 log

20V

V

1

p-p

V

2

Figure 1. Channel Separation Test Circuit

+18V

8

100k⍀

200k⍀

100k⍀

2

1/2

OP270

3

6

1/2

OP270

5

4

1

7

V

1

V2/1000

TOTAL NOISE AND SOURCE RESISTANCE

The total noise of an op amp can be calculated by:

EeiR e

nnnS t

222

=

()+()

+

()

where:

E

= total input referred noise

n

e

= op amp voltage noise

n

i

= op amp current noise

n

e

= source resistance thermal noise

t

R

= source resistance

S

The total noise is referred to the input and at the output would
be amplified by the circuit gain.

Figure 3 shows the relationship between total noise at 1 kHz
and source resistance. For R
by the voltage noise of the OP270. As R

< 1 kW the total noise is dominated

S

rises above 1 kW, total

S

noise increases and is dominated by resistor noise rather than by
the voltage or current noise of the OP270. When R

exceeds

S

20 kW, current noise of the OP270 becomes the major contributor
to total noise.

100

OP200

10

–18V

Figure 2. Burn-In Circuit

APPLICATIONS INFORMATION
VOLTAGE AND CURRENT NOISE

The OP270 is a very low noise dual op amp, exhibiting atypical
voltage noise of only 3.2 nV/

÷÷

÷Hz @ 1 kHz. The exceptionally

÷÷

low noise characteristic of the OP270 is achieved in part by
operating the input transistors at high collector currents since
the voltage noise is inversely proportional to the square root of
the collector current. Current noise, however, is directly propor­tional to the square root of the collector current. As a result, the
outstanding voltage noise performance of the OP270 is gained
at the expense of current noise performance, which is normal for
low noise amplifiers.

To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (e
noise (i

), and resistor noise (et).

n

), current

n

TOTAL NOISE (nV/ Hz)

OP270

RESISTOR
NOISE ONLY

1

100 1k 10k 100k

RS – SOURCE RESISTANCE (⍀)

Figure 3. Total Noise vs. Source Resistance
(Including Resistor Noise) at 1 kHz

Figure 4 also shows the relationship between total noise and
source resistance, but at 10 Hz. Total noise increases more
quickly than shown in Figure 3 because current noise is inversely
proportional to the square root of frequency. In Figure 4, current
noise of the OP270 dominates the total noise when R

> 5 kW.

S

Figures 3 and 4 show that to reduce total noise, source resistance
must be kept to a minimum. In applications with a high source
resistance, the OP200, with lower current noise than the OP270,
will provide lower total noise.

–8–

REV. C

OP270

100

10

OP200

OP270

TOTAL NOISE (nV/ Hz)

RESISTOR
NOISE ONLY

1
100 1k 10k 100k

RS – SOURCE RESISTANCE (⍀)

Figure 4. Total Noise vs. Source Resistance
(Including Resistor Noise) at 10 Hz

1000

OP200

100

OP270

PEAK-TO-PEAK NOISE (nV)

RESISTOR
NOISE ONLY

Figure 5 shows peak-to-peak noise versus source resistance over the

0.1 Hz to 10 Hz range. Once again, at low values of R

, the voltage

S

noise of the OP270 is the major contributor to peak-to-peak
noise, with current noise the major contributor as R

increases.

S

The crossover point between the OP270 and the OP200 for
peak-to-peak noise is at R

=17kW.

S

The OP271 is a higher speed version of the OP270, with a slew
rate of 8 V/ms. Noise of the OP271 is slightly higher than that of
the OP270. Like the OP270, the OP271 is unity-gain stable.

For reference, typical source resistances of some signal sources
are listed in Table I.

Table I.

Source

Device Impedance Comments

Strain gage <500 W Typically used in low

frequency applications.

Magnetic <1500 W Low I

very important to reduce

B

tapehead, self-magnetization problems
microphone when direct coupling is used.

OP270 IB can be neglected.

Magnetic <1500 W Similar need for low I

in

B

phonograph direct coupled applications.
cartridge OP270 will not introduce any

self-magnetization problem.

Linear variable <1500 W Used in rugged servo-feedback
differential applications. Bandwidth of
transformer interest is 400 Hz to 5 kHz.

10

100 1k 10k 100k

RS – SOURCE RESISTANCE (⍀)

Figure 5. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs.
Source Resistance (Includes Resistor Noise)

R3

1.24k⍀

R1
5⍀

R2
5⍀

–
OP270

DUT

+

+

OP27E

–

R4
200⍀

R5

909⍀

C1

2␮F

R6
600⍀

D1, D2
1N4148

R8
10k⍀

Figure 6. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

+

OP27E

–

0.032␮F

R9

306k⍀

C2

R10

65.4k⍀

R11

65.4k⍀

C4

0.22␮F

C3

0.22␮F

+

OP42E

–

R12
10k⍀

R13

5.9k⍀

R14

4.99k⍀

GAIN = 50,000

= ⴞ15V

V

S

C5
1␮F

e

OUT

REV. C

–9–

OP270

eee

OUT nA

2

nB

2

=

()+()

Ê
Ë

Á

ˆ
¯

˜

101

NOISE MEASUREMENTS
Peak-to-Peak Voltage Noise

The circuit of Figure 6 is a test setup for measuring peak-to-peak
voltage noise. To measure the 200 nV peak-to-peak noise specifica­tion of the OP270 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:

1. The device has to be warmed up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 2 mV due to increasing chip temperature after power-up.
In the 10-second measurement interval, these temperature
induced effects can exceed tens of nanovolts.

2. For similar reasons, the device has to be well shielded from
air currents. Shielding also minimizes thermocouple effects.

3. Sudden motion in the vicinity of the device can also “feed
through” to increase the observed noise.

4. The test time to measure noise of 0.1 Hz to 10 Hz should not
exceed 10 seconds. As shown in the noise-tester frequency
response curve of Figure 7, the 0.1 Hz corner is defined by
only one pole. The test time of 10 seconds acts as an additional
pole to eliminate noise contribution from the frequency band
below 0.1 Hz.

100

80

60

GAIN (dB)

40

20

0

0.01 0.1 1.0 10 100

FREQUENCY (Hz)

Figure 7. 0.1 Hz to 10 Hz Peak-to-Peak Voltage
Noise Test Circuit Frequency Response

5. A noise-voltage-density test is recommended when measuring

noise on a large number of units. A 10 Hz noise-voltage-density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined by
the white noise and the location of the 1/f corner frequency.

6. Power should be supplied to the test circuit by well bypassed

low noise supplies, e.g., batteries. They will minimize output
noise introduced via the amplifier supply pins.

Noise Measurement — Noise Voltage Density

The circuit of Figure 8 shows a quick and reliable method of
measuring the noise voltage density of dual op amps. The first
amplifier is in unity-gain, with the final amplifier in a noninverting
gain of 101. As noise voltages of each amplifier are uncorrelated,
they add in rms fashion to yield:

The OP270 is a monolithic device with two identical amplifi­ers. The noise voltage density of each individual amplifier will
match, giving:

2

Ê

ˆ

eee

=

101 2 101 2

OUT n

R1

100⍀

–

1/2

OP270

+

Á
Ë

e

(nV/ Hz) = 101 ( 2

OUT

V

= 15V

S

=

˜

()

¯

R2

10k⍀

–

1/2

OP270

+

TO SPECTRUM ANALYZER

苲
苲

e

e

)

n

n

OUT

Figure 8. Noise Voltage Density Test Circuit

R3

1.24k⍀

R2

R1

100k⍀

5⍀

–
OP270

DUT

+

200⍀

–

OP27E

+

R4

R5

8.06k⍀

e

nOUT

TO SPECTRUM ANALYZER

GAIN = 10,000
VS = ⴞ15V

Figure 9. Current Noise Density Test Circuit

Noise Measurement — Current Noise Density

The test circuit shown in Figure 9 can be used to measure cur­rent noise density. The formula relating the voltage output to
current noise density is:

2

ˆ

Ê

e

nOUT

Á
Ë

i

=

n

-

nV Hz

40 /

˜

G

()

¯

R

S

2

where:

G = gain of 10,000

= 100 kW source resistance

R

S

–10–

REV. C

OP270

CAPACITIVE LOAD DRIVING AND POWER SUPPLY CONSIDERATIONS

The OP270 is unity-gain stable and capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP270.

In the standard feedback amplifier, the op amp’s output resis­tance combines with the load capacitance to form a low-pass
filter that adds phase shift in the feedback network and reduces
stability. A simple circuit to eliminate this effect is shown in
Figure 10. The added components, C1 and R3, decouple the
amplifier from the load capacitance and provide additional
stability. The values of C1 and R3 shown in Figure 10 are for a
load capacitance of up to 1,000 pF when used with the OP270.

V+

+

C3

0.1␮FC210␮F

R2

V–

C1

200pF

C5

0.1␮FC410␮F

R3

50⍀

+

PLACE SUPPLY DECOUPLING
CAPACITOR AT OP270

V

OUT

C1
1000pF

R1

V

IN

–

OP270

+

Figure 10. Driving Large Capacitive Loads

UNITY-GAIN BUFFER APPLICATIONS

When Rf £ 100 W and the input is driven with a fast, large
signal pulse (>1 V), the output waveform will look like the one
in Figure 11.

During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will be
drawn by the signal generator. With R
capable of handling the current requirements (I

≥ 500 W, the output is

f

£ 20 mA at 10 V);

L

the amplifier will stay in its active mode and a smooth transition
will occur.

When R

> 3 kW, a pole created by Rf and the amplifier’s input

f

capacitance (3 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel
with R

helps eliminate this problem.

f

APPLICATIONS
Low Phase Error Amplifier

The simple amplifier depicted in Figure 12 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared to conventional amplifier designs.
At a given gain, the frequency range for a specified phase accuracy is
over a decade greater than for a standard single op amp amplifier.

The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the feed­back loop of A1. Both op amps must be extremely well matched
in frequency response. At low frequencies, the A1 feedback
loop forces V
Vo/(K1 + 1) = V
of V

O/VIN

/(K1 + 1) = VIN. The A2 feedback loop forces

2

/(K1 + 1), yielding an overall transfer function

2

= K1 + 1. The dc gain is determined by the resistor
divider at the output, VO, and is not directly affected by the resis­tor divider around A2. Note that like a conventional single op amp
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10.

R2
K1

–

1/2
OP270E
A2

+

–

1/2
OP270E
A1

V

IN

ASSUME A1 AND A1 ARE MATCHED.

+

␻

T

(s) =

A

O

s

R2

R2

R2 = R1

V

2

R1
K1

VO = (K1 + 1) V

V

O

IN

Figure 12. Low Phase Error Amplifier

Figure 13 compares the phase error performance of the low
phase error amplifier with a conventional single op amp ampli­fier and a cascaded two-stage amplifier. The low phase error
amplifier shows a much lower phase error, particularly for fre­quencies where w/bw
occurs at 0.002 w/bw

0.11 w/bw

for the low phase error amplifier.

T

< 0.1. For example, phase error of –0.1∞

T

for the single op amp amplifier, but at

T

REV. C

Figure 11. Pulsed Operation

–11–

OP270

0

–1

–2

–3

–4

–5

PHASE SHIFT (Degrees)

–6

–7

0.001 0.01 0.1 1.0

SINGLE OP AMP.

CONVENTIONAL DESIGN

CASCADED

(TWO STAGES)

LOW PHASE ERROR

0.005 0.05 0.5
FREQUENCY RATIO (1/␤␻)(␻/␻T)

AMPLIFIER

Figure 13. Phase Error Comparison

C1

0.47␮F

V

IN

47k⍀

R3

680⍀

R5

680⍀

R7

680⍀

R9

680⍀

R11

680⍀

R1

+

1/2

OP270E

–

C2

6.8␮F
+

TANTALUM

C3

1␮F

+

TANTALUM

C4

0.22␮F

C5

0.047␮F

C6

0.022␮F

3.3k⍀

L1

1H

L2

600mH

L3

180mH

L4

60mH

L5

10mH

R2

+

1/2

R4

1k⍀

R6

1k⍀

R8

1k⍀

R10
1k⍀

R12
1k⍀

60Hz

200Hz

800Hz

3kHz

10kHz

OP270E

–

3.3k⍀

R13

Figure 14. 5-Band Low Noise Graphic Equalizer

R14

100⍀

FIVE-BAND LOW NOISE STEREO GRAPHIC EQUALIZER

The graphic equalizer circuit shown in Figure 14 provides 15 dB of
boost or cut over a 5-band range. Signal-to-noise ratio over a 20 kHz
bandwidth is better than 100 dB and referred to a 3 V rms input.
Larger inductors can be replaced by active inductors, but this
reduces the signal-to-noise ratio.

DIGITAL PANNING CONTROL

Figure 15 uses a DAC8221, a dual 12-bit CMOS DAC, to pan
a signal between two channels. One channel is formed by the
current output of DAC A driving one-half of an OP270 in a
current-to-voltage converter configuration. The other channel is
formed by the complementary output current of DAC A, which
normally flows to ground through the AGND pin. This comple­mentary current is converted to a voltage by the other half of the
OP-270, which also holds AGND at virtual ground.

Gain error due to mismatching between the internal DAC ladder
resistors and the current-to-voltage feedback resistors is elimi­nated by using feedback resistors internal to the DAC8221. Only
DAC A passes a signal; DAC B provides the second feedback
resistor. With V

V

OUT

ing DAC B. Distortion of the digital panning control is less than

using R

B, is accurate and not influenced by digital data reach-

FB

B unconnected, the current-to-voltage converter,

REF

0.002% over the 20 Hz to 20 kHz audio range. Figure 16 shows
the complementary outputs for a 1 kHz input signal and a digital
ramp applied to the DAC data input.

DUAL PROGRAMMABLE GAIN AMPLIFIER

The dual OP270 and the DAC8221, a dual 12-bit CMOS
DAC, can be combined to form a space-saving dual program­mable amplifier. The digital code present at the DAC, which is
easily set by a microprocessor, determines the ratio between the
internal feedback resistor and the resistance the DAC ladder
presents to the op amp feedback loop. Gain of each amplifier is

V

OUT

Vn

IN

= –

4096

where n equals the decimal equivalent of the 12-bit digital code
present at the DAC. If the digital code present at the DAC
consists of all zeros, the feedback loop will open, causing the op
amp output to saturate. A 20 MW resistor placed in parallel with
the DAC feedback loop eliminates this problem with only a very
small reduction in gain accuracy.

–12–

REV. C

OP270

V

IN

DAC DATA BUS

PINS 6 (MSB) - 17 (LSB)

NC

WRITE

CONTROL

+5V

2

–

1/2
OP270GP

3

+

6

–

1/2
OP270GP

5

+

+15V

–15V

DAC8221HP

V

4

REF

V

22

REF

18

DAC A/DAC B

19

CS

20

WR

21

V

DD

RFBA

3

A

DAC A

B

DAC B

DGND

I

A

2

OUT

AGND 1

RFBB

23

I

B

24

OUT

5

Figure 15. Digital Panning Control

8

4

0.01␮F

+

10␮F

–

1

7

OUT

–

0.1␮F 10␮F
+

OUT

WRITE

CONTROL

20M⍀

2

3

6

5

+15V

–

1/2
OP270EZ

+

–15V

–

1/2
OP270GP

+

DAC8221HP

3

VINA

23

VINB

DAC DATA BUS

PINS 6 (MSB) - 17 (LSB)

18

19

20

RFBA

RFBB

DGND

+5V

V

DAC A

DAC B

5

21

DD

V

A

4

REF

A

I

2

OUT

AGND

1

I

B

24

OUT

20M⍀

V

B

22

REF

Figure 17. Dual Programmable Gain Amplifier

0.01␮F

+

10␮F

–

8

1

4

0.1␮F 10␮F

7

V

A

OUT

–
+

V

B

OUT

A OUT

A OUT

5V 1ms5V

Figure 16. Digital Panning Control Output

REV. C

–13–

OP270

OUTLINE DIMENSIONS

8-Lead Ceramic Dual In-Line Package [CERDIP]

Z-Suffix

(Q-8)

Dimensions shown in inches and (millimeters)

0.005 (0.13)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.055 (1.40)

MIN

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

85

1

4

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15

0

0.015 (0.38)

0.008 (0.20)

8-Lead Plastic Dual In-Line Package [PDIP]

P-Suffix

(N-8)

Dimensions shown in inches and (millimeters)

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54)

0.180

(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

BSC

5

4

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.015
(0.38)
MIN

SEATING
PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

16-Lead Standard Small Outline Package [SOIC]

Wide Body

S-Suffix

(RW-16)

Dimensions shown in millimeters and (inches)

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500)
BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.33 (0.0130)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.32 (0.0126)

0.23 (0.0091)

8ⴗ
0ⴗ

0.75 (0.0295)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

–14–

REV. C

OP270

Revision History

Location Page

4/03—Data Sheet changed from REV. B to REV. C.

Deletion of OP270A model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Deletion of WAFER LIMITS and DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to equations in Noise Measurements section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Change to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

11/02—Data Sheet changed from REV. A to REV. B.

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9/02—Data Sheet changed from REV. 0 to REV. A.

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. C

–15–

C00325–0–4/03(C)

–16–