Page 1
Ultraprecision
V
www.BDTIC.com/ADI
FEATURES
Ultralow offset voltage
= 25°C, 25 μV maximum
T
A
Outstanding offset voltage drift 0.1 μV/°C maximum
Excellent open-loop gain and gain linearity
12 V/μV typical
CMRR: 130 dB minimum
PSRR: 115 dB minimum
Low supply current 2.0 mA maximum
Fits industry-standard precision op amp sockets
GENERAL DESCRIPTION
The OP177 features one of the highest precision performance of
any op amp currently available. Offset voltage of the OP177 is
only 25 μV maximum at room temperature. The ultralow V
the OP177 combines with its exceptional offset voltage drift
(TCV
) of 0.1 μV/°C maximum to eliminate the need for
OS
external V
adjustment and increases system accuracy over
OS
temperature.
The OP177 open-loop gain of 12 V/μV is maintained over the
ull ±10 V output range. CMRR of 130 dB minimum, PSRR of
f
120 dB minimum, and maximum supply current of 2 mA are
just a few examples of the excellent performance of this
of
OS
Operational Amplifier
OP177
PIN CONFIGURATION
1
TRIM VOS TRIM
OS
OP177
2
–IN
3
+IN
TOP VIEW
4
(Not to Scale)
NC = NO CONNECT
Figure 1. 8-Lead PDIP (P-Suffix),
8-Lead
SOIC (S-Suffix)
operational amplifier. The combination of outstanding
s
pecifications of the OP177 ensures accurate performance in
high closed-loop gain applications.
This low noise, bipolar input op amp is also a cost effective
ternative to chopper-stabilized amplifiers. The OP177
al
provides chopper-type performance without the usual problems
of high noise, low frequency chopper spikes, large physical size,
limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 is offered in the −40°C to +85°C extended industrial
t
emperature ranges. This product is available in 8-lead PDIP, as
well as the space saving 8-lead SOIC.
8
7
V+
6
OUT
5
NCV–
00289-001
FUNCTIONAL BLOCK DIAGRAM
V+
2B
Q
5
R
NONINVERTI NG
INPUT
INVERTING
INPUT
3
Q
21
Q
R
22
4
V–
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
(OPTIO NAL NULL)
R
1A
Q
7
Q
3
Q
1
Q
23
Q
24
AND R2BARE ELECTRONI CALLY ADJUST ED ON CHIP AT F ACTORY.
*R
2A
Q
8
Q
6
Q
Q
Figure 2. Simplified Schematic
R2B*R2A*
R
1B
4
2
C
1
Q
9
Q11Q
C
3
Q
27
R
5
Q
26
Q
25
Q
10
12
C
2
Q
Q
13
Q
17
14
R
7
Q
19
R
9
OUTPUT
R
Q
16
Q
15
R
6
10
Q
20
Q
18
R
8
00289-002
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Page 2
OP177
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Linearity................................................................................9
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Test Cir c ui t s ................................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Application Information.................................................................. 9
REVISION HISTORY
5/06—Rev. D to Rev. E
Changes to Figure 1.......................................................................... 1
Change to Specifications Table 1 .................................................... 3
Changes to Specifications Table 2................................................... 4
Changes to Table 3............................................................................ 5
Changes to Figure 23 and Figure 24............................................... 9
Changes to Figure 32...................................................................... 12
Updated the Ordering Guide........................................................ 14
4/06—Rev. C to Rev. D
hange to Pin Configuration Caption........................................... 1
C
Changes to Features.......................................................................... 1
Change to Table 2 ............................................................................. 4
Change to Figure 2 ........................................................................... 4
Changes to Figure 10 and Figure 11............................................... 6
Changes to Figure 12 through Figure 17....................................... 7
Changes to Figure 18 through Figure 22....................................... 8
Thermocouple Amplifier with Cold-Junction
Compensation................................................................................9
Precision High Gain Differential Amplifier ........................... 10
Isolating Large Capacitive Loads.............................................. 10
Bilateral Current Source............................................................ 10
Precision Absolute Value Amplifier......................................... 10
Precision Positive Peak Detector.............................................. 12
Precision Threshold Detector/Amplifier ................................ 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
Change to Figure 27....................................................................... 10
Changes to Figure 30 and Figure 31............................................. 11
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide.......................................................... 13
1/05—Re
Edits to Features.................................................................................1
dits to General Description ...........................................................1
E
Edits to Pin Connections..................................................................1
Edits to Electrical Characteristics .............................................. 2, 3
Global deletion of references to OP177E............................ 3, 4, 10
Edits to Absolute Maximum Ratings..............................................5
Edits to Package Type .......................................................................5
Edits to Ordering Guide...................................................................5
Edit to Outline Dimensions.......................................................... 11
11/95—Rev. 0: Initial Version
v. B to Rev. C
Rev. E | Page 2 of 16
Page 3
OP177
www.BDTIC.com/ADI
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP177F OP177G
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE V
LONG-TERM INPUT OFFSETT
1
OS
10 25 20 60 μV
Voltage Stability ΔVOS/time 0.3 0.4 μV/mo
INPUT OFFSET CURRENT I
INPUT BIAS CURRENT I
OS
B
INPUT NOISE VOLTAGE en fO = 1 Hz to 100 Hz
INPUT NOISE CURRENT i
n
0.3 1.5 0.3 2.8 nA
−0.2 +1.2 +2 −0.2 +1.2 +2.8 nA
2
118 150 118 150 nV rms
fO = 1 Hz to 100 Hz
2
3 8 3 8 pA rms
INPUT RESISTANCE
Differential Mode
INPUT RESISTANCE COMMON MODE R
3
R
IN
INCM
26 45 18.5 45 MΩ
200 200 GΩ
INPUT VOLTAGE RANGE4 IVR ±13 ±14 ±13 ±14 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 130 140 115 140 dB
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 115 125 110 120 dB
LARGE SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ, VO = ±10 V5 5000 12,000 2000 6000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V
R
R
≥ 2 kΩ ±12.5 ±13.0 ±12.5 ±13.0 V
L
≥ 1 kΩ ±12.0 ±12.5 ±12.0 ±12.5 V
L
SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs
CLOSED-LOOP BANDWIDTH2 BW A
= 1 0.4 0.6 0.4 0.6 MHz
VCL
OPEN-LOOP OUTPUT RESISTANCE RO 60 60 Ω
POWER CONSUMPTION P
D
V
SUPPLY CURRENT I
SY
VS = ±15 V, no load 50 60 50 60 mW
= ±3 V, no load 3.5 4.5 3.5 4.5 mW
S
VS = ±15 V, no load 1.6 2 1.6 2 mA
OFFSET ADJUSTMENT RANGE RP = 20 kΩ ±3 ±3 mV
1
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in V
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
during the first 30 operating days are typically less than 2.0 μV.
OS
Rev. E | Page 3 of 16
Page 4
OP177
Ω
www.BDTIC.com/ADI
@ VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
OP177F OP177G
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT
Input Offset Voltage VOS 15 40 20 100 μV
Average Input Offset Voltage Drift
1
TCVOS 0.1 0.3 0.7 1.2 μV/°C
Input Offset Current IOS 0.5 2.2 0.5 4.5 nA
Average Input Offset Current Drift
Input Bias Current I
Average Input Bias Current Drift
2
2
TCIOS 1.5 40 1.5 85 pA/°C
B
−0.2 +2.4 +4 +2.4 ±6 nA
TCIB 8 40 15 60 pA/°C
Input Voltage Range3 IVR ±13 ±13.5 ±13 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 120 140 110 140 dB
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 110 120 106 115 dB
LARGE-SIGNAL VOLTAGE GAIN4 AVO RL ≥ 2 kΩ, VO = ±10 V 2000 6000 1000 4000 V/mV
OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±12 ±13 ±12 ±13 V
POWER CONSUMPTION PD VS = ±15 V, no load 60 75 60 75 mW
SUPPLY CURRENT ISY VS = ±15 V, no load 20 2.5 2 2.5 mA
1
TCVOS is sample tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V.
TEST CIRCUITS
50Ω
–
OP177
+
Figure 3. Typical Offset Vo
–
INPUT
+
–
OP177
+
Figure 4. Optional Of
20kΩ
–
OP177
+
200k
V
O
V
=
OS
4000
ltage Test Circuit
20kΩ
V
TRIM RANGE IS
OS
TYPICALLY ±3.0mV
V–
fset Nulling Circuit
+20V
PINOUT S SHOWN FO R
P AND Z PACKAGES
V
O
00289-003
V+
OUTPUT
00289-004
–20V
Figure 5. Burn-In Circuit
Rev. E | Page 4 of 16
0289-005
Page 5
OP177
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Ratings
Supply Voltage ±22 V
Internal Power Dissipation
Differential Input Voltage ±30 V
Input Voltage ±22 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 60 sec) 300°C
DICE Junction Temperature (TJ) −65°C to +150°C
1
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
1
500 mW
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case mounting conditions, that is, θJA
is specified for device in socket for PDIP; θ
device soldered to printed circuit board for SOIC package.
Table 4. Thermal Resistance
Package Type θ
8-Lead PDIP (P-Suffix) 103 43 °C/W
8-Lead SOIC (S-Suffix) 158 43 °C/W
is specified for
JA
JA
θ
Unit
JC
Rev. E | Page 5 of 16
Page 6
OP177
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
= 0V)
OUT
TA = 25°C
V
= ±15V
S
R
= 10kΩ
L
20
VS = ±15V
25
30
DEVICE IMMERSE D IN
70° OIL BATH (20 UNIT S)
0
INPUT VOLTAGE (µV)
–1
(NULLED TO 0mV @ V
–2
–10 –5 0 5 10
OUTPUT VOLTAGE (V)
Figure 6. Gain Linearity (Input Voltage vs. Output Voltage)
100
TA = 25°C
10
POWER CONSUM PTION (mW )
1
010203040
TOTAL SUPPLY VOLTAGE, V+ TO V– (V)
Figure 7. Power Consumption vs. Power Supply
35
40
ABSOLUTE CHANGE IN
INPUT OFFSET VOLTAGE (µV)
45
00289-006
50
0 10203040506070
TIME (Seconds)
00289-009
Figure 9. Offset Voltage Change Due to Thermal Shock
25
VS = ±15V
20
15
10
OPEN-LOOP GAIN (V/µV)
5
00289-007
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
00289-010
Figure 10. Open-Loop Gain vs. Temperature
5
4
3
2
1
(µV)
0
OS
V
–1
–2
–3
–4
–5
0 20 40 60 80 100 120 140 160 180
Figure 8. Warm-Up V
LOT A
LOT B
LOT C
LOT D
TIME (S econds)
Drift (Normalized) Z Package
OS
00289-008
Rev. E | Page 6 of 16
16
TA = 25°C
R
= 2kΩ
L
12
8
OPEN-LOOP GAIN (V/µV)
4
0
0±5±10±15
Figure 11. Open-Loop Gain
POWER SUPPLY VOLTAGE (V)
vs. Power Supply Voltage
00289-011
±20
Page 7
OP177
www.BDTIC.com/ADI
4
VS = ±15V
3
160
140
120
100
TA = 25°C
= ±15V
V
S
2
1
INPUT BIAS CURRENT (nA)
0
–50 0 50 100
TEMPERATURE (°C)
Figure 12. Input Bias Current vs. Temperature
2.0
VS = ±15V
1.5
1.0
0.5
INPUT OFFSET CURRENT ( nA)
0
–50 0 50 100
TEMPERATURE (°C)
Figure 13. Input Offset Current vs. Temperature
80
60
OPEN-LOOP GAIN (dB)
40
20
00289-012
00289-013
0
0.01 0.1 1 10 100 1k 10k
FREQUENCY ( Hz)
Figure 15. Open-Loop Frequency Resp
150
140
130
120
110
CMRR (dB)
100
90
80
1 10 100 1k 10k 100k
FREQUENCY ( Hz)
100k 1M
onse
TA = 25°C
00289-015
00289-016
Figure 16. CMRR vs. Frequency
100
80
60
40
20
CLOSED-LOOP GAIN (dB)
0
–20
10 100 1k 10k 100k 1M 10M
FREQUENCY ( Hz)
TA = 25°C
= ±15V
V
S
Figure 14. Closed-Loop Response for Various Gain Configurations
00289-014
Rev. E | Page 7 of 16
130
120
110
100
90
PSRR (dB)
80
70
60
0.1 1 10 100 1k 10k
FREQUENCY (Hz)
TA = 25°C
Figure 17. PSRR vs. Frequency
00289-017
Page 8
OP177
√
www.BDTIC.com/ADI
1000
Hz)
100
RS1 = RS2 = 200kΩ
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
20
15
TA = 25°C
V
= +15V
S
V
= ±10mV
IN
POSITIVE SWING
NEGATIVE SWING
EXCLUDED
10
INPUT NOISE VOLTAGE (nV
TA = 25°C
V
= ±15V
S
1
1 10 100 1k
RS = 0
FREQUENCY (Hz)
Figure 18. Total Input Noise Voltage vs. Frequency
10
TA = 25°C
V
= ±15V
S
1
RMS NOISE (µV)
0.1
100 1k 10k 100k
BANDWIDTH (Hz)
Figure 19. Input Wideband Noise vs. Bandwidth
(0
.1 Hz to Frequency Indicated)
32
28
TA = 25°C
V
= ±15V
S
10
MAXIMUM OUTPUT (V)
5
00289-018
0
100 1k 10k
LOAD RESISTANCE TO G ROUND (Ω)
00289-021
Figure 21. Maximum Output Voltage vs. Load Resistance
40
35
+I
30
25
20
OUTPUT SHORT-CIRCUIT CURRENT (mA)
00289-019
15
0123
TIME FROM OUTPUT BEING SHORTED (Minutes)
SC
–I
SC
TA = 25°C
= ±15V
V
S
00289-022
4
Figure 22. Output Short-Circuit Current vs. Time
24
20
16
12
8
PEAK-TO-PEAK AMPLITUDE ( V)
4
0
1k
10k 100k 1M
FREQUENCY (Hz)
00289-020
Figure 20. Maximum Output Swing vs. Frequency
Rev. E | Page 8 of 16
Page 9
OP177
V
A
V
www.BDTIC.com/ADI
APPLICATION INFORMATION
GAIN LINEARITY
The actual open-loop gain of most monolithic op amps varies at
different output voltages. This nonlinearity causes errors in high
closed-loop gain circuits.
It is important to know that the manufacturer’s A
tion is only a part of the solution because all automated testers
use endpoint testing and, therefore, show only the average gain.
For example,
espectable open-loop gain of 650 V/mV. However, the gain is
r
Figure 23 shows a typical precision op amp with a
not constant through the output voltage range, causing nonlinear errors. An ideal op amp shows a horizontal scope trace.
Figure 24 shows the OP177 output gain linearity trace with its
t
ruly impressive average A
of 12,000 V/mV. The output trace
VO
is virtually horizontal at all points, assuring extremely high gain
accuracy. Analog Devices also performs additional testing to
ensure consistent high open-loop gain at various output
voltages.
Figure 25 is a simple open-loop gain test circuit.
–10V 0V +10V
VO
V
X
specifica-
THERMOCOUPLE AMPLIFIER WITH COLDJUNCTION COMPENSATION
An example of a precision circuit is a thermocouple amplifier
that must accurately amplify very low level signals without
introducing linearity and offset errors to the circuit. In this
circuit, an S-type thermocouple with a Seebeck coefficient of
10.3 μV/°C produces 10.3 mV of output voltage at a temperature
of 1000°C. The amplifier gain is set at 973.16, thus, it produces
an output voltage of 10.024 V. Extended temperature ranges
beyond 1500°C are accomplished by reducing the amplifier
gain. The circuit uses a low cost diode to sense the temperature
at the terminating junctions and, in turn, compensates for any
ambient temperature change. The OP177, with its high openloop gain plus low offset voltage and drift, combines to yield a
precise temperature sensing circuit. Circuit values for other
thermocouple types are listed in
Table 5.
Thermocouple
Type
K 39.2 μV/°C 110 Ω 5.76 kΩ 102 kΩ 269 kΩ
J 50.2 μV/°C 100 Ω 4.02 kΩ 80.6 kΩ 200 kΩ
S 10.3 μV/°C 100 Ω 20.5 kΩ 392 kΩ 1.07 MΩ
Seebeck
Coefficient R1 R2 R7 R9
Tabl e 5.
≥ 12000V/mV
VO
R
= 2kΩ
L
VIN = ±10V
A
≥ 650V/mV
VO
= 2kΩ
R
L
Figure 23. Typical Precision Op Amp
Y
–10V
0V
Figure 24. Output Gain Linearity Trace
Y
10kΩ10kΩ
1MΩ
–
OP177
10Ω
+
+10V
R
47kΩ
1%
1%
100Ω
1%
10.000V
+15V
–
OP177
+
–15V
R
9
1.07MΩ
0.05%
0.1µF
10µF
10µF
0.1µF
ANALOG
GROUND
V
OUT
00289-026
R
R
8
100Ω
(ZERO
MENT)
50Ω
1%
R
5
R
4
ANALOG
GROUND
7
392kΩ
1%
10µF
R
3
10µF
+
R
2
1.0kΩ
0.05%
ADJUST-
R
1
+15V
00289-023
TYPES
V
X
00289-024
2
2.2µF
+
ISOTHERMAL
JUNCTIONS
–
+
ISOTHERMAL
BLOCK
COLD-JUNCTION
COMPENSAT ION
REF01
COLD-
6
4
20.5kΩ
COPPER
COPPER
Figure 26. Thermocouple Amplifier with Cold Junction Compensation
V
X
L
00289-025
Figure 25. Open-Loop Gain Li
nearity Test Circuit
Rev. E | Page 9 of 16
Page 10
OP177
T
+
www.BDTIC.com/ADI
PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER
The high gain, gain linearity, CMRR, and low TCVOS of the
OP177 make it possible to obtain performance not previously
available in single stage, very high gain amplifier applications.
See Figure 27.
For best CMR,
R1
must equal
R2
In this example, with a 10 mV differential signal, the maximum
rors are listed in Tab le 6 .
er
R
1
1kΩ
R
3
1kΩ
R
4
1MΩ
Figure 27. Precision High Gain Differential Amplifier
Table 6. High Gain Differential Amp Performance
Type Amount
Common-Mode Voltage 0.1%/V
Gain Linearity, Worst Case 0.02%
TCVOS 0.0003%/°C
TCIOS 0.008%/°C
2
–
OP177
3
+
+15V
–15V
R3
R4
4
R
2
1MΩ
0.1µF
7
6
0.1µF
00289-027
ISOLATING LARGE CAPACITIVE LOADS
The circuit shown in Figure 28 reduces maximum slew rate but
allows driving capacitive loads of any size without instability.
Because the 100 Ω resistor is inside the feedback loop, its effect
on output impedance is reduced to insignificance by the high
open loop gain of the OP177.
R
F
10pF
+15V
0.1µF
R
S
2
7
INPU
–
OP177
3
+
Figure 28. Isolating Capacitive Loads
–15V
6
4
0.1µF
100Ω
C
LOAD
OUTPUT
00289-028
BILATERAL CURRENT SOURCE
The current sources shown in Figure 29 supply both positive
and negative currents into a grounded load.
Note that
4
R
⎞
⎛
+
1
5
=
Z
O
and that for Z
RR
2
R
R
45
+
R
O
must
⎟
⎜
R
⎝
RR
2
2
⎠
3
45
R
−
1
R
to be infinite
3
R
=
1
R
Rev. E | Page 10 of 16
PRECISION ABSOLUTE VALUE AMPLIFIER
The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps (for details,
see Figure 30).
Page 11
OP177
Ω
Ω
V
Ω
www.BDTIC.com/ADI
BASIC CURRENT SOURCE 100mACURRENT SOURCE
R
3
1kΩ
R
1
100kΩ
V
IN
100kΩ
2
2
OP177
3
+
R
–
R
990Ω
6
R
5
4
10Ω
I
OUT
≤ 15mA
R
V
1
IN
R
2
Figure 29. Bilateral Current Source
2
–
OP177
3
+
R
3
+15V
50Ω
6
R
4
2N2222
2N2907
R
5
–15V
= V
IN
R
R1 × R
I
OUT
GIVEN R3 = R4 + R5, R1 = R
3
I
OUT
5
≤ 100mA
00289-029
2
+15V
7
–
OP177
+
4
–15V
1k
0.1µF
0.1µF
6
V
OUT
0 < V
OUT
< 10V
00289-030
1k
+15V
0.1µF
7
2
–
OP177
3
IN
+
–15V
4
0.1µF
C
D
1
30pF
6
1
1N4148
2N4393
R
2kΩ
2
3
3
Figure 30. Precision Absolute Value Amplifier
1k
+15V
0.1µF
7
2
–
OP177
1kΩ
V
IN
3
+
4
0.1µF
–15V
6
RESET
1N4148
1kΩ
NC
2N930
C
H
1kΩ
2
3
+15V
7
–
AD820
+
4
–15V
0.1µF
0.1µF
6
V
OUT
Figure 31. Precision Positive Peak Detector
Rev. E | Page 11 of 16
00289-031
Page 12
OP177
www.BDTIC.com/ADI
PRECISION POSITIVE PEAK DETECTOR
In Figure 31, CH must be polystyrene, Teflon®, or polyethylene
to minimize dielectric absorption and leakage. The droop rate is
determined by the size of C
PRECISION THRESHOLD DETECTOR/AMPLIFIER
In Figure 32, when VIN < VTH, amplifier output swings negative,
reverse biasing diode D
V
, the loop closes.
TH
and the bias current of the AD820.
H
. V
= VTH if RL = ∞. When VIN ≥
1
OUT
C
C
R
F
100kΩ
+15V
R
S
1kΩ
R
2kΩ
2
1
3
V
TH
V
IN
7
–
OP177
+
4
0.1µF
0.1µF
D
1
1N4148
6
V
OUT
⎛
R
F
()
is selected to smooth the response of the loop.
C
C
⎜
VVVV 1
THINTHOUT
⎜
⎝
+−+=
R
S
⎞
⎟
⎟
⎠
Figure 32. Precision Threshold Detector/Amplifier
–15V
00289-032
Rev. E | Page 12 of 16
Page 13
OP177
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
PIN 1
0.100 (2.54)
0.210
(5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 8-Lead Plastic Dual In-Line Package (PDIP)
4.00 (0.1574)
3.80 (0.1497)
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
4
BSC
0.005 (0.13)
MIN
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.015
(0.38)
MIN
SEATING
PLANE
P
-Suffix
0.060 (1.52)
0.015 (0.38)
GAUGE
PLANE
MAX
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
(N-8)
Dimensions show in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
85
6.20 (0.2440)
5.80 (0.2284)
41
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Figure 34. 8-Lead Standard Small Outline Package (SOIC_N)
S-Suffix
(R-8)
Dimensions shown in millimeters and( inches)
× 45°
Rev. E | Page 13 of 16
Page 14
OP177
www.BDTIC.com/ADI
ORDERING GUIDE
Model Temperature Range Package Description Package Option
OP177FP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177FPZ
OP177GP −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP177GPZ
OP177FS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177FSZ
OP177FSZ-REEL
OP177FSZ-REEL7
OP177GS −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP177GSZ
OP177GSZ-REEL
OP177GSZ-REEL7
1
Z = Pb-free part.
1
1
1
1
1
1
1
1
−40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
−40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
−40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
Rev. E | Page 14 of 16
Page 15
OP177
www.BDTIC.com/ADI
NOTES
Rev. E | Page 15 of 16
Page 16
OP177
www.BDTIC.com/ADI
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00289-0-5/06 (E)
Rev. E | Page 16 of 16
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