Datasheet OP177 Datasheet (Analog Devices)

Ultraprecision

NC = NO CONNECT

a

FEATURES
Ultralow Offset Voltage:

TA = +258C: 10 mV max
–558C ≤ T

Outstanding Offset Voltage Drift: 0.1 mV/8C max
Excellent Open-Loop Gain and Gain Linearity:

12 V/mV typ
CMRR: 130 dB min
PSRR: 120 dB min
Low Supply Current: 2.0 mA max
Fits Industry Standard Precision Op Amp Sockets

(OP07/OP77)

GENERAL DESCRIPTION

The OP177 features the highest precision performance of any
op amp currently available. Offset voltage of the OP177 is only
10 µV max at room temperature and 20 µV max over the full
military temperature range of –55°C to +125°C. The ultralow
V

of the OP177, combines with its exceptional offset voltage

OS

drift (TCV
external V
temperature.

The OP177’s open-loop gain of 12 V/µV is maintained over the
full ±10 V output range. CMRR of 130 dB min, PSRR of
120 dB min, and maximum supply current of 2 mA are just a
few examples of the excellent performance of this operational
amplifier. The OP177’s combination of outstanding specifications
insure accurate performance in high closed-loop gain applications.

≤ +1258C: 20 mV max

A

) of 0.1 µV/°C max, to eliminate the need for

OS

adjustment and increases system accuracy over

OS

Operational Amplifier

OP177

PIN CONNECTIONS

Epoxy Mini-DIP

(P Suffix)

8-Pin Hermetic DIP

(Z-Suffix)

8-Pin SO

(S-Suffix)

NC = NO CONNECT

This low noise bipolar input op amp is also a cost effective
alternative to chopper-stabilized amplifiers. The OP177 provides
chopper-type performance without the usual problems of high
noise, low frequency chopper spikes, large physical size, limited
common-mode input voltage range, and bulky external storage
capacitors.

The OP177 is offered in both the –55°C to +125°C military,
and the –40°C to +85°C extended industrial temperature
ranges. This product is available in 8-pin ceramic and epoxy
DIPs, as well as the space saving 8-pin Small-Outline (SO) and
the Leadless Chip Carrier (LCC) packages.

OP177BRC/883

LCC (RC Suffix)

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Figure 1. Simplified Schematic

© Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

OP177–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 615 V, TA = +258C, unless otherwise noted)

OP177A OP177B

Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Input Offset Voltage V
Long-Term Input Offset Voltage Stability ∆V
Input Offset Current I
Input Bias Current I
Input Noise Voltage e
Input Noise Current i

n

Input Resistance Differential-Mode R
Input Resistance Common-Mode R

OS

/Time (Note 1) 0.2 0.2 µV/Mo

OS
OS
B

n

IN
INCM

fo = 1 Hz to 100 Hz
fo = 1 Hz to 100 Hz
(Note 3) 26 45 26 45 MΩ

–0.2 1.5 –0.2 2.0 nA

2
2

410 1025µV

0.3 1.0 0.3 1.5 nA

118 150 118 150 nV rms
38 38pA

rms

200 200 GΩ

Input Voltage Range IVR (Note 4) ±13 ± 14 ±13 ±14 V
Common-Mode Rejection Ratio CMRR V
Power Supply Rejection Ratio PSRR V
Large Signal Voltage Gain A
Output Voltage Swing V

VO
O

Slew Rate SR R
Closed-Loop Bandwidth BW A
Open-Loop Output Resistance R
Power Consumption P

Supply Current I

O
D

SY

Offset Adjustment Range Rp = 20 kΩ

NOTES

1

Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 µV.

2

Sample tested.

3

Guaranteed by design.

4

Guaranteed by CMRR test condition.

5

To insure high open-loop gain throughout the ±10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

Specifications subject to change without notice.

= ±13 V 130 140 130 140 dB

CM

= ±3 V to ±18 V 120 125 115 125 dB

S

RL ≥ 2 kΩ, VO = ±10 V55000 12000 5000 12000 V/mV
RL ≥ 10 kΩ±13.5 ±14.0 ±13.5 ±14.0 V

≥ 2 kΩ±12.5 ±13.0 ±12.5 ±13.0 V

R

L

≥ 1 kΩ±12.0 ±12.5 ±12.0 ±12.5 V

R

L
L
VCL

≥ 2 kΩ

= +1

2

2

0.1 0.3 0.1 0.3 V/µs

0.4 0.6 0.4 0.6 MHz

60 60 Ω

VS = ±15 V, No Load 50 60 50 60 mW

= ±3 V, No Load 3.5 4.5 3.5 4.5 mW

V

S

VS = ±15 V, No Load 1.6 2.0 1.6 2.0 mA

±3 ±3mV

ELECTRICAL CHARACTERISTICS

(@ VS = 615 V, –55°C ≤ TA ≤ +1258C, unless otherwise noted)

OP177A OP177B

Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Input Offset Voltage V

OS

Average Input Offset Voltage Drift TCV
Input Offset Current I

OS

Average Input Offset Current Drift TCI
Input Bias Current I

B

Average Input Bias Current Drift TCI

OS

B

OS

(Note 1) 0.03 0.1 0.1 0.3 µV/°C
(Note 2) 1.5 25 1.5 25 pA/°C

–0.2 2.4 4 –0.2 2.4 4 nA

(Note 2) 8 25 8 25 pA/°C

10 20 25 55 µV

0.5 1.5 0.5 2.0 nA

Input Voltage Range IVR (Note 3) ±13 ±13.5 ±13 ±13.5 V
Common-Mode Rejection Ratio CMRR V
Power Supply Rejection Ratio PSRR V
Large-Signal Voltage Gain A
Output Voltage Swing V
Power Consumption P
Supply Current I

NOTES

1

TCVOS is 100% tested.

2

Guaranteed by endpoint limits.

3

Guaranteed by CMRR test condition.

4

To insure high open-loop gain throughout the ±10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

Specifications subject to change without notice.

VO
O
D

SY

= ±13 V 120 140 120 140 dB

CM

= ±3 V to ±18 V 120 125 110 120 dB

S

RL ≥ 2 kΩ, VO = ±10 V42000 6000 2000 6000 V/mV
RL ≥ 2 kΩ±12 ±13.0 ±12 ±13.0 V
VS = ±15 V, No Load 60 75 60 75 mW
VS = ±15 V, No Load 2.0 2.5 2.0 2.5 mA

–2–

REV. B

ELECTRICAL CHARACTERISTICS

(@ VS = 615 V, TA = +258C, unless otherwise noted)

OP177

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

OP177E OP177F OP177G

Input Offset Voltage V

OS

41010252060µV

Long-Term Input Offset

Voltage Stability ∆VOS/Time (Note 1) 0.2 0.3 0.4 µV/Mo

Input Offset Current I
Input Bias Current I
Input Noise Voltage e
Input Noise Current i

OS
B
n

n

fo = 1 Hz to 100 Hz
fo = 1 Hz to 100 Hz

2
2

0.3 1.0 0.3 1.5 0.3 2.8 nA

–0.2 1.0 1.5 –0.2 1.2 2.0 –0.2 1.2 2.8 nA

118 150 118 150 118 150 nV rms
38 38 38pA

rms

Input Resistance

Differential-Mode R

IN

(Note 3) 26 45 26 45 18.5 45 MΩ

Input Resistance

Common-Mode R

INCM

200 200 200 GΩ

Input Voltage Range IVR (Note 4) ± 13 ±14 ±13 ±14 ±13 ±14 V
Common-Mode

Rejection Ratio CMRR VCM = ±13 V 130 140 130 140 115 140 dB

Power Supply

Rejection Ratio PSRR VS = ±3 V to ±18 V 120 125 115 125 110 120 dB

Large Signal RL ≥ 2 kΩ,

Voltage Gain A

VO

VO = ±10 V

5

5000 12000 5000 12000 2000 6000 V/mV

Output Voltage

Swing V

O

RL ≥ 10 kΩ±13.5 ±14.0 ±13.5 ±14.0 ± 13.5 ±14.0 V
RL ≥ 2 kΩ±12.5 ±13.0 ±12.5 ±13.0 ± 12.5 ±13.0 V

Slew Rate SR RL ≥ 2 kΩ

RL ≥ 1 kΩ±12.0 ±12.5 ±12.0 ±12.5 ± 12.0 ±12.5 V

Closed-Loop

Bandwidth BW A

VCL

= +1

2

2

0.1 0.3 0.1 0.3 0.1 0.3 V/µs

0.4 0.6 0.4 0.6 0.4 0.6 MHz

Open-Loop Output

Resistance R

Power Consumption P

O
D

VS = ±15 V, No Load 50 60 50 60 50 60 mW

60 60 60 Ω

VS = ±3 V, No Load 3.5 4.5 3.5 4.5 3.5 4.5 mW

Supply Current I

SY

VS = ±15 V, No Load 1.6 2.0 1.6 2.0 1.6 2.0 mA

Offset Adjustment

Range RP = 20 kΩ±3 ±3 ±3mV

NOTES

1

Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the ini­tial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 µV.

2

Sample tested.

3

Guaranteed by design.

4

Guaranteed by CMRR test condition.

5

To insure high open-loop gain throughout the ±10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

Specifications subject to change without notice.

REV. B

–3–

OP177–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 615 V, –40°C ≤ TA ≤ +858C, unless otherwise noted)

OP177E OP177F OP177G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Input Offset Voltage V

OS

10 20 15 40 20 100 µV

Average Input Offset

Voltage Drift TCV

Input Offset Current I

OS

(Note 1) 0.03 0.1 0.1 0.3 0.7 1.2 µV/°C

OS

0.5 1.5 0.5 2.2 0.5 4.5 nA

Average Input Offset

Current Drift TCI

Input Bias Current I

B

(Note 2) 1.5 25 1.5 40 1.5 85 pA/°C

OS

–0.2 2.4 4 –0.2 2.4 4 2.4 ±6.0 nA

Average Input Bias

Current Drift TCI

(Note 2) 8 25 8 40 15 60 pA/°C

B

Input Voltage Range IVR (Note 3) ±13 ± 13.5 ±13 ± 13.5 ±13.0 ±13.5 V
Common-Mode

Rejection Ratio CMRR VCM = ±13 V 120 140 120 140 110 140 dB

Power Supply Rejection

Ratio PSRR VS = ±3 V to ±18 V 120 125 110 120 106 115 dB

Large-Signal

Voltage Gain A
Output Voltage Swing V
Power Consumption P
Supply Current I

NOTES

1

OP177E: TCVOS is 100% tested.

2

Guaranteed by endpoint limits.

3

Guaranteed by CMRR test condition.

4

To insure high open-loop gain throughout the ±10 V output range, AVO is tested at –10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.

Specifications subject to change without notice.

VO
O
D

SY

RL ≥ 2 kΩ, VO = ±10 V42000 6000 2000 6000 1000 4000 V/mV
RL ≥ 2 kΩ±12 ±13.0 ±12 ±13.0 ±12.0 ±13.0 V
VS = ±15 V, No Load 60 75 60 75 60 75 mW
VS = ±15 V, No Load 2.0 2.5 2.0 2.5 2.0 2.5

mA

Figure 2. Typical Offset Voltage Test Circuit

Figure 3. Optional Offset Nulling Circuit

REV. B–4–

Figure 4. Burn-In Circuit

OP177

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V

Internal Power Dissipation

1

. . . . . . . . . . . . . . . . . . . 500 mW

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±30 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

Z and RC Packages . . . . . . . . . . . . . . . . . –65°C to +150°C

S, P Package . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Operating Temperature Range

OP177A, OP177B . . . . . . . . . . . . . . . . . –55°C to +125°C

OP177E, OP177F, OP177G . . . . . . . . . . –40°C to +85°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C

DICE Junction Temperature (T

Package Type u

) . . . . . . . –65°C to +150°C

J

2

JA

u

JC

Units

8-Pin Hermetic DIP (Z) 148 16 °C/W
8-Pin Plastic DIP (P) 103 43 °C/W
20-Contact LCC (RC) 98 38 °C/W
8-Pin SO (S) 158 43 °C/W

NOTES

1

For supply voltages less than ±22 V, the absolute maximum input voltage is equal

to the supply voltage.

2

θJA is specified for worst case mounting conditions, i.e., θJA is specified for

device in socket for cerdip, P-DIP, and LCC packages; θJA is specified for
device soldered to printed circuit board for SO package.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP177AZ –55°C to +125°C 8-Pin Cerdip Q-8
OP177BZ –55°C to +125°C 8-Pin Cerdip Q-8
OP177EZ –40°C to +85°C 8-Pin Cerdip Q-8
OP177FZ –40°C to +85°C 8-Pin Cerdip Q-8
OP177GZ –40°C to +85°C 8-Pin Cerdip Q-8
OP177FP –40°C to +85°C 8-Pin Plastic DIP N-8
OP177GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP177BRC/883 –55°C to +125°C 20-Pin LCC E-20A
OP177FS –40°C to +85°C 8-Pin SO SO-8
OP177GS –40°C to +85°C 8-Pin SO SO-8

REV. B

–5–

OP177–Typical Performance Characteristics

Figure 5. Gain Linearity (Input
Voltage vs. Output Voltage)

Figure 8. Offset Voltage Change
Due to Thermal Shock

Figure 6. Power Consumption vs.
Power Supply

Figure 9. Open-Loop Gain
vs. Temperature

Figure 7. Warm-Up VOS Drift
(Normalized) Z Package

Figure 10. Open-Loop Gain vs.
Power Supply Voltage

Figure 11. Input Bias Current
vs. Temperature

Figure 12. Input Offset Current
vs. Temperature

Figure 13. Closed-Loop Response
for Various Gain Configurations

OP177

Figure 14. Open-Loop
Frequency Response

Figure 17. Total Input Noise
Voltage vs. Frequency

Figure 15. CMRR vs. Frequency

Figure 18. Input Wideband Noise
vs. Bandwidth (0.1 Hz to
Frequency Indicated)

Figure 16. PSRR vs. Frequency

Figure 19. Maximum Output Swing
vs. Frequency

REV. B

Figure 20. Maximum Output Voltage
vs. Load Resistance

Figure 21. Output Short Circuit
Current vs. Time

–7–

OP177

R1
R2

R3
R4

APPLICATIONS INFORMATION
Gain Linearity

The actual open-loop gain of most monolithic op amps varies at
different output voltages. This nonlinearity causes errors in high
closed-loop gain circuits.

It is important to know that the manufacturer’s AVO specifi­cation is only a part of the solution, since all automated testers
use endpoint testing and, therefore, only show the average gain.
For example, Figure 22 shows a typical precision op amp with a
respectable open-loop gain of 650 V/mV. However, the gain is
not constant through the output voltage range, causing
nonlinear errors. An ideal op amp would show a horizontal
scope trace.

Figure 22. Typical Precision Op Amp

THERMOCOUPLE AMPLIFIER WITH COLD-JUNCTION
COMPENSATION

An example of a precision circuit is a thermocouple amplifier
that must amplify very low level signals accurately without
introducing linearity and offset errors to the circuit. In this
circuit, an S-type thermocouple, which has a Seebeck coefficient
of 10.3 µV/°C, produces 10.3 mV of output voltage at a
temperature of 1,000°C. The amplifier gain is set at 973.16.
Thus, it will produce an output voltage of 10.024 V. Extended
temperature ranges to beyond 1,500°C can be accomplished by
reducing the amplifier gain. The circuit uses a low-cost diode to
sense the temperature at the terminating junctions and in turn
compensates for any ambient temperature change. The OP177,
with its high open-loop gain, plus low offset voltage and drift
combines to yield a very precision temperature sensing circuit. Cir­cuit values for other thermocouple types are shown in Table I.

Table I.

Thermo- Seebeck
couple Type Coefficient R1 R2 R7 R9

K 39.2 µV/°C 110 Ω 5.76 kΩ 102 kΩ 269 kΩ
J 50.2 µV/°C 100 Ω 4.02 kΩ 80.6 kΩ 200 kΩ
S 10.3 µV/°C 100 Ω 20.5 kΩ 392 kΩ 1.07 MΩ

Figure 23. OP177’s Output Gain Linearity Trace

Figure 24. Open-Loop Gain Linearity Test Circuit

Figure 23 shows the OP177’s output gain linearity trace with its
truly impressive average AVO of 12000 V/mV. The output trace
is virtually horizontal at all points, assuring extremely high gain
accuracy. PMI also performs additional testing to insure
consistent high open-loop gain at various output voltages.

Figure 24 is a simple open-loop gain test circuit for your own
evaluation.

Figure 25. Thermocouple Amplifier with Cold Junction
Compensation

PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER

The high gain, gain linearity, CMRR, and low TCVOS of the
OP177 make it possible to obtain performance not previously
available in single stage, very high-gain amplifier applications.
See Figure 26.

For best CMR,

must equal

. In this example, with a

10 mV differential signal, the maximum errors are as listed in
Table II.

Figure 26. Precision High Gain Differential Amplifier

Table II. High Gain Differential Amp Performance

OP177

ISOLATING LARGE CAPACITIVE LOADS

The circuit in Figure 27 reduces maximum slew-rate but allows
driving capacitive loads of any size without instability. Because
the 100 Ω resistor is inside the feedback loop, its effect on
output impedance is reduced to insignificance by the high open­loop gain of the OP177.

Type Amount

Common-Mode Voltage 0.1%/V
Gain Linearity, Worst Case 0.02%
TCV
TCI

OS

OS

0.0003%/°C

0.008%/°C

Figure 28. Bilateral Current Source

Figure 27. Isolating Capacitive Loads

Figure 29. Precision Absolute Value Amplifier

OP177

BILATERAL CURRENT SOURCE

The current sources shown in Figure 28 will supply both
positive and negative current into a grounded load.

Note that ZO

=

R5+R4

R5

R2






R4
R2

–

+1

R3

R1






and that for ZO to be infinite,

R5+R4

R2

must =

R3
R1

PRECISION ABSOLUTE VALUE AMPLIFIER

The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps. The
OP177E CMRR of 140 dB assures errors of less than 1 ppm.
See Figure 29.

Figure 30. Precision Positive Peak Detector

PRECISION POSITIVE PEAK DETECTOR

In Figure 30, the CH must be of polystyrene, Teflon*, or
polyethylene to minimize dielectric absorption and leakage. The
droop rate is determined by the size of C

and the bias current

H

of the OP41.

PRECISION THRESHOLD DETECTOR/AMPLIFIER

In Figure 32, when VIN < VTH, amplifier output swings nega­tive, reverse biasing diode D
V

≥ V

IN

C

C

*Teflon is a registered trademark of the Dupont Company.

, the loop closes,

TH

V

OUT=VTH

is selected to smooth the response of the loop.

. V

= VTH if R

1

OUT

+ VIN–V

()

TH

= ∞. When

L








R

F

1+



R



S

Figure 31.Precision Threshold Detector/Amplifier

–10–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

OP177

0.005 (0.13) MIN

PIN 1

0.200

(5.08)

MAX

0.200 (5.08)

0.125 (3.18)

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

8

1

0.405 (10.29) MAX

0.023 (0.58)

0.014 (0.36)

8

1

0.430 (10.92)

8-Pin Cerdip

0.055 (1.4) MAX

5

4

0.100

0.070 (1.78)

(2.54)

0.030 (0.76)

BSC

8-Pin Plastic DIP

5

4

0.348 (8.84)

0.100

0.070 (1.77)

(2.54)

0.045 (1.15)

BSC

(Q-8)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

(N-8)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

15

°

0

°

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

0.358 (9.09)

0.342 (8.69)
SQ

TOP

VIEW

8

1

0.1968 (5.00)

0.1890 (4.80)

0.0500
(1.27)

BSC

0.100 (2.54)

0.064 (1.63)

0.358

(9.09)

MAX

SQ

5

4

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.088 (2.24)

0.054 (1.37)

8-Pin SO

(SO-08)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.0098 (0.25)

0.0075 (0.19)

20-Pin LCC

(E-20A)

0.075
(1.91)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

REF

19

18

14

13

8

°

0

°

0.200 (5.08)
BSC

20

1

BOTTOM

VIEW

0.150 (3.81)
BSC

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

0.100 (2.54) BSC

0.015 (0.38)

3

MIN

4

0.028 (0.71)

0.022 (0.56)

0.050 (1.27)

8

BSC

9

45° TYP

x 45

°

REV. B

–11–

C2087–5–11/95

–12–

PRINTED IN U.S.A.