Datasheet OP162 Datasheet (Analog Devices)

O

A

15 MHz Rail-to-Rail

FEATURES

Wide bandwidth: 15 MHz Low offset voltage: 325 µV max

Hz

Low noise: 9.5 nV/√ Single-supply operation: 2.7 V to 12 V Rail-to-rail output swing Low TCV

: 1 µV/°C typ

OS

High slew rate: 13 V/µs No phase inversion Unity-gain stable

APPLICATIONS

Portable instrumentation Sampling ADC amplifier Wireless LANs Direct access arrangement Office automation

GENERAL DESCRIPTION

The OP162 (single), OP262 (dual), and OP462 (quad) rail-torail 15 MHz amplifiers feature the extra speed new designs require, with the benefits of precision and low power operation. With their incredibly low offset voltage of 45 µV (typical) and low noise, they are perfectly suited for precision filter applications and instrumentation. The low supply current of 500 µA (typical) is critical for portable or densely packed designs. In addition, the rail-to-rail output swing provides greater dynamic range and control than standard video amplifiers.

These products operate from single supplies as low as 2.7 V to dual supplies of ±6 V. The fast settling times and wide output swings recommend them for buffers to sampling A/D converters. The output drive of 30 mA (sink and source) is needed for many audio and display applications; more output current can be supplied for limited durations. The OPx62 family is specified over the extended industrial temperature range (–40°C to +125°C). The single OP162 amplifiers are available in 8-lead SOIC, MSOP, and TSSOP packages. The dual OP262 amplifiers are available in 8-lead SOIC and TSSOP packages. The quad OP462 amplifiers are available in 14-lead, narrow-body SOIC and TSSOP packages.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

@ 1 kHz

Operational Amplifiers

OP162/OP262/OP462

PIN CONFIGURATIONS

NULL

1

–IN A

+IN A

OP162

2

3

TOP VIEW

(Not to Scale)

4

V–

NC = NO CONNECT

Figure 1. 8-Lead Narrow-Body SOIC (S Suffix)

1

NULL

2

–IN A +IN A

V–

OP162

TOP VIEW

3

(Not to Scale)

4

NC = NO CONNECT

Figure 2. 8-Lead TSSOP (RU Suffix)

8-Lead MSOP (RM Suffix)

OUT A

1

V–

OP262

2

3

TOP VIEW

(Not to Scale)

4

–IN A

+IN A

Figure 3. 8-Lead Narrow-Body SOIC (S Suffix)

1

OUT A

2

–IN A +IN A

V–

OP262

TOP VIEW

3

(Not to Scale)

4

Figure 4. 8-Lead TSSOP (RU Suffix)

OUT A

1

2

–IN A

+IN A

3

OP462

TOP VIEW

V+

4

(Not to Scale)

+IN B

5

–IN B

6

7

OUT B

Figure 5. 14-Lead Narrow-Body SOIC (S Suffix)

1

OUT

2

–IN A

3

+IN A

V+

+IN B

–IN B

UT B

TOP VIEW

4

(Not to Scale)

5

6

7

OP462

Figure 6. 14-Lead TSSOP (RU Suffix)

www.analog.com

NULL

8

V+

7

OUT A

6

5

NC

00288-001

8

NULL

7

V+

6

OUT A

5

NC

00288-002

V+

8

OUT B

7

–IN B

6

5

+IN B

00288-003

8

V+

7

OUT B

6

–IN B

5

+IN B

00288-004

OUT D

14

13

–IN D

+IN D

12

V–

11

+IN C

10

–IN C

9

8

OUT C

00288-005

14

OUT D

13

–IN D

12

+IN D

11

V–

10

+IN C

9

–IN C

8

OUT C

00288-006

OP162/OP262/OP462

TABLE OF CONTENTS

Specifications........................................................................................... 3

Absolute Maximum Ratings.................................................................6

ESD Caution.................................................................................. 6

Typical Per f o r mance C h a r acter i s t ics .................................................. 7

Appl ications ...........................................................................................12

Functional Description .............................................................. 12

Offset Adjustment ...................................................................... 12

Power-On Settling Time............................................................ 14

Capacitive Load Drive ............................................................... 14

Total Harmonic Distortion and Crosstalk .............................. 15

PCB Layout Considerations...................................................... 15

Application Circuits ............................................................................ 16

Single-Supply Stereo Headphone Driver................................. 16

Rail-to-Rail Output .................................................................... 12

Output Short-Circuit Protection.............................................. 12

Input Overvoltage Protection................................................... 13

Output Phase Reversal............................................................... 13

Power Dissipation....................................................................... 13

Unused Amplifiers ..................................................................... 14

REVISION HISTORY

1/05—Rev. E to Rev. F

Changes to Absolute Maximum Ratings Table 4 and Table 5 .... 6

Change to Figure 36 ....................................................................... 13

Changes to Ordering Guide.......................................................... 20

12/04—Rev. D to Rev. E

Updated Format..................................................................Universal

Changes to General Description .................................................... 1

Changes to Specifications................................................................ 3

Changes to Package Type................................................................. 6

Change to Figure 16 ......................................................................... 8

Change to Figure 22 ......................................................................... 9

Change to Figure 36 ....................................................................... 13

Change to Figure 37 ....................................................................... 14

Changes to Ordering Guide.......................................................... 20

10/02—Rev. C to Rev. D

Deleted 8-Lead Plastic DIP (N-8) ....................................Universal

Deleted 14-Lead Plastic DIP (N-14) ................................Universal

Edits to ORDERING GUIDE........................................................ 19

Edits to Figure 30............................................................................ 19

Edits to Figure 31............................................................................ 19

Updated Outline Dimensions....................................................... 19

Instrumentation Amplifier........................................................ 16

Direct Access Arrangement...................................................... 17

Spice Macro-Model .................................................................... 18

Outline Dimensions ............................................................................ 19

Ordering Guide .......................................................................... 20

Rev. F | Page 2 of 20

OP162/OP262/OP462

SPECIFICATIONS

@ VS = 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 1. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40°C ≤ TA ≤ +125°C 800 µV H grade, –40°C ≤ TA ≤ +125°C 1 mV D grade 0.8 3 mV –40°C ≤ TA ≤ +125°C 5 mV Input Bias Current I

B

–40°C ≤ TA ≤ +125°C 650 nA Input Offset Current I

OS

–40°C ≤ TA ≤ +125°C ±40 nA Input Voltage Range V

CM

Common-Mode Rejection CMRR 0 V ≤ VCM ≤ 4.0 V, –40°C ≤ TA ≤ +125°C 70 110 dB Large Signal Voltage Gain A

VO

R R Long-Term Offset Voltage Offset Voltage Drift Bias Current Drift

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

1

2

V

OS

∆VOS/∆T ∆I

/∆T

B

OH

I Output Voltage Swing Low V

OL

I Short-Circuit Current I Maximum Output Current I

POWER SUPPLY

SC

OUT

Power Supply Rejection Ratio PSRR VS = 2.7 V to 7 V 120 dB –40°C ≤ TA ≤ +125°C 90 dB Supply Current/Amplifier I

SY

–40°C ≤ TA ≤ +125°C 1 mA OP262, OP462, V –40°C ≤ TA ≤ +125°C 850 µA DYNAMIC PERFORMANCE

Slew Rate SR 1 V < V Settling Time t

S

Gain Bandwidth Product GBP 15 MHz Phase Margin φ

NOISE PERFORMANCE

m

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p Voltage Noise Density e

Current Noise Density i

1

Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.

2

Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.

n

OP162G, OP262G, OP462G 45 325 µV

360 600 nA

±2.5 ±25 nA

0 4 V

RL = 2 kΩ, 0.5 ≤ V

= 10 kΩ, 0.5 ≤ V

L

= 10 kΩ, –40°C ≤ TA ≤ +125°C 40 V/mV

L

≤ 4.5 V 30 V/mV

OUT

≤ 4.5 V 65 88 V/mV

OUT

G grade 600 µV 1 µV/°C 250 pA/°C

IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.95 4.99 V

= 5 mA 4.85 4.94 V

L

IL = 250 µA, –40°C ≤TA ≤ +125°C 14 50 mV

= 5 mA 65 150 mV

L

Short to ground ±80 mA ±30 mA

OP162, V

= 2.5 V 600 750 µA

OUT

= 2.5 V 500 700 µA

OUT

< 4 V, RL = 10 kΩ 10 V/µs

OUT

To 0.1%, AV = –1, VO = 2 V step 540 ns

61 Degrees

f = 1 kHz 9.5 f = 1 kHz 0.4

nV/√ pA/√

Hz Hz

Rev. F | Page 3 of 20

OP162/OP262/OP462

@ VS = 3.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V G, H grades, –40°C ≤ TA ≤ +125°C 1 mV D grade 0.8 3 mV –40°C ≤ TA ≤ +125°C 5 mV Input Bias Current I Input Offset Current I Input Voltage Range V Common-Mode Rejection CMRR 0 V ≤ VCM ≤ 2.0 V, –40°C ≤ TA ≤ +125°C 70 110 dB Large Signal Voltage Gain A R Long-Term Offset Voltage

1

OUTPUT CHARACTERISTICS

Output Voltage Swing High V I Output Voltage Swing Low V

I POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 7 V, –40°C ≤ TA ≤ +125°C 60 110 dB Supply Current/Amplifier I

–40°C ≤ TA ≤ +125°C 1 mA OP262, OP462, V –40°C ≤ TA ≤ +125°C 850 µA DYNAMIC PERFORMANCE

Slew Rate SR RL = 10 kΩ 10 V/µs Settling Time t Gain Bandwidth Product GBP 15 MHz Phase Margin φ

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p Voltage Noise Density e

Current Noise Density i

1

Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.

OS

B

OS

CM

VO

V

OS

OH

OL

SY

S

m

n

OP162G, OP262G, OP462G 50 325 µV

360 600 nA ±2.5 ±25 nA 0 2 V

RL = 2 kΩ, 0.5 V ≤ V

= 10 kΩ, 0.5 V ≤ V

L

G grade 600 µV

IL = 250 µA 2.95 2.99 V

= 5 mA 2.85 2.93 V

L

IL = 250 µA 14 50 mV

= 5 mA 66 150 mV

L

OP162, V

= 1.5 V 600 700 µA

OUT

To 0.1%, AV = –1, VO = 2 V step 575 ns

59 Degrees

f = 1 kHz 9.5 f = 1 kHz 0.4

≤ 2.5 V 20 V/mV

OUT

≤ 2.5 V 20 30 V/mV

OUT

= 1.5 V 500 650 µA

OUT

nV/√ pA/√

Hz

Rev. F | Page 4 of 20

OP162/OP262/OP462

@ VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 3. Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

H grade, –40°C ≤ TA ≤ +125°C 1 mV D grade 0.8 3 mV

Input Bias Current I

B

Input Offset Current I

OS

Input Voltage Range V

CM

Common-Mode Rejection CMRR Large Signal Voltage Gain A

VO

R

Long-Term Offset Voltage1 V Offset Voltage Drift2 Bias Current Drift

∆V ∆I

OS

/∆T

B

/∆T

OUTPUT CHARACTERISTICS

Output Voltage Swing High VOH IL = 250 µA, –40°C ≤ TA ≤ +125°C 4.95 4.99 V I Output Voltage Swing Low VOL IL = 250 µA, –40°C ≤ TA ≤ +125°C –4.99 –4.95 V I Short-Circuit Current ISC Short to ground ±80 mA Maximum Output Current I

±30 mA

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±1.35 V to ±6 V,

Supply Current/Amplifier ISY OP162, V

OP262, OP462, V

Supply Voltage Range VS 3.0 (±1.5) 12 (±6) V

DYNAMIC PERFORMANCE

Slew Rate SR Settling Time tS To 0.1%, AV = –1, VO = 2 V step 475 ns

Gain Bandwidth Product GBP 15 MHz Phase Margin φm 64 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.5 µV p-p Voltage Noise Density en f = 1 kHz 9.5

Current Noise Density in f = 1 kHz 0.4

1

Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125°C, with an LTPD of 1.3.

2

Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.

OP162G, OP262G, OP462G 25 325 µV

−40°C ≤ T

≤ +125°C

A

≤ +125°C

A

800 µV

5 mV

260 500 nA

−40°C ≤ T

≤ +125°C

A

650 nA

±2.5 ±25 nA

−40°C ≤ T

≤ +125°C

A

±40 nA

–5 +4 V

−4.9 V ≤ V

≤ +4.0 V, –40°C ≤ TA ≤ +125°C

CM

RL = 2 kΩ, –4.5 V ≤ V

= 10 kΩ, –4.5 V ≤ V

L

−40°C ≤ T

≤ +125°C

A

≤ +4.5 V 35 V/mV

OUT

≤ +4.5 V 75 120 V/mV

OUT

70 110 dB

25 V/mV

G grade 600 µV 1 µV/°C 250 pA/°C

= 5 mA 4.85 4.94 V

L

= 5 mA –4.94 –4.85 V

L

−40°C ≤ T

−4 V < V

≤ +125°C

A

= 0 V 650 800 µA

OUT

≤ +125°C

A

= 0 V 550 775 µA

OUT

≤ +125°C

A

< 4 V, RL = 10 kΩ

OUT

60 110 dB

1.15 mA

1 mA

13 V/µs

nV/√ pA/√

Hz Hz

Rev. F | Page 5 of 20

OP162/OP262/OP462

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Min

Supply Voltage ±6 V Input Voltage Differential Input Voltage Internal Power Dissipation

1

2

±6 V ±0.6 V

SOIC (S) Observe Derating Curves MSOP (RM) Observe Derating Curves TSSOP (RU) Observe Derating Curves

Output Short-Circuit Duration Observe Derating Curves Storage Temperature Range –65°C to +150°C Operating Temperature Range –40°C to +125°C Junction Temperature Range –65°C to +150°C Lead Temperature Range

(Soldering, 10 sec) 300°C

1

For supply voltages greater than 6 V, the input voltage is limited to less than

or equal to the supply voltage.

2

For differential input voltages greater than 0.6 V, the input current should be

limited to less than 5 mA to prevent degradation or destruction of the input devices.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 5.

Package Type

1

θ

JA

θ

Unit

JC

8-Lead SOIC (S) 157 56 °C/W 8-Lead TSSOP (RU) 208 °C/W 8-Lead MSOP (RM) 190 44 °C/W 14-Lead SOIC (S) 105 °C/W 14-Lead TSSOP (RU) 148 °C/W

____________________________

1

θJA is specified for the worst-case conditions, that is, θJA is specified for a

device soldered in circuit board for SOIC, MSOP, and TSSOP packages.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. F | Page 6 of 20

OP162/OP262/OP462

TYPICAL PERFORMANCE CHARACTERISTICS

250

200

VS = 5V

= 25°C

T

A

COUNT = 720 OP AMPS

125

VS = 5V

100

150

100

QUANTITY (Amplifiers)

50

0 –200 –140 –80 –20 10040 160

INPUT OFFSET VOLTAGE (µV)

Figure 7. OP462 Input Offset Voltage Distribution

100

VS = 5V

80

60

40

QUANTITY (Amplifiers)

20

0

0.2 0.3 0.5 0.7 0.9 1.31.1 1.5 INPUT OFFSET DRIFT, TCV

T COUNT = 360 OP AMPS

(µV,°C)

OS

Figure 8. OP462 Input Offset Voltage Drift (TCV

= 25°C

A

75

50

INPUT OFFSET VOLTAGE (µV)

25

00288-007

0

–75 –50 –25 0 25 50 10075 125 150

TEMPERATURE (°C)

00288-010

Figure 10. OP462 Input Offset Voltage vs. Temperature

0

VS = 5V

–100

–200

–300

INPUT BIAS CURRENT (nA)

–400

00288-008

)

OS

–500

–50 –25 0 25 50 10075 125 150

TEMPERATURE (°C)

Figure 11. OP462 Input Bias Current vs. Temperature

00288−011

420

VS = 5V

340

260

INPUT CURRENT (nA)

180

100

0 0.5 1.0 1.5 2.0 3.02.5 3.5 4.0

COMMON-MODE VOLTAGE (V)

Figure 9. OP462 Input Bias Current vs. Common-Mode Voltage

00288-009

Rev. F | Page 7 of 20

15

10

5

INPUT OFFSET CURRENT (nA)

0

–75 –50 –25 0 25 50 10075 125 150

TEMPERATURE (°C)

Figure 12. OP462 Input Offset Current vs. Temperature

VS = 5V

00288−012

OP162/OP262/OP462

5.12

5.06

5.00

4.94

OUTPUT HIGH VOLTAGE (V)

4.88

4.82 –75 –50 –25 0 25 50 10075 125 150

Figure 13. OP462 Output High Voltage vs. Temperature

0.100

0.080

0.060

0.040

OUTPUT LOW VOLTAGE (mV)

0.020

0.000 –75 –50 –25 0 25 50 10075 125 150

Figure 14. OP462 Output Low Voltage vs. Temperature

I

= 250µA

OUT

I

= 5mA

OUT

TEMPERATURE (°C)

I

= 5mA

OUT

I

= 250µA

OUT

TEMPERATURE (°C)

VS = 5V

00288-013

00288-014

100

80

60

40

OUTPUT LOW VOLTAGE (mV)

20

0

01 234 567

VS = 10V

VS = 3V

LOAD CURRENT (mA)

Figure 16. Output Low Voltage to Supply Rail vs. Load Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

SUPPLY CURRENT (mA)

0.2

0.1 0

–75 –50 –25 0 25 10075 125 150

VS = 5V

TEMPERATURE (°C)

VS = 10V

VS = 3V

Figure 17. Supply Current/Amplifier vs. Temperature

00288-016

00288-017

100

RL = 10kΩ

80

VS = 5V

60

40

OPEN-LOOP GAIN (V/mV)

20

0

–75 –50 –25 0 25 50 10075 125 150

RL = 2kΩ

RL = 600kΩ

TEMPERATURE (°C)

Figure 15. OP462 Open-Loop Gain vs. Temperature

00288-015

Rev. F | Page 8 of 20

0.7

0.6

0.5

SUPPLY CURRENT (mA)

0.4

024 68101

SUPPLY VOLTAGE (V)

TA = 25°C

Figure 18. OP462 Supply Current/Amplifier vs. Supply Voltage

00288-018

2

OP162/OP262/OP462

50

40

30

20

10

GAIN (dB)

0

–10

–20

–30

100k 1M 10M 100M

GAIN

FREQUENCY (Hz)

VS = 5V

= 25°C

T

A

PHASE

Figure 19. Open-Loop Gain and Phase vs. Frequency (No Load)

45

90

135

180

225

270

PHASE SHIFT (dB)

00288-019

4

3

VS = 5V

2

T

= 25°C

A

1

0

STEP SIZE (V)

–1

–2

–3

–4

0 200 400 600 800 1000

SETTLING TIME (nS)

Figure 22. Step Size vs. Settling Time

0.01%0.1%

00288-022

60

40

20

0

CLOSED-LOOP GAIN (dB)

–20

–30

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 20. Closed-Loop Gain vs. Frequency

5

4

3

2

VS = 5V

= 1

A

VCL

RL = 10kΩ

1

C

MAXIMUM OUTPUT SWING (V p-p)

= 15pF

L

= 25°C

T

A

DISTORTION<1%

0

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 21. Maximum Output Swing vs. Frequency

VS = 5V T

= 25°C

A

R

= 830Ω

L

= 5pF

C

L

00288-020

00288-021

60

VS = 5V

= 25°C

T

A

T

= ±50mV

50

A

R

= 10kΩ

L

40

30

OVERSHOOT (%)

20

10

0

10 100 1000

CAPACITANCE (pF)

+OS

–OS

Figure 23. Small-Signal Overshoot vs. Capacitance

70

60

50

Hz)

√

40

30

20

NOISE DENSITY (nV/

10

0

1 10 100 1k

FREQUENCY (Hz)

Figure 24. Voltage Noise Density vs. Frequency

VS = 5V T

= 25°C

A

00288-023

00288-024

Rev. F | Page 9 of 20

OP162/OP262/OP462

7

VS = 5V

6

5

Hz)

√

4

3

2

NOISE DENSITY (pA/

1

0

1 10 100 1k

FREQUENCY (Hz)

T

Figure 25. Current Noise Density vs. Frequency

300

VS = 5V

250

)

Ω

200

150

100

OUTPUT IMPEDANCE (

50

0 100k 1M 10M

A

= 10

VCL

A

VCL

FREQUENCY (Hz)

T

= 1

Figure 26. Output Impedance vs. Frequency

= 25°C

A

= 25°C

A

00288-025

00288-026

90

80

70

60

+PSRR –PSRR

50

PSRR (dB)

40

30

20

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 28. PSRR v s. Frequency

2s20mV

100

90

10

0%

VS = 5V A

= 100kΩ

V

e

= 0.5µV p-p

n



Figure 29. 0.1 Hz to 10 Hz Noise

VS = 5V T

= 25°C

A

00288-029

00288-028

90

80

70

60

50

CMRR (dB)

40

30

20

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 27. CMRR vs. Fre quency

VS = 5V T

= 25°C

A

00288-027

Rev. F | Page 10 of 20

2V

100

90

10

0%

2V

Figure 30. No Phase Reversal (V

VIN = 12V p-p V

= ±5V

S

AV = 1

20µs

= 12 V p-p, VS = ±5 V, AV = 1)

IN

00288-030

OP162/OP262/OP462

= 5V

V

S

100

V

= 5V

S

A

= 1

V

T

90

A

C

L

= 25°C = 100pF

100

AV = 1 T

= 25°C

A

C

= 100pF

L

90

10

0%

Figure 31. Small Signal Transient Response

200ns20mV

00288-031

10

0%

500mV

Figure 32. Large Signal Transient Response

100µs

00288-032

Rev. F | Page 11 of 20

OP162/OP262/OP462

APPLICATIONS

FUNCTIONAL DESCRIPTION

The OPx62 family is fabricated using Analog Devices’ high speed complementary bipolar process, also called XFCB. This process trench isolates each transistor to lower parasitic capacitances for high speed performance. This high speed process has been implemented without sacrificing the excellent transistor matching and overall dc performance characteristic of Analog Devices’ complementary bipolar process. This makes the OPx62 family an excellent choice as an extremely fast and accurate low voltage op amp.

Figure 33 shows a simplified equivalent schematic for the OP162. A PNP differential pair is used at the input of the device. The cross connecting of the emitters lowers the transconductance of the input stage improving the slew rate of the device. Lowering the transconductance through cross connecting the emitters has another advantage in that it provides a lower noise factor than if emitter degeneration resistors were used. The input stage can function with the base voltages taken all the way to the negative power supply, or up to within 1 V of the positive power supply.

V

CC

+IN

V

–IN

OUT

OFFSET ADJUSTMENT

Because the OP162/OP262/OP462 have an exceptionally low typical offset voltage, adjustment to correct offset voltage may not be needed. However, the OP162 has pinouts to attach a nulling resistor. Figure 34 shows how the OP162 offset voltage can be adjusted by connecting a potentiometer between Pin 1 and Pin 8, and connecting the wiper to V avoid accidentally connecting the wiper to V

. It is important to

CC

, as this can damage

EE

the device. The recommended value for the potentiometer is 20 kΩ.

+5V

20kΩ

1

8

3

OP162

2

Figure 34. Offset Adjustment Schematic

–5V

7

6

4

V

OS

00288-034

RAIL-TO-RAIL OUTPUT

The OP162/OP262/OP462 have a wide output voltage range that extends to within 60 mV of each supply rail with a load current of 5 mA. Decreasing the load current extends the output voltage range even closer to the supply rails. The common-mode input range extends from ground to within 1 V of the positive supply. It is recommended that there be some minimal amount of gain when a rail-to-rail output swing is desired. The minimum gain required is based on the supply voltage and can be found as

V

EE

Figure 33. Simplified Schematic

00288-033

Two complementary transistors in a common-emitter configuration are used for the output stage. This allows the output of the device to swing to within 50 mV of either supply rail at load currents less than 1 mA. As load current increases, the maximum voltage swing of the output decreases. This is due to the collector-to-emitter saturation voltages of the output transistors increasing. The gain of the output stage, and consequently the open-loop gain of the amplifier, is dependent on the load resistance connected at the output. Because the dominant pole frequency is inversely proportional to the open-loop gain, the unity-gain bandwidth of the device is not affected by the load resistance. This is typically the case in rail-to-rail output devices.

Rev. F | Page 12 of 20

V

S

=

A

V,min

voltage of 5 V, the minimum gain to achieve rail-to-rail output

where V

is the positive supply voltage. With a single-supply

S

1−

V

S

should be 1.25.

OUTPUT SHORT-CIRCUIT PROTECTION

To achieve a wide bandwidth and high slew rate, the output of the OP162/OP262/OP462 are not short-circuit protected. Shorting the output directly to ground or to a supply rail may destroy the device. The typical maximum safe output current is ±30 mA. Steps should be taken to ensure the output of the device will not be forced to source or sink more than 30 mA.

In applications where some output current protection is needed, but not at the expense of reduced output voltage headroom, a low value resistor in series with the output can be used. This is shown in Figure 35. The resistor is connected within the feedback loop of the amplifier so that if V

is shorted to ground

OUT

OP162/OP262/OP462

V

and VIN swings up to 5 V, the output current will not exceed 30 mA. For single 5 V supply applications, resistors less than 169 Ω are not recommended.

5V

IN

OPx62

Figure 35. Output Short-Circuit Protection

169Ω

V

OUT

00288-035

INPUT OVERVOLTAGE PROTECTION

The input voltage should be limited to ±6 V, or damage to the device can occur. Electrostatic protection diodes placed in the input stage of the device help protect the amplifier from static discharge. Diodes are connected between each input as well as from each input to both supply pins as shown in the simplified equivalent circuit in Figure 33. If an input voltage exceeds either supply voltage by more than 0.6 V, or if the differential input voltage is greater than 0.6 V, these diodes energize causing overvoltage damage.

The input current should be limited to less than 5 mA to prevent degradation or destruction of the device by placing an external resistor in series with the input at risk of being overdriven. The size of the resistor can be calculated by dividing the maximum input voltage by 5 mA. For example, if the differential input voltage could reach 5 V, the external resistor should be 5 V/5 mA = 1 kΩ. In practice, this resistor should be placed in series with both inputs to balance any offset voltages created by the input bias current.

OUTPUT PHASE REVERSAL

The OP162/OP262/OP462 are immune to phase reversal as long as the input voltage is limited to ±6 V. Figure 30 shows the output of a device with the input voltage driven beyond the supply voltages. Although the device’s output does not change phase, large currents due to input overvoltage could result, damaging the device. In applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used, as described in the previous section.

POWER DISSIPATION

The maximum power that can be safely dissipated by the OP162/OP262/OP462 is limited by the associated rise in junction temperature. The maximum safe junction temperature is 150°C; device performance suffers when this limit is exceeded. If this maximum is only momentarily exceeded, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in an “overheated” condition for an extended period can result in permanent damage to the device.

To calculate the internal junction temperature of the OPx62, use the formula

= P

T

× θJA + T

J

DISS

A

where:

T

is the OPx62 junction temperature.

J

is the OPx62 power dissipation.

P

DISS

θ

is the OPx62 package thermal resistance, junction-to-

JA

ambient temperature.

is the ambient temperature of the circuit.

T

A

The power dissipated by the device can be calculated as

= I

P

DISS

× (VS – V

LOAD

OUT

)

where:

is the OPx62 output load current.

I

LOAD

is the OPx62 supply voltage.

V

S

V

is the OPx62 output voltage.

OUT

Figure 36 and Figure 37 provide a convenient way to determine if the device is being overheated. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature around the package. By using the previous equation, it is a simple matter to see if P

exceeds the

DISS

device’s power derating curve. To ensure proper operation, it is important to observe the recommended derating curves shown in Figure 36 and Figure 37.

0.9

0.8

0.7

0.6

0.5 8-LEAD MSOP

0.4

0.3

0.2

MAXIMUM POWER DISSIPATION (Watts)

0.1

0

20 40 60 10080 120

Figure 36. Maximum Power Dissipation vs. Temperature for

8-LEAD SOIC

8-LEAD TSSOP

AMBIENT TEMPERATURE (°C)

8-Lead Package Types

00288-036

Rev. F | Page 13 of 20

OP162/OP262/OP462

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

MAXIMUM POWER DISSIPATION (Watts)

0.1 0

20 45 70 95 120

Figure 37. Maximum Power Dissipation vs. Temperature for

UNUSED AMPLIFIERS

It is recommended that any unused amplifiers in a dual or a quad package be configured as a unity-gain follower with a 1 kΩ feedback resistor connected from the inverting input to the output, and the noninverting input tied to the ground plane.

POWER-ON SETTLING TIME

The time it takes for the output of an op amp to settle after a supply voltage is delivered can be an important consideration in some power-up-sensitive applications. An example of this would be in an A/D converter where the time until valid data can be produced after power-up is important.

The OPx62 family has a rapid settling time after power-up. Figure 38 shows the OP462 output settling times for a singlesupply voltage of V used to find the power-on settling times for the device.

14-LEAD SOIC

14-LEAD TSSOP

AMBIENT TEMPERATURE (°C)

14-Lead Package Types

= +5 V. The test circuit in Figure 39 was

S

00288-037

1

0 TO +5V SQUARE

OP462

10KΩ

V

OUT

00288-039

Figure 39. Test Circuit for Power-On Settling Time

CAPACITIVE LOAD DRIVE

The OP162/OP262/OP462 are high speed, extremely accurate devices that tolerate some capacitive loading at their outputs. As load capacitance increases, unity-gain bandwidth of an OPx62 device decreases. This also causes an increase in overshoot and settling time for the output. Figure 41 shows an example of this with the device configured for unity gain and driving a 10 kΩ resistor and 300 pF capacitor placed in parallel.

By connecting a series R-C network, commonly called a “snubber” network, from the output of the device to ground, this ringing can be eliminated and overshoot can be significantly reduced. Figure 40 shows how to set up the snubber network, and Figure 42 shows the improvement in output response with the network added.

5V

OPx62

V

IN

R

X

C

X

Figure 40. Snubber Network Compensation for Capacitive Loads

V

OUT

C

L

00288-040

2V

100

90

10 0%

50mV

Figure 38. Oscilloscope Photo of V

VS = 5V AV = 1 RL = 10kΩ

and V

S

500ns

OUT

00288-038

Rev. F | Page 14 of 20

100

90

10

0%

50mV 1µs

Figure 41. A Photo of a Ringing Square Wave

VS = 5V A

= 1

V

C

= 300pF

L

R

= 10k

L

Ω

00288-041

OP162/OP262/OP462

V

= 5V

S

A

= 1

V

C

= 300pF

100

90

10

0%

50mV

L

R

= 10k

Ω

L

WITH SNUBBER: R

= 140

Ω

X

CX = 10nF

µ

s

1



00288-042

Figure 42. A Photo of a Nice Square Wave at the Output

The network operates in parallel with the load capacitor, CL, and provides compensation for the added phase lag. The actual values of the network resistor and capacitor are empirically determined to minimize overshoot and maximize unity-gain bandwidth. Table 6 shows a few sample snubber networks for large load capacitors.

Table 6. Snubber Networks for Large Capacitive Loads

C

RX CX

LOAD

< 300 pF 140 Ω 10 nF 500 pF 100 Ω 10 nF 1 nF 80 Ω 10 nF 10 nF 10 Ω 47 nF

Higher load capacitance will reduce the unity-gain bandwidth of the device. Figure 43 shows unity-gain bandwidth vs. capacitive load. The snubber network does not provide any increase in bandwidth, but it substantially reduces ringing and overshoot, as shown between Figure 41 and Figure 42.

10

9

8

7

6

5

4

BANDWIDTH (MHz)

3

2

1 0

10pF 100pF 1nF 10nF

Figure 43. Unity-Gain Bandwidth vs. C

C

LOAD

00288-043

TOTAL HARMONIC DISTORTION AND CROSSTALK

The OPx62 device family offers low total harmonic distortion making it an excellent choice for audio applications. Figure 44 shows a graph of THD plus noise figures at 0.001% for the OP462.

Figure 45 shows the worst case crosstalk between two amplifiers in the OP462. A 1 V rms signal is applied to one amplifier while measuring the output of an adjacent amplifier. Both amplifiers are configured for unity gain and supplied with ±2.5 V.

0.010 VS = ±2.5V

A

= 1

V

= 1.0V rms

IN

R

= 10kΩ

L

BANDWIDTH: <10Hz TO 22kHz

0.001

THD+N (%)

0.0001 20 100 1k 10k 20k

FREQUENCY (Hz)

00288-044

Figure 44. THD + N vs. Frequency

–40

AV = 1

–50

V

= 1.0V rms

IN

(0dBV)

–60

R

= 10kΩ

L



V

= ±2.5V

S

–70

–80

–90

–100

XTALK (dBV)

–110

–120

–130 –140

20 100 1k 10k 20k

FREQUENCY (Hz)

00288-045

Figure 45. Cross talk vs. Frequency

PCB LAYOUT CONSIDERATIONS

Because the OP162/OP262/OP462 can provide gains at high frequency, careful attention to board layout and component selection is recommended. As with any high speed application, a good ground plane is essential to achieve the optimum performance. This can significantly reduce the undesirable effects of ground loops and I × R losses by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to ground plane.

Use chip capacitors for supply bypassing, with one end of the capacitor connected to the ground plane and the other end connected within 1/8 inch of each power pin. An additional large tantalum electrolytic capacitor (4.7 µF to 10 µF) should be connected in parallel. This capacitor provides current for fast, large-signal changes at the device’s output; therefore, it does not need to be placed as close to the supply pins.

Rev. F | Page 15 of 20

OP162/OP262/OP462

–

+

APPLICATION CIRCUITS

SINGLE-SUPPLY STEREO HEADPHONE DRIVER

Figure 46 shows a stereo headphone output amplifier that can operate from a single 5 V supply. The reference voltage is derived by dividing the supply voltage down with two 100 kΩ resistors. A 10 µF capacitor prevents power supply noise from contaminating the audio signal and establishes an ac ground for the volume control potentiometers.

The audio signal is ac-coupled to each noninverting input through a 10 µF capacitor. The gain of the amplifier is controlled by the feedback resistors and is (R2/R1) + 1. For this example, the gain is 6. By removing R1, the amplifier would have unity gain. To short-circuit protect the output of the device, a 169 Ω resistor is placed at the output in the feedback network. This prevents any damage to the device if the headphone output becomes shorted. A 270 µF capacitor is used at the output to couple the amplifier to the headphone. This value is much larger than that used for the input because of the low impedance of headphones, which can range from 32 Ω to 600 Ω or more.

LEFT IN

RIGHT IN

5V

R1 = 10kΩ

10µF

L VOLUME CONTROL

10kΩ

100kΩ

10kΩ

R VOLUME CONTROL

10µF

R1 = 10kΩ

Figure 46. Headphone Output Amplifier

OP262-A

100kΩ

10µF

OP262-B

10µF

R2 = 50kΩ

5V

R2 = 50kΩ

169Ω

270µF

47kΩ

270µF

47kΩ

HEADPHONE LEFT

HEADPHONE RIGHT

00288-046

INSTRUMENTATION AMPLIFIER

Because of their high speed, low offset voltages, and low noise characteristics, the OP162/OP262/OP462 can be used in a wide variety of high speed applications, including precision instrumentation amplifiers. Figure 47 shows an example of such an application.

V

IN

V

IN

Figure 47. High Speed Instrumentation Amplifier

The differential gain of the circuit is determined by RG, where

A

1

DIFF

with the R

resistor value in kΩ. Removing RG sets the circuit

G

gain to unity.

The fourth op amp, OP462-D, is optional and is used to improve CMRR by reducing any input capacitance to the amplifier. By shielding the input signal leads and driving the shield with the common-mode voltage, input capacitance is eliminated at common-mode voltages. This voltage is derived from the midpoint of the outputs of OP462-A and OP462-B by using two 10 kΩ resistors followed by OP462-D as a unity-gain buffer.

It is important to use 1% or better tolerance components for the 2 kΩ resistors, as the common-mode rejection is dependent on their ratios being exact. A potentiometer should also be connected in series with the OP462-C noninverting input resistor to ground to optimize common-mode rejection.

OP462-A

1kΩ

R

G

1kΩ

10kΩ

OP462-B

2

+=

R

G

2kΩ

10kΩ

2kΩ

OP462-COP462-D

1.9kΩ 200Ω

10 TURN (OPTIONAL)

OUTPUT

00288-047

The circuit in Figure 47 was implemented to test its settling time. The instrumentation amp was powered with −5 V, so the input step voltage went from −5 V to +4 V to keep the OP462 within its input range. Therefore, the 0.05% settling range is when the output is within 4.5 mV. Figure 48 shows the positive slope settling time to be 1.8 µs, and Figure 49 shows a settling time of 3.9 µs for the negative slope.

Rev. F | Page 16 of 20

OP162/OP262/OP462

5mV 2V

100

90

10

0%

5mV

5mV 2V

100

90

10

0%

Figure 48. Positive Slope Settling Time

1µs

Figure 49. Negative Slope Settling Time

1µs

00288-048

00288-049

DIRECT ACCESS ARRANGEMENT

Figure 50 shows a schematic for a 5 V single-supply transmit/ receive telephone line interface for 600 Ω transmission systems. It allows full-duplex transmission of signals on a transformercoupled 600 Ω line. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible differential signal to the transformer. The largest signal available on a single 5 V supply is approximately 4.0 V p-p into a 600 Ω transmission system. Amplifier A3 is configured as a difference amplifier to extract the receive information from the transmission line for amplification by A4. A3 also prevents the transmit signal from interfering with the receive signal. The gain of A4 can be adjusted in the same manner as A1 to meet the modem’s input signal requirements. Standard resistor values permit the use of SIP (single in-line package) format resistor arrays. Couple this with the OP462 14-lead SOIC or TSSOP package and this circuit offers a compact solution.

P1 TX GAIN ADJUST

TO TELEPHONE

LINE

1:1

Z

O

600Ω

T1

MIDCOM 671-8005

A1, A2 = 1/2 AD8532 A3, A4 = 1/2 AD8532

6.2V

R11

10kΩ

360Ω

R9

10kΩ

R12

10kΩ

R3

R5

10kΩ

R6

10kΩ

R10

10kΩ

2

A3

3

Figure 50. Single-Supply Direct Access Arrangement for Modems

R2

9.09kΩ



2k

2

1

A1

3

6

7

A2

5

R14

R13

14.3kΩ

10kΩ

1

6 5

R1

10kΩ

A4

C1

0.1µF

5V DC

10µF

P2

RX GAIN

ADJUST

2kΩ

7

TRANSMIT

R7 10kΩ

R8 10kΩ

C2

0.1µF

TXA

RECEIVE

RXA

00288-050

Rev. F | Page 17 of 20

OP162/OP262/OP462

SPICE MACRO-MODEL

* OP162/OP262/OP462 SPICE Macro-model

7/96, Ver. 1

* * Troy Murphy / ADSC *

* *

Refer to “README.DOC” file for License Statement. Use of this model

* *

indicates your acceptance of the terms and provisions in the License

* Statement *

Node Assignments

* * * | inverting input * | | * | | | * | | | | * | | | | | * | | | | | .SUBCKT OP162 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14, 20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 (20, 0) 1 G1 98 10 (5, 6) 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz *

noninverting input

positive supply

negative supply

output

ECM 13 98 POLY (2) (1, 98) (2, 98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 (10, 98) .588E-6 R4 21 98 1.7E6 R5 21 22 1.7E6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 (21, 98) 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 (24, 98) 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY (1) (99, 50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY (1) (98, 25) 0.70366 1 EB2 42 50 POLY (1) (25, 98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 . MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS

Rev. F | Page 18 of 20

OP162/OP262/OP462

Y

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 51. 8-Lead Standard Small Outline Package [SOIC] Narrow Body

S-Suffix (R-8)

Dimensions shown in millimeters and (inches)

3.00 BSC

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP]

5.10

5.00

4.90

14

0.65

BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

6.40

BSC

71

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

(RU-14)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

8° 0°

0.75

0.60

0.45

8

5

4

SEATING PLANE

4.90

BSC

1.10 MAX

0.23

0.08

8° 0°

3.00

BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 52. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.10

3.00

2.90

8

5

4.50

6.40 BSC

4.40

4.30

41

PIN 1

0.65 BSC

0.15

0.05

COPLANARIT

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AA

0.30

0.19

1.20 MAX

SEATING PLANE

0.20

0.09

8° 0°

0.75

0.60

0.45

Figure 53. 8-Lead Thin Shrink Small Outline Package [ TSSOP)

(RU-8)

Dimensions shown in millimeters

0.80

0.60

0.40

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14

1

1.27 (0.0500) BSC

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

8

6.20 (0.2441)

7

5.80 (0.2283)

SEATING PLANE

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8° 0°

1.27 (0.0500)

0.40 (0.0157)

× 45°

Figure 55. 14-Lead Standard Small Outline Package [SOIC] Narrow Body

S-Suffix (R-14)

Dimensions shown in millimeters and (inches)

Rev. F | Page 19 of 20

OP162/OP262/OP462

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

OP162GS −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP162GS-REEL −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP162GS-REEL7 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP162GSZ OP162GSZ-REEL1 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP162GSZ-REEL71 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP162DRU-REEL −40°C to +125°C 8-Lead TSSOP RU-8 OP162DRUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8 OP162HRU-REEL −40°C to +125°C 8-Lead TSSOP RU-8 OP162HRUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8 OP162DRM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AND OP162DRMZ-REEL OP262DRU-REEL −40°C to +125°C 8-Lead TSSOP RU-8 OP262DRUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8 OP262GS −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262GS-REEL −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262GS-REEL7 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262GSZ1 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262GSZ-REEL1 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262GSZ-REEL71 −40°C to +125°C 8-Lead SOIC S-Suffix (R-8) OP262HRU-REEL −40°C to +125°C 8-Lead TSSOP RU-8 OP262HRUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8 OP462DRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP462DRUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14 OP462DS −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462DS-REEL −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462DS-REEL7 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462DSZ1 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462DSZ-REEL1 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462DSZ-REEL71 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GS −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GS-REEL −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GS-REEL7 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GSZ1 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GSZ-REEL1 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462GSZ-REEL71 −40°C to +125°C 14-Lead SOIC S-Suffix (R-14) OP462HRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP462HRUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14

1

Z = Pb-free part.

1

−40°C to +125°C 8-Lead SOIC S-Suffix (R-8)

−40°C to +125°C 8-Lead MSOP RM-8 AOJ

C00288–0–1/05(F)

Rev. F | Page 20 of 20

Datasheet OP162 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PIN CONFIGURATIONS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS

FUNCTIONAL DESCRIPTION

OFFSET ADJUSTMENT

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OUTPUT PHASE REVERSAL

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UNUSED AMPLIFIERS

POWER-ON SETTLING TIME

CAPACITIVE LOAD DRIVE

TOTAL HARMONIC DISTORTION AND CROSSTALK

PCB LAYOUT CONSIDERATIONS

APPLICATION CIRCUITS

SINGLE-SUPPLY STEREO HEADPHONE DRIVER

INSTRUMENTATION AMPLIFIER

DIRECT ACCESS ARRANGEMENT

SPICE MACRO-MODEL

OUTLINE DIMENSIONS

ORDERING GUIDE