Datasheet OP1177, OP2177, OP4177 Datasheet (ANALOG DEVICES)

Precision Low Noise, Low Input

–

+

FEATURES

Low offset voltage: 60 μV maximum
Very low offset voltage drift: 0.7 μV/°C maximum
Low input bias current: 2 nA maximum
Low noise: 8 nV/√Hz typical
CMRR, PSRR, and A
Low supply current: 400 μA per amplifier
Dual supply operation: ±2.5 V to ±15 V
Unity-gain stable
No phase reversal
Inputs internally protected beyond supply voltage

APPLICATIONS

Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls

Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements

Precision filters

> 120 dB minimum

VO

Bias Current Operational Amplifiers

OP1177/OP2177/OP4177

PIN CONFIGURATIONS

NC

1

IN

2

18

NC
–IN

OP1177

+IN

V–

45

NC = NO CONNECT

NC
V+
OUT

NC

02627-001

OP1177

IN

3

V–

4

NC = NO CONNECT

Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix)

OUT A

1

–IN A

2

OUT A

–IN A
+IN A

18

OP2177

45

V–

V+
OUT B
–IN B

+IN B

02627-003

+IN A

OP2177

3

V–

4

Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix)

OUT A

1

213

–IN A

+IN A

3

OP4177

V+

4

5

+IN B

69

–IN B

78

OUT B

OUT D

14

–IN D

+IN D

12

11

V–

+IN C

10

–IN C

OUT C

OUT A

OUT B

02627-005

–IN A
+IN A

+IN B
–IN B

1

OP4177

V+

7

Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)

NC

8

V+

7

OUT

6

NC

5

02627-002

V+

8

OUT B

7

–IN B

6

+IN B

5

OUT D

14

–IN D
+IN D
V–
+IN C
–IN C

8

OUT C

02627-004

02627-006

GENERAL DESCRIPTION

The OPx177 family consists of very high precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power consump­tion. Outputs are stable with capacitive loads of over 1000 pF
with no external compensation. Supply current is less than 500 A
per amplifier at 30 V. Internal 500  series resistors protect the
inputs, allowing input signal levels several volts beyond either
supply without phase reversal.

Unlike previous high voltage amplifiers with very low offset
voltages, the OP1177 (single) and OP2177 (dual) amplifiers
are available in tiny 8-lead surface-mount MSOP and 8-lead
narrow SOIC packages. The OP4177 (quad) is available in
TSSOP and 14-lead narrow SOIC packages. Moreover, specified
performance in the MSOP and the TSSOP is identical to

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

performance in the SOIC package. MSOP and TSSOP are
available in tape and reel only.

The OPx177 family offers the widest specified temperature
range of any high precision amplifier in surface-mount packaging.
All versions are fully specified for operation from −40°C to
+125°C for the most demanding operating environments.

Applications for these amplifiers include precision diode
power measurement, voltage and current level setting, and
level detection in optical and wireless transmission systems.
Additional applications include line-powered and portable
instrumentation and controls—thermocouple, RTD, strain­bridge, and other sensor signal conditioning—and precision filters.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2001–2009 Analog Devices, Inc. All rights reserved.

OP1177/OP2177/OP4177

TABLE OF CONTENTS

Features .............................................................................................. 1

Overload Recovery Time .......................................................... 15

Applications ....................................................................................... 1

Pin Configurations ........................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Electrical Characteristics ............................................................. 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Functional Description .................................................................. 14

Total Noise-Including Source Resistors ................................... 14

Gain Linearity ............................................................................. 14

Input Overvoltage Protection ................................................... 15

Output Phase Reversal ............................................................... 15

THD + Noise ............................................................................... 16

Capacitive Load Drive ............................................................... 16

Stray Input Capacitance Compensation .................................. 17

Reducing Electromagnetic Interference .................................. 17

Proper Board Layout .................................................................. 18

Difference Amplifiers ................................................................ 18

A High Accuracy Thermocouple Amplifier ........................... 19

Low Power Linearized RTD ...................................................... 19

Single Operational Amplifier Bridge ....................................... 20

Realization of Active Filters .......................................................... 21

Band-Pass KRC or Sallen-Key Filter ........................................ 21

Channel Separation .................................................................... 21

References on Noise Dynamics and Flicker Noise ............... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 24

Settling Time ............................................................................... 15

REVISION HISTORY

11/09—Rev. F to Rev. G

Changes to Figure 64 ...................................................................... 19

Changes to Ordering Guide .......................................................... 24

Updated Outline Dimensions ....................................................... 22

5/09—Rev. E to Rev. F

Changes to Figure 64 ...................................................................... 19

Changes to Ordering Guide .......................................................... 24

10/07—Rev. D to Rev. E

Changes to General Description .................................................... 1

Changes to Table 4 ............................................................................ 5

Updated Outline Dimensions ....................................................... 22

7/06—Rev. C to Rev. D

Changes to Table 4 ............................................................................ 5

Changes to Figure 51 ...................................................................... 14

Changes to Figure 52 ...................................................................... 15

Changes to Figure 54 ...................................................................... 16

Changes to Figure 58 to Figure 61 ................................................ 17

Changes to Figure 62 and Figure 63 ............................................. 18

Changes to Figure 64 ...................................................................... 19

Changes to Figure 65 and Figure 66 ............................................. 20

Rev. G | Page 2 of 24

Changes to Figure 67 and Figure 68............................................. 21

Removed SPICE Model Section ................................................... 21

Updated Outline Dimensions ....................................................... 22

Changes to Ordering Guide .......................................................... 24

4/04—Rev. B to Rev. C

Changes to Ordering Guide ............................................................. 4

Changes to TPC 6 .............................................................................. 5

Changes to TPC 26 ............................................................................ 7

Updated Outline Dimensions ....................................................... 17

4/02—Rev. A to Rev. B

Added OP4177 ......................................................................... Global

Edits to Specifications ....................................................................... 2

Edits to Electrical Characteristics Headings .................................. 4

Edits to Ordering Guide ................................................................... 4

11/01—Rev. 0 to Rev. A

Edit to Features .................................................................................. 1

Edits to TPC 6 ................................................................................... 5

7/01—Revision 0: Initial Version

OP1177/OP2177/OP4177

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP1177 VOS 15 60 V
OP2177/OP4177 VOS 15 75 V
OP1177/OP2177 VOS −40°C < TA < +125°C 25 100 V

OP4177 VOS −40°C < TA < +125°C 25 120 V
Input Bias Current IB −40°C < TA < +125°C −2 +0.5 +2 nA
Input Offset Current IOS −40°C < TA < +125°C −1 +0.2 +1 nA
Input Voltage Range −3.5 +3.5 V
Common-Mode Rejection Ratio CMRR VCM = −3.5 V to +3.5 V 120 126 dB

−40°C < TA < +125°C 118 125 dB
Large Signal Voltage Gain AVO R
Offset Voltage Drift

OP1177/OP2177 ∆VOS/∆T −40°C < TA < +125°C 0.2 0.7 V/°C

OP4177 ∆VOS/∆T −40°C < TA < +125°C 0.3 0.9 V/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH I
Output Voltage Low VOL I
Output Current I

V

OUT

POWER SUPPLY

Power Supply Rejection Ratio

OP1177 PSRR VS = ±2.5 V to ±15 V 120 130 dB

−40°C < TA < +125°C 115 125 dB

OP2177/OP4177 PSRR VS = ±2.5 V to ±15 V 118 121 dB

−40°C < TA < +125°C 114 120 dB
Supply Current per Amplifier ISY V

−40°C < TA < +125°C 500 600 A

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 0.7 V/s
Gain Bandwidth Product GBP 1.3 MHz

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 V p-p
Voltage Noise Density en f = 1 kHz 7.9 8.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz

MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS DC 0.01 V/V
f = 100 kHz −120 dB

1

Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically

low estimates for parameters that can have both positive and negative values.

= 2 kΩ, VO = −3.5 V to +3.5 V 1000 2000 V/mV

L

= 1 mA, −40°C < TA < +125°C +4 +4.1 V

L

= 1 mA, −40°C < TA < +125°C −4.1 −4 V

L

< 1.2 V ±10 mA

DROPOUT

= 0 V 400 500 A

O

Rev. G | Page 3 of 24

OP1177/OP2177/OP4177

ELECTRICAL CHARACTERISTICS

VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP1177 VOS 15 60 V
OP2177/OP4177 VOS 15 75 V
OP1177/OP2177 VOS −40°C < TA < +125°C 25 100 V

OP4177 VOS −40°C < TA < +125°C 25 120 V
Input Bias Current IB −40°C < TA < +125°C −2 +0.5 +2 nA
Input Offset Current IOS −40°C < TA < +125°C −1 +0.2 +1 nA
Input Voltage Range −13.5 +13.5 V
Common-Mode Rejection Ratio CMRR VCM = −13.5 V to +13.5 V,

−40°C < TA < +125°C 120 125 dB
Large Signal Voltage Gain AVO R
Offset Voltage Drift

OP1177/OP2177 ∆VOS/∆T −40°C < TA < +125°C 0.2 0.7 V/°C

OP4177 ∆VOS/∆T −40°C < TA < +125°C 0.3 0.9 V/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH I
Output Voltage Low VOL I
Output Current I

V

OUT

Short-Circuit Current ISC ±25 mA

POWER SUPPLY

Power Supply Rejection Ratio

OP1177 PSRR VS = ±2.5 V to ±15 V 120 130 dB

−40°C < TA < +125°C 115 125 dB

OP2177/OP4177 PSRR VS = ±2.5 V to ±15 V 118 121 dB

−40°C < TA < +125°C 114 120 dB
Supply Current per Amplifier ISY V

−40°C < TA < +125°C 500 600 A

DYNAMIC PERFORMANCE

Slew Rate SR RL = 2 kΩ 0.7 V/s
Gain Bandwidth Product GBP 1.3 MHz

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 V p-p
Voltage Noise Density en f = 1 kHz 7.9 8.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz

MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS DC 0.01 V/V
f = 100 kHz −120 dB

1

Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically

low estimates for parameters that can have both positive and negative values.

= 2 kΩ, VO = –13.5 V to +13.5 V 1000 3000 V/mV

L

= 1 mA, −40°C < TA < +125°C +14 +14.1 V

L

= 1 mA, −40°C < TA < +125°C −14.1 −14 V

L

< 1.2 V ±10 mA

DROPOUT

= 0 V 400 500 A

O

Rev. G | Page 4 of 24

OP1177/OP2177/OP4177

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 36 V
Input Voltage VS− to VS+
Differential Input Voltage ±Supply Voltage
Storage Temperature Range

R, RM, and RU Packages −65°C to +150°C

Operating Temperature Range

OP1177/OP2177/OP4177 −40°C to +125°C

Junction Temperature Range

R, RM, and RU Packages −65°C to +150°C

Lead Temperature, Soldering (10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

8-Lead MSOP (RM-8)1 190 44 °C/W
8-Lead SOIC_N (R-8) 158 43 °C/W
14-Lead SOIC_N (R-14) 120 36 °C/W
14-Lead TSSOP (RU-14) 240 43 °C/W

1

MSOP is available in tape and reel only.

Unit

JC

ESD CAUTION

Rev. G | Page 5 of 24

OP1177/OP2177/OP4177

TYPICAL PERFORMANCE CHARACTERISTICS

50

VSY = ±15V

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

–30 –20 –10 0 10 20 30 40

–40

INPUT OFFSET VOLTAGE (µV)

Figure 7. Input Offset Voltage Distribution

02627-007

1.8
VSY = ±15V

= 25°C

T

A

1.6

1.4

1.2

1.0

0.8

0.6

ΔOUTPUT VOL TAGE (V)

0.4

0.2

0

0.001 10

SOURCE

SINK

0.01 0.1 1

LOAD CURRENT (mA)

Figure 10. Output Voltage to Supply Rail vs. Load Current

02627-010

90

80

70

60

50

40

30

NUMBER OF AMPLIFIERS

20

10

0

0.15 0.25 0.35 0.45 0. 55 0.65

0.05

INPUT OFFSET VOLTAGE DRIFT (µV/°C)

Figure 8. Input Offset Voltage Drift Distribution

VSY = ±15V

02627-008

140

VSY = ±15V

120

100

80

60

40

NUMBER OF AMPL IFIERS

20

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7

0

INPUT BIAS CURRENT (nA)

Figure 9. Input Bias Current Distribution

02627-009

3

2

1

0

–1

INPUT BI AS CURRE NT (nA)

–2

–3

–50 150

0 50 100

TEMPERATURE (°C)

Figure 11. Input Bias Current vs. Temperature

60

VSY = ±15V
C

= 0

L

50

R

=

∞

L

40

30

GAIN

20

10

OPEN-LOOP GAIN (dB)

0

–10

–20

100k 10M

1M

FREQUENCY (Hz)

Figure 12. Open-Loop Gain and Phase Shift vs. Frequency

PHASE

VSY = ±15V

270

225

180

135

90

45

0

–45

–90

2627-011

PHASE SHIFT (Degrees)

02627-012

Rev. G | Page 6 of 24

OP1177/OP2177/OP4177

V

120

100

80

60

AV = 100

40

AV = 10

20

0

AV = 1

–20

CLOSED-LOOP GAIN (dB)

–40

–60

–80

1k 100M

10k 100k 1M 10M

FREQUENCY (Hz)

VSY = ±15V
V

= 4mV p-p

IN

C

= 0

L

R

=

∞

L

Figure 13. Closed-Loop Gain vs. Frequency

02627-013

VOLTAGE (100mV/DIV)

GND

VSY = ±15V

= 1,000pF

C

L

= 2kΩ

R

L

= 100mV

V

IN

= 1

A

V

TIME (100µ s/DIV)

Figure 16. Small Signal Transient Response

02627-016

500

VSY = ±15V

450

= 50mV p-p

V

IN

400

350

300

250

200

150

OUTPUT IMPEDANCE (Ω)

100

50

0

100

1k 10k 100k 1M

FREQUENCY (Hz)

AV = 10

AV = 100

AV = 1

2627-014

Figure 14. Output Impedance vs. Frequency

VSY = ±15V
C

= 300pF

L

R

= 2kΩ

L

V

= 4V

IN

A

= 1

V

50

VSY = ±15V

45

= 2kΩ

R

L

= 100mV p-p

V

IN

40

35

30

25

20

15

10

SMALL SIG NAL OVERSHO OT (%)

5

0

1 10k

10 100 1k

CAPACITANCE (pF)

+OS

–OS

02627-017

Figure 17. Small Signal Overshoot vs. Load Capacitance

VSY = ±15V
R

= 10kΩ

L

A

= –100

–15V

V

V

= 200mV

IN

0V

OUTPUT

VOLTAGE (1V/DIV)

GND

TIME (100µs/ DIV)

Figure 15. Large Signal Transient Response

02627-015

+200m

0V

TIME (10µs/DIV)

Figure 18. Positive Overvoltage Recovery

INPUT

2627-018

Rev. G | Page 7 of 24

OP1177/OP2177/OP4177

–

V

√

OUTPUT

15V

0V

VSY = ±15V
R

= 10kΩ

L

A

= –100

V

V

= 200mV

IN

0V

VSY = ±15V

(0.2µV/DIV)

NOISE

V

200m

CMRR (dB)

PSRR (dB)

INPUT

TIME (4µs/DIV)

Figure 19. Negative Overvoltage Recovery

140

120

100

80

60

40

20

0

10 10M

100 1k 10k 100k 1M

FREQUENCY (Hz)

VSY = ±15V

Figure 20. CMRR vs. Frequency

140

120

100

80

60

+PSRR

VSY = ±15V

–PSRR

2627-019

TIME (1s/DIV)

2627-022

Figure 22. 0.1 Hz to 10 Hz Input Voltage Noise

18

VSY = ±15V

16

Hz)

14

12

10

8

6

VOLTAGE NOISE DENSITY (nV/

4

2

2627-020

50 100 150 2000 250

FREQUENCY ( Hz)

02627-023

Figure 23. Voltage Noise Density vs. Frequency

35

30

+I

25

20

15

SC

–I

SC

V

SY

= ±15V

40

20

0

10 10M

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 21. PSRR vs. Frequency

02627-021

10

SHORT-CIRCUIT CURRENT (mA)

5

0

–50 150

0 50 100

TEMPERATURE ( °C)

Figure 24. Short-Circuit Current vs. Temperature

2627-024

Rev. G | Page 8 of 24

OP1177/OP2177/OP4177

14.40

VSY = ±15V

14.35

14.30

14.25

14.20

14.15

14.10

OUTPUT VOLTAGE SWING (V)

14.05

14.00

+V

OH

0 50 100–50 150

TEMPERATURE (°C)

Figure 25. Output Voltage Swing vs. Temperature

–V

OL

02627-025

133

132

131

130

129

128

127

CMRR (dB)

126

125

124

123

0 50 100–50 150

TEMPERATURE (°C)

VSY = ±15V

2627-028

Figure 28. CMRR vs. Temperature

0.5

VSY = ±15V

0.4

0.3

0.2

0.1

0

–0.1

ΔOFFSET VOLTAGE (µV)

–0.2

–0.3

–0.4

–0.5

20 40 60 80 100 120

0 140

TIME FROM POWER SUPPLY TURN-ON (Sec)

02627-026

Figure 26. Warm-Up Drift

18

16

14

12

10

8

6

4

INPUT OFFSET VOLTAGE (µV)

2

0

0 50 100–50 150

TEMPERATURE (°C)

Figure 27. Input Offset Voltage vs. Temperature

VSY = ±15V

02627-027

133

132

131

130

129

128

PSRR (dB)

127

126

125

124

123

0 50 100–50 150

TEMPERATURE (°C)

Figure 29. PSRR vs. Temperature

VSY = ±15V

02627-029

50

VSY = ±5V

45

40

35

30

25

20

15

NUMBER OF AMPLIFIERS

10

5

0

–40 –30 –20 –10 0 10 20 30 40

Figure 30. Input Offset Voltage Distribution

INPUT OFFSET VOLTAGE (µV)

2627-030

Rev. G | Page 9 of 24

OP1177/OP2177/OP4177

1.4

VSY = ±5V

= 25°C

T

A

1.2

1.0

0.8

0.6

0.4

ΔOUTPUT VOLTAGE (V)

0.2

0

0.001 10

Figure 31. Output Voltage to Supply Rail vs. Load Current

SINK

SOURCE

0.01 0.1 1

LOAD CURRENT (mA)

500

VSY = ±5V

450

= 50mV p-p

V

IN

400

350

300

250

200

150

OUTPUT IMPEDANCE (Ω)

100

50

0

100 1M

02627-031

1k 10k 100k

AV = 100

AV = 10

FREQUENCY (Hz)

AV = 1

02627-034

Figure 34. Output Impedance vs. Frequency

60

50

40

30

GAIN

20

10

OPEN-LOOP GAIN (dB)

0

–10

–20

100k 10M

1M

FREQUENCY (Hz)

PHASE

Figure 32. Open-Loop Gain and Phase Shift vs. Frequency

120

100

80

60

AV = 100

40

AV = 10

20

0

AV = 1

–20

CLOSED-LOOP GAIN (dB)

–40

–60

–80

1k 100M

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 33. Closed-Loop Gain vs. Frequency

VSY = ±5V

= 0

C

L

=

∞

R

L

VSY = ±5V
V

= 4mV p-p

IN

= 0

C

L

=

∞

R

L

270

225

180

135

90

45

0

–45

–90

VSY = ±5V
C

= 300pF

L

R

= 2kΩ

L

V

= 1V

IN

A

= 1

V

VOLTAGE (1V/DIV)

PHASE SHIFT (Degrees)

2627-032

GND

TIME (100µ s/DIV)

02627-035

Figure 35. Large Signal Transient Response

VSY = ±5V
C

= 1,000pF

L

R

= 2kΩ

L

V

= 100mV

IN

A

= 1

V

VOLTAGE (50mV/DIV)

GND

2627-033

TIME (10µ s/DIV)

Figure 36. Small Signal Transient Response

02627-036

Rev. G | Page 10 of 24

OP1177/OP2177/OP4177

–

V

50

VSY = ±5V

45

= 2kΩ

R

L

= 100mV

V

IN

40

35

30

25

20

15

10

SMALL SIGNAL OVERSHOOT (%)

5

0

1 10k

10 100 1k

CAPACITANCE (p F)

+OS

–OS

Figure 37. Small Signal Overshoot vs. Load Capacitance

INPUT

GND

VOLTAGE (2V/DIV)

OUTPUT

02627-037

TIME (200µ s/DIV)

Figure 40. No Phase Reversal

VS = ±5V

= 1

A

V

= 10kΩ

R

L

02627-040

–15V

+200mV

200m

VSY = ±5V

= 10kΩ

R

L

= –100

A

V

= 200mV

V

IN

0V

0V

OUTPUT

INPUT

TIME (4µs/DIV)

Figure 38. Positive Overvoltage Recovery

5V

0V

0V

OUTPUT

INPUT

TIME (4µs/DIV)

Figure 39. Negative Overvoltage Recovery

VSY = ±5V

= 10kΩ

R

L

= –100

A

V

= 200mV

V

IN

140

120

100

80

60

CMRR (dB)

40

20

0

10 10M

02627-038

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 41. CMRR vs. Frequency

VSY = ±5V

02627-041

200

180

160

140

120

100

PSRR (dB)

80

60

40

20

0

10 10M

02627-039

100 1k 10k 100k 1M

FREQUENCY (Hz)

–PSRR

+PSRR

Figure 42. PSRR vs. Frequency

VSY = ±5V

02627-042

Rev. G | Page 11 of 24

OP1177/OP2177/OP4177

VSY = ±5V

4.40

VSY = ±5V

4.35

4.30

4.25

(0.2µV/DIV)

NOISE

V

TIME (1s/ DIV)

02627-043

Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise

18

VSY = ±5V

16

14

12

10

8

6

VOLTAGE NOISE DENSITY (nV/√Hz)

4

2

50 100 150 2000250

FREQUENCY (Hz)

02627-044

Figure 44. Voltage Noise Density vs. Frequency

4.20

4.15

4.10

OUTPUT VOLTAGE SWING (V)

4.05

4.00

Figure 46. Output Voltage Swing vs. Temperature

25

20

15

10

INPUT OFFSET VOLTAGE (µV)

5

0

Figure 47. Input Offset Voltage vs. Temperature

+V

OH

–V

OL

0 50 100–50 150

TEMPERATURE (°C)

= ±5V

V

SY

0 50 100–50 150

TEMPERATURE (°C)

02627-046

02627-047

35

30

+I

25

20

15

10

SHORT-CIRCUIT CURRENT (mA)

5

0

–50 150

Figure 45. Short-Circuit Current vs. Temperature

SC

–I

SC

0 50 100

TEMPERATURE ( °C)

V

= ±5V

SY

02627-045

Rev. G | Page 12 of 24

600

500

400

300

200

SUPPLY CURRENT (µA)

100

0

V

= ±15V

SY

VSY = ±5V

0 50 100–50 150

TEMPERATURE (°C)

02627-048

Figure 48. Supply Current vs. Temperature

OP1177/OP2177/OP4177

450

TA = 25°C

400

350

300

250

200

150

SUPPLY CURRENT (µA)

100

50

0

5101502025 30 35

SUPPLY VOLTAGE (V)

2627-049

Figure 49. Supply Current vs. Supply Voltage

0

–20

–40

–60

–80

–100

–120

CHANNEL SEPARATIO N (dB)

–140

–160

10 1M

100 1k 10k 100k

FREQUENCY (Hz)

Figure 50. Channel Separation vs. Frequency

02627-050

Rev. G | Page 13 of 24

OP1177/OP2177/OP4177

(

FUNCTIONAL DESCRIPTION

The OPx177 series is the fourth generation of Analog Devices,
Inc., industry-standard OP07 amplifier family. OPx177 is a high
precision, low noise operational amplifier with a combination of
extremely low offset voltage and very low input bias currents.
Unlike JFET amplifiers, the low bias and offset currents are
relatively insensitive to ambient temperatures, even up to 125°C.

Analog Devices proprietary process technology and linear design
expertise has produced a high voltage amplifier with superior
performance to the OP07, OP77, and OP177 in a tiny MSOP
8lead package. Despite its small size, the OPx177 offers numerous
improvements, including low wideband noise, very wide input
and output voltage range, lower input bias current, and complete
freedom from phase inversion.

OPx177 has a specified operating temperature range as wide as
any similar device in a plastic surface-mount package. This is
increasingly important as PCB and overall system sizes continue
to shrink, causing internal system temperatures to rise. Power
consumption is reduced by a factor of four from the OP177, and
bandwidth and slew rate increase by a factor of two. The low
power dissipation and very stable performance vs. temperature
also act to reduce warmup drift errors to insignificant levels.

For R

< 3.9 kΩ, en dominates and

S

e

≈ en

n,TOTAL

For 3.9 kΩ < R

< 412 kΩ, voltage noise of the amplifier, the

S

current noise of the amplifier translated through the source
resistor, and the thermal noise from the source resistor all
contribute to the total noise.

> 412 kΩ, the current noise dominates and

For R

S

e

≈ inRS

n,TOTAL

The total equivalent rms noise over a specific bandwidth is
expressed as

)

,=

TOTALnn

BWee

where BW is the bandwidth in hertz.

The preceding analysis is valid for frequencies larger than 50 Hz.
When considering lower frequencies, flicker noise (also known
as 1/f noise) must be taken into account.

For a reference on noise calculations, refer to the Band-Pass
KRC or Sallen-Key Filter section.

Open-loop gain linearity under heavy loads is superior to compet­itive parts, such as the OPA277, improving dc accuracy and
reducing distortion in circuits with high closed-loop gains.
Inputs are internally protected from overvoltage conditions
referenced to either supply rail.

Like any high performance amplifier, maximum performance is
achieved by following appropriate circuit and PCB guidelines.
The following sections provide practical advice on getting the
most out of the OPx177 under a variety of application conditions.

TOTAL NOISE-INCLUDING SOURCE RESISTORS

The low input current noise and input bias current of the OPx177
make it useful for circuits with substantial input source resistance.
Input offset voltage increases by less than 1 µV maximum per
500 Ω of source resistance.

The total noise density of the OPx177 is

,

TOTALn

2

where:

is the input voltage noise density.

e

n

is the input current noise density.

i

n

R

is the source resistance at the noninverting terminal.

S

k is Boltzmann’s constant (1.38 × 10
T is the ambient temperature in Kelvin (T = 273 + temperature

in degrees Celsius).

2

()

nn

kTRRiee 4

++=

SS

−23

J/K).

GAIN LINEARITY

Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range. This is especially true for circuits with high
closed-loop gains.

The OP1177 has excellent gain linearity even with heavy loads,
as shown in Figure 51. Compare its performance to the OPA277,
shown in Figure 52. Both devices are measured under identical
conditions, with R
distortion at lower voltages. Compared to the OPA277 at several
supply voltages and various loads, OP1177 performance far
exceeds that of its counterpart.

(10µV/DIV )

= 2 kΩ. The OP2177 (dual) has virtually no

L

VSY = ±15V

= 2kΩ

R

L

OP1177

(5V/DIV)

Figure 51. Gain Linearity

02627-051

Rev. G | Page 14 of 24

OP1177/OP2177/OP4177

(

)

VSY = ±15V

= 2kΩ

R

L

V

IN

V

OUT

VSY= 10V

= 1

A

V

(10µV/DIV )

OPA277

(5V/DIV)

Figure 52. Gain Linearity

2627-052

INPUT OVERVOLTAGE PROTECTION

When input voltages exceed the positive or negative supply
voltage, most amplifiers require external resistors to protect
them from damage.

The OPx177 has internal protective circuitry that allows voltages as
high as 2.5 V beyond the supplies to be applied at the input of
either terminal without any harmful effects.

Use an additional resistor in series with the inputs if the voltage
exceeds the supplies by more than 2.5 V. The value of the resistor
can be determined from the formula

−

VV

IN

S

R

500≤Ω+

S

mA5

With the OPx177 low input offset current of <1 nA maximum,
placing a 5 kΩ resistor in series with both inputs adds less than
5 µV to input offset voltage and has a negligible impact on the
overall noise performance of the circuit.

5 kΩ protects the inputs to more than 27 V beyond either supply.
Refer to the THD + Noise section for additional information on
noise vs. source resistance.

OUTPUT PHASE REVERSAL

Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this can
cause permanent damage to the amplifier. In feedback loops, it
can result in system lockups or equipment damage. The OPx177
is immune to phase reversal problems even at input voltages
beyond the supplies.

VOLTAGE (5V/DIV)

TIME (400µ s/DIV)

Figure 53. No Phase Reversal

02627-053

SETTLING TIME

Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in measure­ment and control circuits in which amplifiers buffer ADC inputs
or DAC outputs.

To minimize settling time in amplifier circuits, use proper
bypassing of power supplies and an appropriate choice of circuit
components. Resistors should be metal film types, because they
have less stray capacitance and inductance than their wire-wound
counterparts. Capacitors should be polystyrene or polycarbonate
types to minimize dielectric absorption.

The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OPx177
has a settling time of about 45 µs to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.

OVERLOAD RECOVERY TIME

Overload recovery is defined as the time it takes the output
voltage of an amplifier to recover from a saturated condition to
its linear response region. A common example is one in which
the output voltage demanded by the transfer function of the
circuit lies beyond the maximum output voltage capability of
the amplifier. A 10 V input applied to an amplifier in a closed­loop gain of 2 demands an output voltage of 20 V. This is beyond
the output voltage range of the OPx177 when operating at ±15 V
supplies and forces the output into saturation.

Recovery time is important in many applications, particularly
where the operational amplifier must amplify small signals in
the presence of large transient voltages.

Rev. G | Page 15 of 24

OP1177/OP2177/OP4177

2

V

T

R1

1kΩ

+

00m

–

100kΩ

2

OP1177

3

R2

V+

7

6

4

V–

10kΩ

V

OUT

02627-054

Figure 54. Test Circuit for Overload Recovery Time

Figure 18 shows the positive overload recovery time of the
OP1177. The output recovers in less than 4 µs after being
overdriven by more than 100%.

The negative overload recovery of the OP1177 is 1.4 µs, as seen
in Figure 19.

THD + NOISE

The OPx177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OPx177 a great choice for
high closed-loop gain precision circuits.

Figure 55 shows that the OPx177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.

0.1
VSY = ±15V

R

= 10kΩ

L

BW = 22kHz

Figure 56 is a scope shot of the output of the OPx177 in response
to a 400 mV pulse. The load capacitance is 2 nF. The circuit is
configured in positive unity gain, the worst-case condition for
stability.

As shown in Figure 58, placing an R-C network parallel to the
load capacitance (C
of C

without causing oscillation or excessive overshoot.

L

) allows the amplifier to drive higher values

L

There is no ringing, and overshoot is reduced from 27% to 5%
using the snubber network.

Optimum values for R

and CS are tabulated in Tab le 5 for several

S

capacitive loads, up to 200 nF. Values for other capacitive loads can
be determined experimentally.

Table 5. Optimum Values for Capacitive Loads

CL RS CS

10 nF 20 Ω 0.33 µF
50 nF 30 Ω 6.8 nF
200 nF 200 Ω 0.47 µF

VSY = ±5V

= 10kΩ

R

L

= 2nF

C

L

0.01

THD + N (%)

0.001

0.0001
20 6k

100 1k

FREQUENCY (Hz)

02627-055

Figure 55. THD + N vs. Frequency

CAPACITIVE LOAD DRIVE

OPx177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external
compensation, the OPx177 safely drives capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.

In this case, a snubber network is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the Resistor R

is not inside the feedback loop.

S

0

GND

VOLTAGE (200mV/DIV)

TIME (10µ s/DIV)

2627-056

Figure 56. Capacitive Load Drive Without Snubber

VSY = ±5V

= 10kΩ

R

L

= 200Ω

R

S

= 2nF

C

L

= 0.47µF

C

S

AGE (200mV/DI V)

GND

VOL

TIME (10µs/DIV)

Figure 57. Capacitive Load Drive with Snubber

2627-057

Rev. G | Page 16 of 24

OP1177/OP2177/OP4177

V+

7

2

400mV

OP1177

3

+
–

6

R

4

V–

S

C

S

V

OUT

C

L

2627-058

Figure 58. Snubber Network Configuration

Caution: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.

STRAY INPUT CAPACITANCE COMPENSATION

The effective input capacitance in an operational amplifier
circuit (C
differential capacitance between the input terminals, the internal
common-mode capacitance of each input to ground, and the
external capacitance including parasitic capacitance. In the
circuit in Figure 59, the closed-loop gain increases as the signal
frequency increases.

The transfer function of the circuit is

) consists of three components. These are the internal

t

R2

()

++ 1 1

R1

R1sC

t

C

f

R2R1

+

V1

–

C

t

2

OP1177

3

V+

7

6

4

V–

V

OUT

02627-060

Figure 60. Compensation Using Feedback Capacitor

REDUCING ELECTROMAGNETIC INTERFERENCE

A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.

In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the CMRR of the amplifier.

This is usually achieved by inserting a capacitor between the inputs
of the amplifier, as shown in Figure 61. However, this method can
also cause instability, depending on the value of capacitance.

R2R1

indicating a zero at

R1R2

s

+

=

=

1

()

π

CR2R1R2R1C

/ 2

tt

Depending on the value of R1 and R2, the cutoff frequency of
the closed-loop gain can be well below the crossover frequency.
In this case, the phase margin (Φ

) can be severely degraded,

M

resulting in excessive ringing or even oscillation.

A simple way to overcome this problem is to insert a capacitor
in the feedback path, as shown in Figure 60.

The resulting pole can be positioned to adjust the phase margin.

Setting C

= (R1/R2) Ct achieves a phase margin of 90°.

f

R2R1

+

V1

–

C

t

2

OP1177

3

V+

7

6

4

V–

V

OUT

Figure 59. Stray Input Capacitance

02627-059

+

V1

–

C

2

OP1177

3

V+

7

6

4

V–

V

OUT

02627-061

Figure 61. EMI Reduction

Placing a resistor in series with the capacitor (see Figure 62)
increases the dc loop gain and reduces the output error. Positioning
the breakpoint (introduced by R-C) below the secondary pole of
the operational amplifier improves the phase margin and,
therefore, stability.

R can be chosen independently of C for a specific phase margin
according to the formula

R

R2

()

jfa

2

R2

⎛
⎜
⎝

⎞

1

+−=

⎟

R1

⎠

where:

a is the open-loop gain of the amplifier.
f

is the frequency at which the phase of a = ΦM − 180°.

2

R2

R1

+

–

R

V1

C

Figure 62. Compensation Using Input R-C Network

2

OP1177

3

V+

7

6

4

V–

V

OUT

02627-062

Rev. G | Page 17 of 24

OP1177/OP2177/OP4177

V

V

V

V

+

+

δ

PROPER BOARD LAYOUT

The OPx177 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout.

To avoid leakage currents, the surface of the board should be
kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic
resistance on the board.

Keeping supply traces short and properly bypassing the power
supplies minimizes power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. It is recommended that
signal traces be kept at least 5 mm from supply lines to
minimize coupling.

A variation in temperature across the PCB can cause a mismatch in
the Seebeck voltages at solder joints and other points where dissi­milar metals are in contact, resulting in thermal voltage errors. To
minimize these thermocouple effects, orient resistors so heat
sources warm both ends equally. Input signal paths should contain
matching numbers and types of components, where possible to
match the number and type of thermocouple junctions. For
example, dummy components such as zero value resistors can
be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and
should be oriented in the same manner. Ensure leads are of equal
length so that thermal conduction is in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as
is practical.

The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.

In the single instrumentation amplifier (see Figure 63), where

R2

R4
R3

V −=

O

=

R1

R2

()

R1

VV

12

a mismatch between the ratio R2/R1 and R4/R3 causes the
common-mode rejection ratio to be reduced.

To better understand this effect, consider that, by definition,

A

DM

CMRR =

A

CM

where ADM is the differential gain and ACM is the common­mode gain.

CM

O

V

CM

1

()

and

2

VVVVVV +=−=

21

A and ==

DM

DIFF

O

V

DIFF

A

CM

21

For this circuit to act as a difference amplifier, its output must
be proportional to the differential input signal.

From Figure 63,

R2

⎡

⎛

1

⎜

R2

⎛

−=

V

⎜

O

R1

⎝

⎢

⎝

⎞

⎢

+

V

⎟
⎠

⎛

⎢

1

⎜

⎢

⎝

⎣

⎤

⎞

+

⎟

⎥

R1

⎠

⎥

V

21

R3

⎞

⎥

+

⎟

⎥

R4

⎠

⎦

Arranging terms and combining the previous equations yields

R4R2R3R2R4R1

2

CMRR

=

R2R3R4R1

22

−

(1)

The sensitivity of CMRR with respect to the R1 is obtained by
taking the derivative of CMRR, in Equation 1, with respect to R1.

δ

DIFFERENCE AMPLIFIERS

Difference amplifiers are used in high accuracy circuits to improve
the common-mode rejection ratio (CMRR).

R2

100kΩ

V+

R1

1

2

R3 = R1

R4R3R2

=

Figure 63. Difference Amplifier

2

3

R1

7

OP1177

4

V–

R4 = R1

6

V

OUT

02627-063

Rev. G | Page 18 of 24

CMRR

δ

CMRR

R1

δ

Assuming that

R1 ≈ R2 ≈ R3 ≈ R4 ≈ R

and

R(1 − δ) < R1, R2, R3, R4 < R(1 + δ)

the worst-case CMRR error arises when

R1 = R4 = R(1 + δ) and R2 = R3 = R(1 − δ)

δ

=

R1R1

−=
2

R1R4

⎛
⎜
⎝

1

()

2

R2R3

−δ

+

R2R3R1R4

22

R1R4

+

2

R2R3R2R4

⎞

−

⎟

R2R3R1R4

22

⎠

OP1177/OP2177/OP4177

V

Plugging these values into Equation 1 yields

MIN

1

δ≅2

CMRR

where δ is the tolerance of the resistors.

Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the operational amplifier).

Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. Alternatively, using 0.1% tolerance resistors
results in a common-mode rejection ratio of at least 54 dB
(assuming that the operational amplifier CMRR × 54 dB).

With the CMRR of OPx177 at 120 dB minimum, the resistor
match is the limiting factor in most circuits. A trimming resistor
can be used to further improve resistor matching and CMRR of
the difference amplifier circuit.

A HIGH ACCURACY THERMOCOUPLE AMPLIFIER

A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage

V

= α(TJ − TR)

TC

where:

is the temperature at the measurement of the hot junction.

T

J

is the temperature at the cold junction.

T

R

α is the Seebeck coefficient specific to the dissimilar metals used
in the thermocouple.

is the thermocouple voltage and becomes larger with

V

TC

increasing temperature.

CC

R9

2

OP1177

3

200kΩ

V+

7

4

V–

0.1µF

10µF

10µF

0.1µF

6

V

OUT

2.2µF

(–)

T

J

(+)

C1

D1

V

TC

ISOTHERMAL

ADR293

D1

TR

TR

BLOCK

R3

47kΩ

4.02kΩ

Cu

Cu

R7

80.6kΩ

10µF

R2

R1
50Ω

R8

1kΩ

100Ω

R6
50Ω

R5

10µF

R4
50Ω

Figure 64. Type K Thermocouple Amplifier Circuit

LOW POWER LINEARIZED RTD

A common application for a single element varying bridge is an
RTD thermometer amplifier, as shown in Figure 65. The excita­tion is delivered to the bridge by a 2.5 V reference applied at the
top of the bridge.

RTDs may have thermal resistance as high as 0.5°C to 0.8°C
per mW. To minimize errors due to resistor drift, the current
through each leg of the bridge must be kept low. In this circuit,
the amplifier supply current flows through the bridge. However,
at the OPx177 maximum supply current of 600 µA, the RTD
dissipates less than 0.1 mW of power, even at the highest resis­tance. Errors due to power dissipation in the bridge are kept
under 0.1°C.

02627-064

Maximum measurement accuracy requires cold junction compen­sation of the thermocouple. To perform the cold junction compen­sation, apply a copper wire short across the terminating junctions
(inside the isothermal block) simulating a 0°C point. Adjust the
output voltage to zero using the R5 trimming resistor, and remove
the copper wire.

The OPx177 is an ideal amplifier for thermocouple circuits
because it has a very low offset voltage, excellent PSRR and
CMRR, and low noise at low frequencies.

It can be used to create a thermocouple circuit with great
linearity. Resistor R1, Resistor R2, and Diode D1, shown in
Figure 64, are mounted in an isothermal block.

Calibration of the bridge is made at the minimum value of
temperature to be measured by adjusting R

until the output is zero.

P

To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint and apply a 500°C temperature to
the sensor or substitute the equivalent 500°C RTD resistance.

Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
better than ±0.5°C accuracy after adjustment.

Rev. G | Page 19 of 24

OP1177/OP2177/OP4177

V

F

T

F

0.1µ

+15

ADR421

4.12kΩ

4.12kΩ

100Ω

RTD

2

3

Figure 65. Low Power Linearized RTD Circuit

100Ω

100Ω 20Ω

V+

8

1/2

OP2177

4

V–

1

4.37kΩ

V

OUT

6

OP2177

5

1/2

500Ω

200Ω

49.9kΩ

V

OU

7

5kΩ

SINGLE OPERATIONAL AMPLIFIER BRIDGE

The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal condi­tioning. It is often more economical to use a single bridge
operational amplifier as opposed to an instrumentation amplifier.

In the circuit shown in Figure 66, the output voltage at the
operational amplifier is

⎡

⎛
⎜

⎢

R2

=

V

O

R

⎜

⎢

V

REF

⎜

R1

⎢

⎜

⎢
⎣

R

⎝

δ

R1

⎞

⎛

++

⎟

⎜

R2

⎠

⎝

⎤

⎞
⎟

⎥

⎟

⎥

⎟

⎥

()

1 1

δ+

⎟

⎥

⎠

⎦

where δ = ∆R/R is the fractional deviation of the RTD resistance
with respect to the bridge resistance due to the change in temper­ature at the RTD.

For δ << 1, the preceding expression becomes

⎞
⎟

δ

⎟

=

R1

⎟

++

⎟

R2

⎠

⎤

⎞

1

δ

V

⎟

REF

⎥

⎠

⎦

V

With V

⎛

R2

⎛

≅

⎜

O

R

⎝

R2

⎡

⎛

⎞

⎛

⎜

⎟

⎜

⎢

R

⎝

⎠

⎝

⎣

constant, the output voltage is linearly proportional

REF

⎜

⎞

⎜

V

⎟

REF

⎠

R1

+

R2

R1

⎜

1

⎜

R

⎝

R1

⎛

⎞

+

⎜

⎟

R2

⎝

⎠

to δ with a gain factor of

R1

R2

⎛

V

⎜

REF

R

⎝

2627-065

0.1µ

15V

ADR421

R1

⎡

⎞
⎟

⎢

⎠

⎣

⎞

⎛

+

1

⎟

⎜

R2

⎠

⎝

R

R(1+δ)

Figure 66. Single Bridge Amplifier

⎤

⎞

⎛

+

⎟

⎜

⎥

R2

⎠

⎝

⎦

R

R

2

OP1177

3

R

F

V+

7

4

V–

R

F

V

OUT

6

02627-066

Rev. G | Page 20 of 24

OP1177/OP2177/OP4177

REALIZATION OF ACTIVE FILTERS

BAND-PASS KRC OR SALLEN-KEY FILTER

The low offset voltage and the high CMRR of the OPx177 make
it an excellent choice for precision filters, such as the band-pass
KRC filter shown in Figure 67. This filter type offers the capability
to tune the gain and the cutoff frequency independently.

Because the common-mode voltage into the amplifier varies with
the input signal in the KRC filter circuit, a high CMRR is required
to minimize distortion. Also, the low offset voltage of the OPx177
allows a wider dynamic range when the circuit gain is chosen to
be high.

The circuit of Figure 67 consists of two stages. The first stage is
a simple high-pass filter where the corner frequency (f

1

C1C2R1R2π2

(2)

and

R1

(3)

KQ =

R2

where K is the dc gain.

Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to

1

R1R2C

π

2

The value of Q determines the peaking of the gain vs. frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.

Setting

1

yields minimum gain peaking and minimum

=

Q

2

ringing. Determine values for R1 and R2 by using Equation 3.

1

For

Q =

R1/R2 = 2 in the circuit example. Select R1 = 5 kΩ

,

2

and R2 = 10 kΩ for simplicity.

The second stage is a low-pass filter where the corner frequency
can be determined in a similar fashion. For R3 = R4 = R

C

) is

CHANNEL SEPARATION

Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to prevent
feedthrough of signals from one amplifier channel to the other.
As a result, the OP2177 has an impressive channel separation of
greater than −120 dB for frequencies up to 100 kHz and greater
than −115 dB for signals up to 1 MHz.

C3

330pF

680pF

2

1/2

1

V

OP2177

3

C4

OUT

C2

10nFC110nF

+

V1

20kΩ

–

R2

10kΩ

V+

8

6

1/2

OP2177

5

R1

4

V–

Figure 67. Two-Stage, Band-Pass KRC Filter

33kΩR433kΩ

7

R3

10kΩ

V+

50mV

8

6

1/2

OP2177

5

+

V1

–

Figure 68. Channel Separation Test Circuit

7

1

4

V–

1/2

OP2177

100Ω

2

3

2627-068

REFERENCES ON NOISE DYNAMICS AND FLICKER NOISE

S. Franco, Design with Operational Amplifiers and Analog
Integrated Circuits. McGraw-Hill, 1998.

Analog Devices, Inc., The Best of Analog Dialogue, 1967 to

1991. Analog Devices, Inc., 1991.

02627-067

C3

1

Q

==

C4

2

2

πR

1

and

C3

C4

f

C

Rev. G | Page 21 of 24

OP1177/OP2177/OP4177

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

14

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.31 (0.0122)

8

6.20 (0.2441)

5.80 (0.2283)

7

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 70. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

Rev. G | Page 22 of 24

060606-A

OP1177/OP2177/OP4177

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

3.20

3.00

2.80

8

5

5.15

4.90

4

0.40

0.25

4.65

1.10 MAX

15° MAX

6°
0°

0.23

0.09

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.55

0.40

100709-B

Figure 71. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]

8

6.40
BSC

7

1.20

0.20

MAX

0.09

SEATING
PLANE

8°
0°

(RU-14)

Dimensions shown in millimeters

0.75

0.60

0.45

061908-A

Rev. G | Page 23 of 24

OP1177/OP2177/OP4177

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

OP1177AR −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AZA
OP1177ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 AZA#
OP1177ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 AZA#
OP1177ARMZ-R71 −40°C to +125°C 8-Lead MSOP RM-8 AZA#
OP2177AR −40°C to +125°C 8-Lead SOIC_N R-8
OP2177AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
OP2177AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B2A
OP2177ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 B2A#
OP2177ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 B2A#
OP2177ARMZ-R71 −40°C to +125°C 8-Lead MSOP RM-8 B2A#
OP4177AR −40°C to +125°C 14-Lead SOIC_N R-14
OP4177AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
OP4177AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ1 −40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ-REEL1 −40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ-REEL71 −40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARU −40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14

1

Z = RoHS Compliant Part; # denotes Pb-free product may be top or bottom marked.

©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02627-0-11/09(G)

Rev. G | Page 24 of 24