Datasheet OM5202-FBP, OM5202-FBB Datasheet (Philips)

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

1

December 1994

DESCRIPTION

The OM5202 8-Bit ROMless Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The OM5202 has the same instruction set as
the 80C51.

See also:
– OM5232 — 8K bytes mask programmable ROM

– OM5234 — 16k bytes mask programmable ROM
– OM5238 — 32K bytes mask programmable ROM

This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The OM5202 contains no read-only program memory, a volatile
256 × 8 read/write data memory , four 8-bit I/O ports, two 16-bit
timer/event counters (identical to the timers of the 80C51), a
multi-source, two-priority-level, nested interrupt structure, UART and
on-chip oscillator and timing circuits. The OM5202 can be expanded
with standard TTL compatible memories and logic.

The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58%
of the instructions are executed in 0.75µs and 40% in 1.5µs. Multiply
and divide instructions require 3µs.

FEATURES

•80C51 central processing unit

•no internal ROM, externally up to 64k bytes

•256 × 8 RAM, expandable externally to 64k bytes

•Two standard 16-bit timer/counters

•Four 8-bit I/O ports

•Two open drain I/O’s (P1.6, P1.7)

•Full-duplex UART facilities

•Power control modes

– Idle mode
– Power-down mode

•Operating frequency range: 1.2 to 16 MHz

•Operating ambient temperature range: 0 to +70°C

PIN CONFIGURATIONS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

RST
RxD/P3.0
TxD/P3.1

INT0

/P3.2

INT1

/P3.3
T0/P3.4
T1/P3.5

P1.7

RD

/P3.7

XTAL2
XTAL1

V

SS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

EA

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

V

DD

DIP

SEE PAGE 2 FOR QFP PIN FUNCTIONS.

QFP

44

34

1

11

33

23

12 22

WR/P3.6

(SOT307–2)

PART NUMBER SELECTION

PHILIPS PART

ORDER NUMBER

PART MARKING

PACKAGE NUMBER

TEMPERATURE RANGE °C,

PACKAGE

FREQUENCY

MHz

OM5202/FBP SOT129 0 to +70, Plastic Dual In–line Package, 40 leads 1.2 to 16
OM5202/FBB SOT307–2 0 to +70, Plastic Quad Flat Pack, 44 leads 1.2 to 16

EQUIVALENT TYPES

Details are as specified by the data sheet for the equivalent type:

OM5202 = P80C652 without I

2

C function.
OM5232 = P83C652 without I2C function.
OM5234 = P83C654 without I

2

C function.
OM5238 = P83C528 without I2C function.

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

2

QFP PIN FUNCTIONS

QFP

44 34

1

11

33

23

12 22

(SOT307–2)

Pin Function Pin Function Pin Function

1 P1.5 16 V

SS1

31 P0.6/AD6
2 P1.6 17 NC 32 P0.5/AD5
3 P1.7 18 P2.0/A8 33 P0.4/AD4
4 RST 19 P2.1/A9 34 P0.3/AD3
5 P3.0/RxD 20 P2.2/A10 35 P0.2/AD2
6 V

SS4

21 P2.3/A11 36 P0.1/AD1
7 P3.1/TxD 22 P2.4/A12 37 P0.0/AD0
8 P3.2/INT0 23 P2.5/A13 38 V

DD

9 P3.3/INT1 24 P2.6/A14 39 V

SS3

10 P3.4/T0 25 P2.7/A15 40 P1.0
11 P3.5/T1 26 PSEN 41 P1.1
12 P3.6/WR 27 ALE 42 P1.2
13 P3.7/RD 28 V

SS2

43 P1.3

14 XTAL2 29 EA/V

PP

44 P1.4

15 XTAL1 30 P0.7/AD7

NOTE:

1. Due to EMC improvements, all V

SS

pins (6, 16, 28, 39)

must be connected to VSS.

LOGIC SYMBOL

PORT 0PORT 1PORT 2

PORT 3

ADDRESS AND

DATA BUS

ADDRESS BUS

VSSV

DD

ALTERNATE

FUNCTIONS

RST
XTAL1
XTAL2

ALE

PSEN

RxD

TxD
INT0
INT1

T0
T1

WR

RD

EA

64K BYTE BUS

EXPANSION

CONTRTOL

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

PROGRAMMABLE I/O

CPU

OSCILLATOR

AND

TIMING

DATA

MEMORY

(256 x 8 RAM)

TWO 16-BIT

TIMER/EVENT

COUNTERS

T0 T1

COUNTERS

XTAL2 XTAL1

FREQUENCY
REFERENCE

INTERNAL

INTERRUPTS

EXTERNAL

INTERRUPTS

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

SERIAL IN SERIAL OUT

SHARED WITH

PORT 3

INT0

INT1

BLOCK DIAGRAM

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

3

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP QFP TYPE NAME AND FUNCTION

V

SS

20 6, 16,

28, 39

I Ground: 0V reference. With the QFP package all VSS pins (V

SS1

to V

SS4

) must be connected.

V

DD

40 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0–0.7 39–32 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application, it uses
strong internal pull-ups when emitting 1s.

P1.0–P1.5 1–6 40–44,1I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which

are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I

IL

). Alternate functions

include:
P1.6 7 2 I/O open drain output
P1.7 8 3 I/O open drain output

P2.0–P2.7 21–28 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port

2 pins that are externally being pulled low will source current because of the internal pull-ups.

(See DC Electrical Characteristics: I

IL

). Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the
contents of the P2 special function register.

P3.0–P3.7 10–17 5,

7–13

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
3 pins that are externally being pulled low will source current because of the pull-ups. (See DC
Electrical Characteristics: I

IL

). Port 3 also serves the special features of the 80C51 family, as

listed below:

10 5 I RxD (P3.0): Serial input port
11 7 O TxD (P3.1): Serial output port
12 8 I INT0 (P3.2): External interrupt
13 9 I INT1 (P3.3): External interrupt
14 10 I T0 (P3.4): Timer 0 external input
15 11 I T1 (P3.5): Timer 1 external input
16 12 O WR (P3.6): External data memory write strobe
17 13 O RD (P3.7): External data memory read strobe

RST 9 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

An internal diffused resistor to V

SS

permits a power-on reset using only an external capacitor to

V

DD

.

ALE 30 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an access

to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency. Note that one ALE pulse is skipped during each access to external data memory.

PSEN 29 26 O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is

activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN

are skipped during each

access to external data memory. PSEN

is not activated (remains HIGH) during no fetches from

external program memory. PSEN

can sink/source 8 LSTTL inputs and can drive CMOS inputs

without external pull–ups.

EA 31 29 I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the

internal program memory ROM provided the Program Counter is less than 16384. If during a
RESET, EA

is held a TTL LOW level, the CPU executes out of external program memory. EA is

not allowed to float.

XTAL1 19 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2 18 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

4

Table 1. OM5202 Special Function Registers

SYMBOL DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB LSB

RESET
VALUE

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H
B* B Register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H
DPTR:

DPH
DPL

Data Pointer
(2 bytes)
Data Pointer High
Data Pointer Low

83H
82H

00H
00H

AF AE AD AC AB AA A9 A8

IE*# Interrupt Enable A8H EA ES1 ES0 ET1 EX1 ET0 EX0 0x000000B

BF BE BD BC BB BA B9 B8

IP*# Interrupt Priority B8H – PS1 PS0 PT1 PX1 PT0 PX0 xx000000B

87 86 85 84 83 82 81 80

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

97 96 95 94 93 92 91 90

P1*# Port 1 90H SDA SCL FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2* Port 2 A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TXD RXD FFH
PCON Power Control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

9F 9E 9D 9C 9B 9A 99 98
S0CON*# Serial 0 Port Control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H
S0BUF# Serial 0 Data Buffer 99H xxxxxxxxB

D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H

reserved (Note 1) DAH 00H

SP Stack Pointer 81H 07H

reserved (Note 1) DBH 00H

reserved (Note 1) D9H F8H

reserved (Note 1) D8H 00000000B

8F 8E 8D 8C 8B 8A 89 88
TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H
TH1 Timer High 1 8DH 00H
TH0 Timer High 0 8CH 00H
TL1 Timer Low 1 8BH 00H
TL0 Timer Low 0 8AH 00H
TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.

NOTE

1. Reserved for I

2

C; not supported in OM5202

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

5

ROM CODE EXTERNAL (OM5202)

The MOVC instructions are the only instructions that have access to
program code in the external program memory. The EA

input is

latched during RESET.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 2.

To drive the device from an external clock source, XT AL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-on, the voltage on
V

DD

and RST must come up at the same time for a proper start-up.

Idle Mode

In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 2 shows the state of the I/O ports during low current
operating modes.

Table 2. External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle External 1 1 Float Data Address Data
Power-down External 0 0 Float Data Data Data

Serial Control Register (S1CON) – See Table 3

CR2 ENS1 STA STO SI AA CR1 CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2 CR1 CR0

6MHz 12MHz 16MHz f

OSC

DIVIDED BY

0 0 0 23 47 62.5 256
0 0 1 27 54 71 224
0 1 0 31.25 62.5 83.3 192
0 1 1 37 75 100 160
1 0 0 6.25 12.5 17 960
1 0 1 50 100 133 120
1 1 0 100 200 267 60
1 1 1 0.24 < 62.5

0 to 255

0.49 < 62.5
0 to 254

0.65 < 55.6
0 to 253

96 × (256 – (reload value Timer 1))

reload value range Timer 1 (in mode 2)

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

6

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING UNIT

Storage temperature range –65 to +150 °C
Voltage on any other pin to V

SS

–0.5 to + 6.5 V
Input, output current on any single pin ±5 mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

SS

unless otherwise

noted.

40

30

20

10

0

0 4 8 12 16

(1) MAXIMUM OPERATING MODE: V

DD

= V

DDmax

(2) MAXIMUM IDLE MODE: VDD = V

DDmax

f

XTAL1

(MHz)

I

DD

(mA)

Figure 1. IDD vs. Frequency

(2)

(1)

These values are valid within the specified
frequency range.

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

7

DC ELECTRICAL CHARACTERISTICS

VSS = 0V, VDD = 5.0V ±10%. Operating temperature range 0 to 70°C.

TEST LIMITS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

IL

Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V

V

IL1

Input low voltage to EA –0.5 0.2VDD–0.3 V

V

IL2

Input low voltage to P1.6, P1.7 –0.5 0.3V

DD

V

V

IH

Input high voltage, except XTAL1, RST, P1.6, P1.7 0.2VDD+0.9 VDD+0.5 V

V

IH1

Input high voltage, XTAL1, RST 0.7V

DD

VDD+0.5 V

V

IH2

Input high voltage, P1.6, P1.7 0.7V

DD

6.0 V

V

OL

Output low voltage, ports 1, 2, 3, except P1.6, P1.7 IOL = 1.6mA

7), 8)

0.45 V

V

OL1

Output low voltage, port 0, ALE, PSEN IOL = 3.2mA

7), 8)

0.45 V

V

OL2

Output low voltage, P1.6, P1.7 IOL = 3.0mA 0.4 V

V

OH

Output high voltage, ports 1, 2, 3, ALE, PSEN

9)

IOH = –60µA 2.4 V
IOH = –25µA 0.75V

DD

V

IOH = –10µA 0.9V

DD

V

V

OH1

Output high voltage; port 0 in external bus mode IOH = –800µA 2.4 V

IOH = –300µA 0.75V

DD

V

IOH = –80µA 0.9V

DD

V

I

IL

Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7 VIN = 0.45V –50 µA

I

TL

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6, P1.7

See note 6) –650 µA

I

L1

Input leakage current, port 0, EA 0.45V < V

I

< V

DD

±10

µA

I

L2

Input leakage current, P1.6, P1.7 0V < V

I

< 6.0V

0V < V

DD

< 6.0V

±10

µA

I

DD

Power supply current: See note 1)

Active mode @ 16MHz

2), 10)

VDD=6.0V 26.5 mA

Idle mode @ 16MHz

3), 10)

6 mA

Power down mode

4), 5)

50 µA

R

RST

Internal reset pull-down resistor 50 150 kΩ

C

IO

Pin capacitance Freq.=1MHz 10 pF

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 9 through 11 for I

DD

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

r

= tf = 5ns;

VIL = VSS + 0.5V; VIH = V

DD

–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9.

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

r

= tf = 5ns; VIL = VSS + 0.5V;

V

IH

= V

DD

–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10.

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD;
EA

= RST = VSS. See Figure 11.

5. 2V

≤ V

PD

≤ VDDmax.

6. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V

IN

is approximately 2V .

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

OL

s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

8. Under steady state (non-transient) conditions, I

OL

must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum

I

OL

= 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the

test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

9. Capacitive loading on ports 0 and 2 may cause the V

OH

on ALE and PSEN to momentarily fall below the 0.9VDD specification when the

address bits are stabilizing.

10.I

DDMAX

for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I

DDMAX

is given in mA.

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

8

AC ELECTRICAL CHARACTERISTICS

1, 2

16MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

2 Oscillator frequency 1.2 16 MHz

t

LHLL

2 ALE pulse width 85 2t

CLCL

–40 ns

t

AVLL

2 Address valid to ALE low 8 t

CLCL

–55 ns

t

LLAX

2 Address hold after ALE low 28 t

CLCL

–35 ns

t

LLIV

2 ALE low to valid instruction in 150 4t

CLCL

–100 ns

t

LLPL

2 ALE low to PSEN low 23 t

CLCL

–40 ns

t

PLPH

2 PSEN pulse width 143 3t

CLCL

–45 ns

t

PLIV

2 PSEN low to valid instruction in 83 3t

CLCL

–105 ns

t

PXIX

2 Input instruction hold after PSEN 0 0 ns

t

PXIZ

2 Input instruction float after PSEN 38 t

CLCL

–25 ns

t

AVIV

2 Address to valid instruction in 208 5t

CLCL

–105 ns

t

PLAZ

2 PSEN low to address float 10 10 ns

Data Memory

t

RLRH

3, 4 RD pulse width 275 6t

CLCL

–100 ns

t

WLWH

3, 4 WR pulse width 275 6t

CLCL

–100 ns

t

RLDV

3, 4 RD low to valid data in 148 5t

CLCL

–165 ns

t

RHDX

3, 4 Data hold after RD 0 0 ns

t

RHDZ

3, 4 Data float after RD 55 2t

CLCL

–70 ns

t

LLDV

3, 4 ALE low to valid data in 350 8t

CLCL

–150 ns

t

AVDV

3, 4 Address to valid data in 398 9t

CLCL

–165 ns

t

LLWL

3, 4 ALE low to RD or WR low 138 238 3t

CLCL

–50 3t

CLCL

+50 ns

t

AVWL

3, 4 Address valid to WR low or RD low 120 4t

CLCL

–130 ns

t

QVWX

3, 4 Data valid to WR transition 3 t

CLCL

–60 ns

t

DW

3, 4 Data setup time before WR 288 7t

CLCL

–150 ns

t

WHQX

3, 4 Data hold after WR 13 t

CLCL

–50 ns

t

RLAZ

3, 4 RD low to address float 0 0 ns

t

WHLH

3, 4 RD or WR high to ALE high 23 103 t

CLCL

–40 t

CLCL

+40 ns

Shift Register

t

XLXL

5 Serial port clock cycle time

3

0.75 12t

CLCL

µs

t

QVXH

5 Output data setup to clock rising edge

3

492 10t

CLCL

–133 ns

t

XHQX

5 Output data hold after clock rising edge

3

80 2t

CLCL

–117 ns

t

XHDX

5 Input data hold after clock rising edge

3

0 0 ns

t

XHDV

5 Clock rising edge to input data valid

3

492 10t

CLCL

–133 ns

External Clock

t

CHCX

6 High time

3

20 20 t

CLCL –

t

CLCX

ns

t

CLCX

6 Low time

3

20 20 t

CLCL –

t

CHCX

ns

t

CLCH

6 Rise time

3

20 20 ns

t

CHCL

6 Fall time

3

20 20 ns

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF.

3. These values are characterized but not 100% production tested.

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

9

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN

Q – Output data
R – RD

signal
t – Time
V – Valid
W – WR

signal
X – No longer a valid logic level
Z – Float
Examples: t

AVLL

= Time for address valid

to ALE low.

t

LLPL

= Time for ALE low

to PSEN

low.

t

PXIZ

Figure 2. External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

A8–A15 A8–A15

A0–A7 A0–A7

t

AVLL

t

PXIX

t

LLAX

INSTR IN

t

PLIV

t

LHLL

t

PLPH

t

LLIV

t

PLAZ

t

LLPL

t

AVIV

ALE

PSEN

PORT 0

PORT 2

Figure 3. External Data Memory Read Cycle

RD

A0–A7

FROM RI OR DPL

DATA IN A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLDV

t

LLWL

t

RLRH

t

LLAX

t

RLAZ

t

AVLL

t

RHDX

t

RHDZ

t

AVWL

t

AVDV

t

RLDV

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

10

t

LLAX

ALE

PSEN

PORT 0

PORT 2

Figure 4. External Data Memory Write Cycle

WR

A0–A7

FROM RI OR DPL

DATA OUT A0–A7 FROM PCL INSTR IN

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

WHLH

t

LLWL

t

WLWH

t

AVLL

t

AVWL

t

QVWX

t

WHQX

t

DW

0 1 2 3 4 5 6 7 8

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

VALID VALID VALID VALID VALID VALID VALID VALID

SET TI

SET RI

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

Figure 5. Shift Register Mode Timing

V

IH1

0.8V

t

CHCL

t

CLCL

t

CLCH

t

CLCX

t

CHCX

Figure 6. External Clock Drive at XTAL1

Philips Semiconductors Product specification

OM5202ROMless 8-bit microcontroller

December 1994

11

VDD–0.5

0.45V

0.2V

DD

+0.9

0.2V

DD

–0.1

NOTE:

AC INPUTS DURING TESTING ARE DRIVEN AT V

DD

–0.5 FOR A LOGIC ’1’ AND

0.45V FOR A LOGIC ’0’. TIMING MEASUREMENTS ARE MADE AT V

IH

MIN FOR A

LOGIC ’1’ AND V

IL

MAX FOR A LOGIC ’0’.

Figure 7. AC Testing Input/Output

V

LOAD

V

LOAD

+0.1V

V

LOAD

–0.1V

V

OH

–0.1V

V

OL

+0.1V

NOTE:

FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A

100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > +
20mA.

Figure 8. Float Waveform

TIMING

REFERENCE

POINTS

V

DD

P0

EA

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

V

DD

I

DD

(NC)

CLOCK SIGNAL

Figure 9. IDD Test Condition, Active Mode

All other pins are disconnected

V

DD

P0

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

I

DD

(NC)

CLOCK SIGNAL

P1.6
P1.7

P1.6
P1.7

EA

*
*

*
*

Figure 10. I

DD

Test Condition, Idle Mode

All other pins are disconnected

V

DD

P0

RST

XTAL1

XTAL2

V

SS

V

DD

V

DD

I

DD

(NC)

Figure 11. IDD Test Condition, Power Down Mode

All other pins are disconnected. V

DD

= 2V to 5.5V

P1.6
P1.7

EA

*
*

NOTE:

* Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.