Datasheet OM4085T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

OM4085

Universal LCD driver for low
multiplex rates

Product specification
Supersedes data of 1996 Nov 14
File under Integrated Circuits, IC12

1997 Feb 25

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

FEATURES

• Single-chip LCD controller/driver

• Selectable backplane drive configuration: static

or 2, 3 or 4 backplane multiplexing

• Selectable display bias configuration: static,1⁄2or1⁄

• Internal LCD bias generation with voltage-follower

buffers

• 24 segment drives: up to twelve 8-segment numeric
characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements

• 24 × 4-bit RAM for display data storage

• Auto-incremented display data loading across device

subaddress boundaries

• Display memory bank switching in static and duplex
drive modes

• Versatile blinking modes

• LCD and logic supplies may be separated

• 2.0 to 6 V power supply range

• Low power consumption

• Power saving mode for extremely low power

consumption in battery-operated and telephone
applications

2

C-bus interface

• I

• TTL/CMOS compatible

• Compatible with any 4-bit, 8-bit or 16-bit

microprocessors/microcontrollers

• May be cascaded for large LCD applications
(up to 1536 segments possible)

• Cascadable with the 40 segment LCD driver PCF8576C

• Optimized pinning for single plane wiring in both single

and multiple OM4085 applications

• Space-saving 40 lead plasticvery small outline package
(VSO40; SOT158-1)

• No external components required (even in multiple
device applications)

• Manufactured in silicon gate CMOS process.

3

OM4085

GENERAL DESCRIPTION

The OM4085 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) having low
multiplex rates. It generates the drive signals for any static
or multiplexed LCD containing up to four backplanes and
up to 24 segments and can easily be cascaded for larger
LCD applications. The OM4085 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).

2

C-bus. Communication overheads

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

OM4085T VSO40 plastic very small outline package; 40 leads SOT158-1

1997 Feb 25 2

PACKAGE

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1997 Feb 25 3

handbook, full pagewidth

BLOCK DIAGRAM

Universal LCD driver for low multiplex

rates

Philips Semiconductors Product specification

V

DD

V

LCD

CLK

SYNC

OSC

V

SS

SCL

SDA

5

12

4
3

6

11

2
1

R

R

LCD BIAS

R

GENERATOR

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS

POWER-

RESET

LCD

VOLTAGE

SELECTOR

ON

2

I C-BUS

CONTROLLER

10

BP014BP215BP116BP3

13

BACKPLANE

OUTPUTS

OM4085

DISPLAY

CONTROLLER

COMMAND

DECODER

INPUT

BANK

SELECTOR

S0 to S23

17 to 40

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

DISPLAY

RAM

24 × 4 BITS

DATA

POINTER

OUTPUT

BANK

SELECTOR

SUB­ADDRESS
COUNTER

9

SA0

Fig.1 Block diagram.

A07A18A2

MGD866

OM4085

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PINNING

SYMBOL PIN DESCRIPTION

2

SDA 1 I
SCL 2 I
SYNC 3 cascade synchronization

CLK 4 external clock input/output
V

DD

5 positive supply voltage
OSC 6 oscillator input
A0 7

A2 9
SA0 10 I
V
V

SS
LCD

11 logic ground

12 LCD supply voltage
BP0 13
BP2 14
BP1 15
BP3 16
S0 to S23 17 to 40 LCD segment outputs

C-bus data input/output

2

C-bus clock input/output

input/output

2

I

C-bus subaddress inputsA1 8

2

C-bus slave address bit 0 input

LCD backplane outputs

handbook, halfpage

SDA
SCL

SYNC

CLK

V

DD

OSC

A0
A1

A2
SA0
V

SS

V

LCD
BP0

BP2
BP1
BP3

S0

S1

S2

S3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

OM4085

MGD865

OM4085

40

S23

39

S22

38

S21

37

S20

36

S19

35

S18

34

S17

33

S16

32

S15

31

S14

30

S13

29

S12

28

S11

27

S10

26

S9

25

S8

24

S7

23

S6

22

S5

21

S4

1997 Feb 25 4

Fig.2 Pin configuration.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

FUNCTIONAL DESCRIPTION

The OM4085 is a versatile peripheral device designed to
interface any microprocessor to a wide variety of LCDs.
It can directly drive any static or multiplexed LCD
containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the OM4085
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.

Table 1 Selection of display configurations

ACTIVE

BACKPLANE

OUTPUTS

4 96 12 digits + 12 indicator

3 72 9 digits + 9 indicator

2 48 6 digits + 6 indicator

1 24 3 digits + 3 indicator

NUMBER OF

SEGMENTS

7-SEGMENT NUMERIC

symbols

symbols

symbols

symbols

OM4085

All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
two-line I
OM4085. The internal oscillator is selected by tying OSC
(pin 6) to VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (VDD, VSSand V
to the LCD panel chosen for the application.

2

C-bus communication channel with the

14-SEGMENT

ALPHANUMERIC

6 characters + 12 indicator
symbols

4 characters + 16 indicator
symbols

3 characters + 6 indicator
symbols

1 character + 10 indicator
symbols

DOT MATRIX

96 dots (4 × 24)

72 dots (3 × 24)

48 dots (2 × 24)

24 dots

LCD

) and

handbook, full pagewidth

V

DD

V

SS

R ≤

2 C

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

t

rise

bus

SDA
SCL

OSC

V

DD

512

1 17 to 40

OM4085

2
6

78

A0 A1 A2 SA0

Fig.3 Typical system configuration.

1997 Feb 25 5

V

LCD

13 to 16

91011

V

24 segment drives

4 backplanes

SS

LCD PANEL

(up to 96

elements)

MBH951

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Power-on reset

At power-on the OM4085 resets to a defined starting
condition as follows:

1. All backplane outputs are set to V

2. All segment outputs are set to V

3. The drive mode ‘1 : 4 multiplex with1⁄3bias’ is selected

4. Blinking is switched off

5. Input and output bank selectors are reset (as defined
in Table 5)

6. The I2C-bus interface is initialized

7. The data pointer and the subaddress counter are
cleared.

2

Data transfers on the I

C-bus should be avoided for 1 ms

following power-on to allow completion of the reset action.

LCD bias generator

The full-scale LCD voltage (V
VDD− V

. The LCD voltage may be temperature

LCD

op

compensated externally through the V
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors connected
between VDD and V

. The centre resistor can be

LCD

switched out of circuit to provide a1⁄2bias voltage level for
the 1 : 2 multiplex configuration.

DD

DD

) is obtained from

supply to pin 12.

LCD

OM4085

LCD voltage selector

The LCD voltage selector coordinates the multiplexing of
the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing

− V

characteristics as functions of V

op=VDD

resulting discrimination ratios (D), are given in Table 2.
A practical value of V

is determined by equating V

op

with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is V

ratios of 1 : 3 and 1 : 4 with

≥ 3Vth. Multiplex drive

op

1

⁄2bias are possible but the

discrimination and hence the contrast ratios are smaller
( for 1 : 3 multiplex or for

3 1.732=

21 3⁄ 1.528=
1 : 4 multiplex). The advantage of these modes is a
reduction of the LCD full scale voltage V

6V

1

⁄2bias):

op(mrs)

1

⁄2bias):

off rms()

2.449V

==

op

=3V

off rms()

2.309V

off(rms)

1 : 3 multiplex (

V

op

1 : 4 multiplex (

Vop343⁄ V

==

These compare with V

op

off rms()

when1⁄3bias is used.

and the

LCD

off(rms)

as follows:

Table 2 Preferred LCD drive modes: summary of characteristics

LCD DRIVE MODE

LCD BIAS

CONFIGURATION

V

off rms()

----------------------­V

op

V

on rms()

---------------------- ­V

op

D

=

Static (1 BP) static (2 levels) 0 1 ∞
1 : 2 MUX (2 BP)

1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)

1

⁄2(3 levels)

1

⁄3(4 levels)

1

⁄3(4 levels)

1

⁄3(4 levels)

2 4 0.354=⁄

1

⁄3= 0.333

1

⁄3= 0.333

1

⁄3= 0.333

10 4⁄ 0.791=

53⁄ 0.745=

52.236=

52.236=

33 9⁄ 0.638= 33 3⁄ 1.915=

33⁄ 0.577= 31.732=

1997 Feb 25 6

V

on rms()

----------------------­V

off rms()

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

LCD drive mode waveforms

The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.4.

When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The OM4085 allows use of

1

⁄2or1⁄3bias in this mode as shown in Figs 5 and 6.

The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4
multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.

T

handbook, full pagewidth

S

BP0

S

n + 1

V

DD

V

LCD

V

DD

n

V

LCD

V

DD

V

LCD

(a) waveforms at driver

frame

LCD segments

state 1

(on)

state 2

(off)

V

op

state 1

state 2 0

−V

−V

0

op

V

op

op

(b) resultant waveforms

at LCD segment

At any instant (t):
V

(t) = V

state 1

V

= V

on(rms)

V

(t) = V

state 2

V

= 0 V

off(rms)

Fig.4 Static drive mode waveforms: Vop=VDD− V

(t) − V

S

n

op

S

n + 1

(t) − V

LCD

BP0

MGG392

.

(t)

BP0

(t)

1997 Feb 25 7

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

V

DD

(V

+ V

BP0

BP1

S

n

S

n + 1

state 1

DD

V

LCD

V

DD

(V

DD

V

LCD

V

DD

V

LCD

V

DD

V

LCD

V

op

Vop/2

−Vop/2

−V

op

V

op

Vop/2

)/2

LCD

+ V

)/2

LCD

(a) waveforms at driver

0

T

frame

LCD segments

state 1
state 2

At any instant (t):
V

(t) = V

state 1

V

=

on(rms)

V

(t) = V

state 2

V

=

off(rms)

(t) − V

S

n

V

op

√10 = 0.791V

4

(t) − V

S

n

V

op

√2 = 0.354V

4

BP0

BP1

OM4085

(t)

op

(t)

op

−Vop/2

−V

op

0

(b) resultant waveforms

at LCD segment

state 2

Fig.5 Waveforms for 1 : 2 multiplex drive mode with1⁄2bias: Vop=VDD− V

1997 Feb 25 8

MGG394

LCD

.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

andbook, full pagewidth

BP0

BP1

S

n + 1

state 1 0

state 2 0

V

DD

V

− Vop/3

DD

V

− 2Vop/3

DD

V

LCD

V

DD

V

− Vop/3

DD

V

− 2Vop/3

DD

V

LCD

V

DD

V

− Vop/3

S

DD

n

V

− 2Vop/3

DD

V

LCD

V

DD

V

− Vop/3

DD

V

− 2Vop/3

DD

V

LCD

V

op
2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

V

op
2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

T

frame

LCD segments

state 1
state 2

At any instant (t):
V

(t) = V

state 1

V

on(rms)

V

state 2

V

off(rms)

V

=

(t) = V

V

=

(t) − V

S

n

op

√5 = 0.745V

3

(t) − V

S

n

op

= 0.333V

3

BP0

BP1

MGG393

OM4085

(t)

op

(t)

op

Fig.6 Waveforms for 1 : 2 multiplex drive mode with1⁄3bias: Vop=VDD− V

1997 Feb 25 9

LCD

.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

V

DD

V

BP0

BP1

BP2

S

S

n + 1

S

n + 2

state 1 0

state 2 0

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

n

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

op

2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

V

op
2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

T

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

frame

LCD segments

state 1
state 2

At any instant (t):
V

state 1

V

on(rms)

V

state 2

V

off(rms)

(t) = V

V

=

(t) = V

=

(t) − V

S

n

op

√33 = 0.638V

9

(t) − V

S

n

V

op

= 0.333V

3

BP0

BP1

MGG395

OM4085

(t)

op

(t)

op

Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop=VDD− V

1997 Feb 25 10

LCD

.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

V

DD

V

− Vop/3

BP0

BP1

BP2

BP3

S

n

S

n + 1

Sn + 2

S

n + 3

state 1 0

state 2 0

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

DD

V

DD

V

DD

V

LCD

V

op

2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

V

op
2Vop/3
Vop/3

−Vop/3

−2Vop/3

−V

op

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

− Vop/3

− 2Vop/3

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

T

frame

LCD segments

state 1
state 2

At any instant (t):
V

state 1

V

on(rms)

V

state 2

V

off(rms)

(t) = V

V

=

(t) = V

V

=

(t) − V

S

n

op

√3 = 0.577V

3

(t) − V

S

n

op

= 0.333V

3

MGG396

OM4085

(t)

BP0

op

(t)

BP1

op

Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop=VDD− V

1997 Feb 25 11

LCD.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Oscillator

The internal logic and the LCD drive signals of the
OM4085 or PCF8576 are timed either by the built-in
oscillator or from an external clock.

The clock frequency (f
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, f
be above 125 kHz.

A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.

Internal clock

When the internal oscillator is used, OSC (pin 6) should be
tied to V

. In this case, the output from CLK (pin 4)

SS

provides the clock signal for cascaded OM4085s and
PCF8576s in the system.

External clock

The condition for external clock is made by tying OSC
(pin 6) to V

; CLK (pin 4) then becomes the external

DD

clock input.

Timing

The timing of the OM4085 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the OM4085s in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (Table 3). The frame
frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when
external clock is used.

Table 3 LCD frame frequencies

OM4085 MODE f

Normal mode f
Power saving mode f

) determines the LCD frame

CLK

should be chosen to

CLK

frame

/2880 64

CLK

/480 64

CLK

NOMINAL
f

frame

(Hz)

OM4085

The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus. When a
device is unable to ‘digest’ a display data byte before the
next one arrives, it holds the SCL line LOW until the first
display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.

Display latch

The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.

Shift register

The shift register serves to transfer display information
from the display RAM to the display latch while previous
data are displayed.

Segment outputs

The LCD drive section includes 24 segment outputs
S0 to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with the data resident in the display latch.
When less than 24 segment outputs are required the
unused segment outputs should be left open-circuit.

Backplane outputs

The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open. In the 1 : 3 multiplex drive mode BP3
carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.

The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.

1997 Feb 25 12

Display RAM

The display RAM is a static 24 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the ‘on’
state of the corresponding LCD segment; similarly, a
logic 0 indicates the ‘off’ state.

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs.
The first RAM column corresponds to the 24 segments
operated with respect to backplane BP0 (see Fig.9).
In multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.

When display data are transmitted to the OM4085 the
display bytes received are stored in the display RAM
according to the selected LCD drive mode. To illustrate the
filling order, an example of a 7-segment numeric display
showing all drive modes is given in Fig.10; the RAM filling
organization depicted applies equally to other LCD types.

With reference to Fig.10, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.

Data pointer

The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM.

OM4085

The sequence commences with the initialization of the
data pointer by the LOAD DATA POINTER command.
Following this, an arriving data byte is stored starting at the
display RAM address indicated by the data pointer thereby
observing the filling order shown in Fig.10. The data
pointer is automatically incremented according to the LCD
configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode), by
three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex
drive mode).

Subaddress counter

The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should
be tied to V
defined by the DEVICE SELECT command. If the contents
of the subaddress counter and the hardware subaddress
do not agree then data storage is inhibited but the data
pointer is incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.

The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are being sent to the display RAM,
automatic wrap-over to the next OM4085 occurs when the
last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character.

or VDD. The subaddress counter value is

SS

handbook, full pagewidth

display RAM bits

(columns) /

backplane outputs

(BP)

0

0
1
2
3

display RAM addresses (rows)/segment outputs (S)

1234 1920212223

MGG389

Fig.9 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,

and between bits in a RAM word and backplane outputs.

1997 Feb 25 13

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1997 Feb 25 14

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

drive mode

static

1 : 2

multiplex

1 : 3

multiplex

1 : 4

multiplex

LCD segments LCD backplanes display RAM filling order transmitted display byte

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

S

n

a

2

3

4

5

6

S

n

1

2

3

1

2

S

n

1

b

f

g

e

c

d

a

b

f

g

e

c

d

a

b

f

g

e

c

d

a

b

f

g

e

c

d

BP0

S

1

n

S

n

S

7

n

DP

BP0

bit/
BP

bit/

BP1

DP

BP0

S

n

BP

bit/
BP

DP

BP1

BP0

BP2

BP2

bit/
BP

BP1

DP

BP3

n1

n

c

0

x

1

x

2

x

3

n

a

0

b

1

x

2

x

3

n

b

0

DP

1

c

2

x

3

n

a

0

c

1

b

2

DP

3

n2 n3 n4 n5 n6 n7

b

a

f

g

e

x

x

x

x
x
x

n1

f
g
x
x

n1

a
d
g
x

x

x

x

x

n2 n3

e

d

c

DP

x

x

x

x

n2

f
e
x
x

x

x

x

x

x

n1

f
e
g
d

d

DP

x

x

x

x

x

x

MSB LSB

cbaf gedDP

MSB LSB

abf gecdDP

MSB LSB

bDPcadgf e

MSB LSB

acbDPf egd

MBE534

Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus (X = data bit

unchanged).

handbook, full pagewidth

OM4085

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Output bank selector

This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 then 1
are selected and, in the static mode, bit 0 is selected.

The OM4085 includes a RAM bank switching feature in the
static and 1 : 2 multiplex drive modes. In the static drive
mode, the BANK SELECT command may request the
contents of bit 2 to be selected for display instead of bit 0
contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.

OM4085

Blinker

The display blinking capabilities of the OM4085 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.

An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and 1 : 2
LCD drive modes and can be implemented without any
communication overheads. By means of the output bank
selector, the displayed RAM banks are exchanged with
alternate RAM banks at the blinking frequency. This mode
can also be specified by the BLINK command.

In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.

Input bank selector

The input bank selector loads display data into the display
RAM according to the selected LCD drive configuration.
Display data can be loaded in bit 2 in static drive mode or
in bits2and3in1:2 drive mode by using the BANK
SELECT command. The input bank selector functions
independently of the output bank selector.

Table 4 Blinking frequencies

BLINKING MODE

NORMAL OPERATING

MODE RATIO

POWER-SAVING

MODE RATIO

Off −− blinking off
2Hz f
1Hz f

0.5 Hz f

/92160 f

CLK

/184320 f

CLK

/368640 f

CLK

If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.

NOMINAL BLINKING FREQUENCY

f

(Hz)

blink

/15360 2

CLK

/30720 1

CLK

/61440 0.5

CLK

1997 Feb 25 15

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

I2C-BUS DESCRIPTION

The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).

OM4085

Acknowledge

The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.

System configuration

A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.

SDA

SCL

data line

stable;

data valid

Fig.11 Bit transfer.

change

of data

allowed

MBA607

1997 Feb 25 16

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

SDA

SCL

S

START condition

Fig.12 Definition of START and STOP conditions.

P

STOP condition

OM4085

SDA

SCL

MBA608

SDA
SCL

handbook, full pagewidth

BY TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

SCL FROM

MASTER

DATA OUTPUT

DATA OUTPUT

BY RECEIVER

START

condition

S

SLAVE

RECEIVER

TRANSMITTER /

RECEIVER

Fig.13 System configuration.

1

2

SLAVE

MASTER

TRANSMITTER

clock pulse for

acknowledgement

8

MBA606 - 1

TRANSMITTER /

RECEIVER

9

MASTER

MBA605

Fig.14 Acknowledgement on the I2C-bus.

1997 Feb 25 17

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

OM4085 I2C-bus controller

The OM4085 acts as an I2C-bus slave receiver. It does not
initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the OM4085
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.

In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to VSS which defines the hardware subaddress 0.
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to VSS or VDD according to a binary
coding scheme such that no two devices with a common
I2C-bus slave address have the same hardware
subaddress.

In the power-saving mode it is possible that the OM4085 is
not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the OM4085 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.

Input filters

To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.

2

I

C-bus protocol

Two I2C-bus slave addresses (0111110 and 0111111) are
reserved for OM4085. The least-significant bit of the slave
address that a OM4085 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
OM4085 can be distinguished on the same I2C-bus which
allows:

1. Up to 16 OM4085s on the same I2C-bus for very large
LCD applications

2. The use of two types of LCD multiplex on the same
I2C-bus.

OM4085

2

The I

C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two OM4085 slave
addresses available. All OM4085s with the corresponding
SA0 level acknowledge in parallel the slave address but all
OM4085s with the alternative SA0 level ignore the whole
I2C-bus transfer. After acknowledgement, one or more
command bytes (m) follow which define the status of the
addressed OM4085s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed OM4085s on the bus.

After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended OM4085 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed OM4085. After the last display
byte, the I2C-bus master issues a STOP condition (P).

Command decoder

The command decoder identifies command bytes that
arrive on the I
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.

The five commands available to the OM4085 are defined
in Table 5.

2

C-bus. All available commands carry a

1997 Feb 25 18

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

slave address

S

011111 0AC

S

A

0

/RW

acknowledge by

all addressed

m ≥1 byte(s) n ≥ 0 byte(s)1 byte

Fig.15 I2C-bus protocol.

OM4085s

COMMAND

OM4085

acknowledge

by A0, A1 and A2

selected

OM4085 only

A

MBH953

ADISPLAY DATA

P

update data pointers

and if necessary,

subaddress counter

0 = last command
1 = commands continue

MSB LSB

C

REST OF OPCODE

MGG388

Fig.16 General format of command byte.

1997 Feb 25 19

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

Table 5 Definition of OM4085 commands

COMMAND/OPCODE OPTIONS DESCRIPTION

Mode set

C 1 0 LP E B M1 M0 see Table 6 defines LCD drive mode

see Table 7 defines LCD bias configuration
see Table 8 defines display status; the possibility to disable

the display allows implementation of blinking
under external control

see Table 9 defines power dissipation mode

Load data pointer

C 0 0 P4 P3 P2 P1 P0 see Table 10 five bits of immediate data, bits P4 to P0, are

transferred to the data pointer to define one of
twenty-four display RAM addresses

Device select

C1100A2A1A0 see Table 11 three bits of immediate data, bits A0 to A2, are

transferred to the subaddress counter to define
one of eight hardware subaddresses

Bank select

C11110IO see T able12 defines input bank selection (storage of arriving

display data)

see Table 13 defines output bank selection (retrieval of LCD

display data)
the BANK SELECT command has no effect in

1 : 3 and 1 : 4 multiplex drive modes

Blink

C1110ABF1BF0 see Table 14 defines the blinking frequency

see Table 15 selects the blinking mode; normal operation

with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes

Table 6 LCD drive mode

LCD DRIVE MODE BIT M1 BIT M0

Static (1 BP) 0 1
1 : 2 MUX (2 BP) 1 0
1 : 3 MUX (3 BP) 1 1
1 : 4 MUX (4 BP) 0 0

1997 Feb 25 20

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 7 LCD bias configuration

LCD BIAS BIT B

1

⁄3bias 0

1

⁄2bias 1

Table 8 Display status

DISPLAY STATUS BIT E

Disabled (blank) 0
Enabled 1

Table 9 Power dissipation mode

MODE BIT LP

Normal mode 0
Power-saving mode 1

Table 10 Load data pointer

BITS P4 P3 P2 P1 P0

5-bit binary value of 0 to 23

Table 11 Device select

BITS A0 A1 A2

3-bit binary value of 0 to 7

Table 12 Input bank selection

STATIC 1 : 2 MUX BIT 1

RAM bit 0 RAM bits 0, 1 0
RAM bit 2 RAM bits 2, 3 1

Table 13 Output bank selection

STATIC 1 : 2 MUX BIT 0

RAM bit 0 RAM bits 0, 1 0
RAM bit 2 RAM bits 2, 3 1

Table 14 Blinking frequency

BLINK

FREQUENCY

Off 0 0
2Hz 0 1
1Hz 1 0

0.5 Hz 1 1

BIT BF1 BIT BF0

OM4085

Table 15 Blink mode selection

BLINK MODE BIT A

Normal blinking 0
Alternation blinking 1

Display controller

The display controller executes the commands identified
by the command decoder. It contains the status registers
of the OM4085 and coordinates their effects.

The controller is also responsible for loading display data
into the display RAM as required by the filling order.

Cascaded operation

In large display configurations, up to 16 OM4085s can be
distinguished on the same I
hardware subaddress (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). It is also
possible to cascade up to 16 OM4085s. When cascaded,
several OM4085s are synchronized so that they can share
the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other OM4085s of the cascade contribute
additional segment outputs but their backplane outputs are
left open-circuit (Fig.17).

The SYNC line is provided to maintain the correct
synchronization between all cascaded OM4085s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when OM4085s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A OM4085 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be
restored by the first OM4085 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
OM4085s and PCF8576s is possible, giving cost effective
LCD applications.

2

C-bus by using the 3-bit

1997 Feb 25 21

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

SDA
SCL

SYNC

CLK
OSC

V

DDVLCD

512

1
2
3
4

6

7 8 9 10 11

A0 A1 A2 SA0

17 to 40

OM4085

13 to 16

24 segment drives

BP0 to BP3
(open-circuit)

V

SS

OM4085

LCD PANEL

(up to 1536

elements)

V

LCD
V

DD

V

SS

R ≤

2 C

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

t

rise

bus

SDA

SCL

SYNC

CLK

OSC

V

DD

512

1
2
3

OM4085

4
6

78

91011

A0 A1 A2 SA0

V

LCD

17 to 40

13 to 16

24 segment drives

4 backplanes

BP0 to BP3

V

SS

MBH950

Fig.17 Cascaded OM4085 configuration.

1997 Feb 25 22

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

BP0

SYNC

BP1

(1/2 bias)

BP1

(1/3 bias)

SYNC

T=

framefframe

(a) static drive mode.

(b) 1 : 2 multiplex drive mode.

OM4085

1

BP2

SYNC

(c) 1 : 3 multiplex drive mode.

BP3

SYNC

(d) 1 : 4 multiplex drive mode.

Fig.18 Synchronization of the cascade for the various OM4085 drive modes.

For single plane wiring of OM4085s, see Chapter “Application information”.

MBE535

1997 Feb 25 23

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

LCD

V

I

V

O

I

I

I

O

I

, ISS, I

DD

P

tot

P

O

T

stg

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
advised to take handling precautions appropriate to handling MOS devices (see

supply voltage −0.5 +7 V
LCD supply voltage VDD− 7V

DD

input voltage (SCL, SDA, A0 to A2, OSC, CLK, SYNC and SA0) VSS− 0.5 VDD+ 0.5 V
output voltage (S0 to S23 and BP0 to BP3) V

− 0.5 VDD+ 0.5 V

LCD

DC input current −±20 mA
DC output current −±25 mA

LCDVDD

, VSSor V

current −±50 mA

LCD

power dissipation per package − 400 mW
power dissipation per output − 100 mW
storage temperature −65 +150 °C

“Handling MOS devices”

V

).

1997 Feb 25 24

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

DC CHARACTERISTICS

V

=0V; VDD= 2.0 to 6 V; V

SS

LCD=VDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

V

LCD

I

DD

operating supply voltage 2.0 − 6V
LCD supply voltage VDD− 6 − VDD− 2.0 V
operating supply current

(normal mode)

I

LP

power saving mode supply current VDD= 3.5 V; V

Logic

V

IL

V

IH

V

OL

V

OH

I

OL1

LOW level input voltage V
HIGH level input voltage 0.7V
LOW level output voltage IO=0mA −−0.05 V
HIGH level output voltage IO=0mA VDD− 0.05 −− V
LOW level output current

(CLK and SYNC)

I

OH

I

OL2

HIGH level output current (CLK) VOH=4V; VDD=5V −−−1mA
LOW level output current

(SDA and SCL)

I

LI

leakage current
(SA0, CLK, OSC, A0, A1, A2, SCL
and SDA)

I

pd

pull-down current
(A0, A1, A2 and OSC)

R

puSYNC

V

ref

t

sw

C

i

pull-up resistor (SYNC) 15 25 60 kΩ
power-on reset level note 2 − 1.3 2 V
tolerable spike width on bus −−100 ns
input capacitance note 3 −−7pF

LCD outputs

V

BP

DC voltage component
(BP0 to BP3)

V

S

Z

BP

Z

S

DC voltage component (S0 to S23) CS=5nF −±20 − mV
output impedance (BP0 to BP3) V
output impedance (S0 to S23) V

− 2.0 to VDD− 6 V; T

f

= 200 kHz; note 1 − 30 90 µA

CLK

f

= 35 kHz; A0,

CLK

A1 and A2 tied to VSS;
note 1

VOL=1V; VDD=5V 1 −− mA

VOL= 0.4 V; VDD=5V 3 −− mA

VI=VSSor V

VI=1V; VDD= 5 V 15 50 150 µA

CBP=35nF −±20 − mV

LCD=VDD
LCD=VDD

= −40 to +85 °C; unless otherwise specified.

amb

DD

LCD

=0V;

− 15 40 µA

SS

DD

− 0.3V

− V

DD

DD

V
V

−−±1µA

− 5 V; note 4 − 15 kΩ

−5 V; note 4 − 37 kΩ

Notes

1. Outputs open; inputs at V

2. Resets all logic when VDD<V

or VDD; external clock with 50% duty factor; I2C-bus inactive.

SS

.

ref

3. Periodically sampled, not 100% tested.

4. Outputs measured one at a time.

1997 Feb 25 25

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

AC CHARACTERISTICS

V

=0V; VDD= 2.0 to 6 V; V

SS

LCD=VDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

CLK

f

CLKLP

oscillator frequency (normal mode) VDD= 5 V; note 2 125 200 315 kHz
oscillator frequency (power saving

mode)

t

CLKH

t

CLKL

t

PSYNC

t

SYNCL

t

PLCD

2

C-bus

I

t

BUF

t

HD; STA

t

LOW

t

HIGH

t

SU; STA

CLK HIGH time 1 −−µs
CLK LOW time 1 −−µs
SYNC propagation delay −−400 ns
SYNC LOW time 1 −−µs
driver delays with test loads V

bus free time 4.7 −−µs
START condition hold time 4 −−µs
SCL LOW time 4.7 −−µs
SCL HIGH time 4 −−µs
START condition set-up time

(repeated start code only)

t

HD; DAT

t

SU; DAT

t

r

t

f

t

SU; STO

data hold time 0 −−µs
data set-up time 250 −−ns
rise time −−1µs
fall time −−300 ns
STOP condition set-up time 4.7 −−µs

− 2.0 to VDD− 6 V; T

VDD= 3.5 V 21 31 48 kHz

LCD=VDD

= −40 to +85 °C; unless otherwise specified; note 1.

amb

− 5V −−30 µs

4.7 −−µs

Notes

1. All timing values referred to V

2. At f

handbook, full pagewidth

< 125 kHz, I2C-bus maximum transmission speed is derated.

CLK

BP0 to BP3

(pins 13 to 16)

and VIL levels with an input voltage swing of VSS to VDD.

IH

CLK

(pin 4)

3.3 kΩ 1.5 kΩ
(2%) (2%)

load

0.5V

DD

SYNC
(pin 3)

≈ 25 µA

Fig.19 Test loads.

1997 Feb 25 26

6.8 kΩ
(2%)

SDA, SCL
(pins 1, 2)

V

DD

S0 to S23

(pins 17 to 40)

I

load

V

DD

≈ 15 µAI

MGG387

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

handbook, full pagewidth

t

CLKH

CLK

SYNC

t

PSYNC

BP0 to BP3
S0 to S23

f

CLK

OM4085

1

t

CLKL

0.7V

DD

0.3V

DD

0.7V

DD

0.3V

DD

t

SYNCL

0.5 V

(VDD = 5 V)

0.5 V

t

PLCD

MGG391

handbook, full pagewidth

SDA

SCL

SDA

MGA728

t

BUF

Fig.20 Driver timing waveforms.

t

LOW

t

HD;STA

t

r

t

SU;STA

t

HD;DAT

t

HIGH

t

f

t

SU;DAT

t

SU;STO

Fig.21 I2C-bus timing waveforms.

1997 Feb 25 27

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

+85 °C

MGG397

V

(V)

DD

40

handbook, halfpage

I

DD

(µA)

30

20

10

0

0

a. Normal mode; V

−40 °C

24 86

=0V;

LCD

external clock = 200 kHz.

24

handbook, halfpage

I

DD

(µA)

16

8

0

0

24 86

b. Low power mode; V

external clock = 35 kHz.

−40 °C

+85 °C

LCD

OM4085

MGG398

VDD (V)

=0V;

R

(kΩ)

BP

6

4

2

0

0

24 86

handbook, halfpage

a. Backplane output impedance BP0 to BP3

(RBP); VDD= 5 V; T

= −40 to +85 °C.

amb

Fig.22 Typical supply current characteristics.

MGG399

VDD (V)

12

handbook, halfpage

R

S

(kΩ)

8

4

0

0

+25 °C
+85 °C

24 86

b. Segment output impedance S0 to S23 (RS);

MGG400

−40 °C

VDD (V)

VDD=5V.

Fig.23 Typical characteristics of LCD outputs.

1997 Feb 25 28

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1997 Feb 25 29

APPLICATION INFORMATION

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

handbook, full pagewidth

SDA
SCL

SYNC

CLK

V

DD

OSC

A0
A1

A2
SA0
V

SS

V

LCD

BP0
BP2
BP1
BP3

S0

S1

S2

S3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

OM4085

SDA
SCL

SYNC
CLK
V

DD

V

SS

V

LCD

BP0
BP2
BP1
BP3

S24
S25
S26
S27

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

OM4085

40

S47

39

S46

38

S45

37

S44

36

S43

35

S42

34

S41

33

S40

32

S39

31

S38

30

S37

29

S36

28

S35

27

S34

26

S33

25

S32

24

S31

23

S30

22

S29

21

S28

40

S23

39

S22

38

S21

37

S20

36

S19

35

S18

34

S17

33

S16

32

S15

31

S14

30

S13

29

S12

28

S11

27

S10

26

S9

25

S8

24

S7

23

S6

22

S5

21

S4

open-circuit

BACKPLANES

S0

S23

S24

SEGMENTS

Fig.24 Single plane wiring of package OM4085s.

S47

MBH952

OM4085

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

CHIP DIMENSIONS AND BONDING PAD LOCATIONS

handbook, full pagewidth

S4

S5

S9

S10

S7S8S6

25 24 23 22 21 16

26

27

2.5 mm
y

OM4085

(1)

S1

S2

S3

BP3

S0

17181920

15

BP1

14

BP2

13

BP0

S11

S12

S13

S14

S15

S16

S17

S18

(1) Typical value.
Pad size: 120 × 120 µm
Chip area: 7.27 mm.
The numbers given in the small squares refer to the pad numbers.

28

29

30

31

32

33

34

35

36 37 38 39 40 54321

S22

S21

S20

S19

0

0

OM4085

S23

SDA

SCL

SYNC

CLK

V

12

LCD

(1)

V

SS

SA0

A2

A1

A0

OSC

2.91

x

MBH949

mm

11

10

9

8

7

6

DD

V

Fig.25 Bonding pad locations.

1997 Feb 25 30

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

Table 16 Bonding pad locations (dimensions in mm)
All x/y coordinates are referenced to centre of chip, (see Fig.25)

PAD NUMBER SYMBOL x y PIN

1 SDA 200 −1235 1
2 SCL 400 −1235 2
3
4 CLK 856 −1235 4
5V
6 OSC 1080 −1025 6
7 A0 1080 −825 7
8 A1 1080 −625 8
9 A2 1080 −425 9

10 SA0 1080 −225 10

11 V
12 V
13 BP0 1080 547 13
14 BP2 1080 747 14
15 BP1 1080 947 15
16 BP3 1074 1235 16
17 S0 674 1235 17
18 S1 674 1235 18
19 S2 474 1235 19
20 S3 274 1235 20
21 S4 −274 1235 21
22 S5 −474 1235 22
23 S6 −674 1235 23
24 S7 −874 1235 24
25 S8 −1074 1235 25
26 S9 −1080 765 26
27 S10 −1080 565 27
28 S11 −1080 365 28
29 S12 −1080 165 29
30 S13 −1080 −35 30
31 S14 −1080 −235 31
32 S15 −1080 −435 32
33 S16 −1080 −635 33
34 S17 −1080 −835 34
35 S18 −1080 −1035 35
36 S19 −1056 −1235 36
37 S20 −830 −1235 37
38 S21 −630 −1235 38
39 S22 −430 −1235 39
40 S23 −230 −1235 40

SYNC 605 −1235 3

DD

SS

LCD

1062 −1235 5

1080 −25 11
1080 347 12

OM4085

1997 Feb 25 31

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PACKAGE OUTLINE

VSO40: plastic very small outline package; 40 leads

D

y

Z

40

OM4085

SOT158-1

E

c

H

E

21

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT A1A2A

mm

inches

Notes

1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

A

max.

2.70

0.11

0.3

0.1

0.012

0.004

2.45

2.25

0.096

0.089

3

0.25

0.010

b

p

0.42

0.30

0.017

0.012

0.22

0.14

0.0087

0.0055

(1)E(2)

cD

15.6

15.2

0.61

0.60

20

w M

b

p

scale

eHELLpQywv θ

7.6

0.762 2.25

7.5

0.30

0.03 0.089

0.29

12.3

11.8

0.48

0.46

Q

A

2

A

1

1.7

1.5

0.067

0.059

detail X

1.15

0.2

1.05

0.045

0.008 0.004

0.041

L

p

L

0.1 0.1

0.004

(A )

A

3

θ

(1)

Z

0.6

0.3

0.024

0.012

o

7

o

0

OUTLINE

VERSION

SOT158-1

IEC JEDEC EIAJ

REFERENCES

1997 Feb 25 32

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-01-24

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all VSO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

OM4085

Wave soldering

Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Feb 25 33

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

OM4085

rates

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1997 Feb 25 34

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

NOTES

OM4085

1997 Feb 25 35

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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 417067/25/02/pp36 Date of release: 1997 Feb 25 Document order number: 9397750 01676