Datasheet OM4031T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

OM4031T

Digital post-detection filter
for FSK data receivers

Preliminary specification
File under Integrated Circuits, IC03

Philips Semiconductors

October 1994

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

FEATURES

• External clock frequency 30 to 80 kHz (typ. 38.4 kHz)

• Supported data rates 600, 1200, 2400 and 4800 bits/s

(typ.)

• Double bandwidth option (not for 4800 bits/s)

• Schmitt-triggered inputs for optimum slope tolerance

• Enable input for power-down mode

• Open-drain output (3-state in power-down mode)

• No external components required

• Single supply voltage from 1.8 to 6.0 V

• Very low operating current (1.5 µA typ.)

• Operating temperature from −10 to +70 °C.

APPLICATIONS

• Telemetry data receivers

• RF security systems

OM4031T

GENERAL DESCRIPTION

The OM4031T is intended for performance enhancement
of FSK data receivers that do not have a built-in
post-detection filter.

It contains a digital moving average filter to remove noise
from the demodulated data. When operated from a

38.4 kHz external clock it can handle data rates of 600,
1200 and 2400 bits/s at an oversampling rate of 16. The
filter bandwidth can be doubled to ease the search for bit
synchronization on the output data.

To allow for jitter in the input data, a 12-bit sample is taken
for the majority decision. Doubling the filter bandwidth is
realised by taking the majority out of 6 samples
(2400 bits/s) or by doubling the sampling rate (600 and
1200 bits/s).

An input data rate of 4800 bits/s is supported at 8 times
oversampling and normal bandwidth.

All inputs are Schmitt-triggered to ensure reliable
operation even at signals with long rise/fall times.

• Low-bit-rate radio data links

• Paging applications of UAA2080 and UAA2082 with

software decoding.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DD

I

DDPD

I

DD

P

i(ref)

supply voltage 1.8 − 6.0 V
power-down supply current CE = V

SS

− 1.0 10.0 µA
operating supply current CE = VDD; note 1 − 1.5 20.0 µA
sensitivity improvement at 3% bit error rate note 2

600 bits/s, 250 µs slope − 5.3 − dB
1200 bits/s, 250 µs slope − 3.6 − dB
2400 bits/s, 125 µs slope − 2.0 − dB

T

amb

operating ambient temperature −10 − +70 °C

Notes

1. V

= 2.0 V; DOUT open-circuit; input data at 20 kHz random pattern.

DD

2. Bench evaluated for UAA2080H at 470 MHz, not factory tested.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

OM4031T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

October 1994 2

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

BLOCK DIAGRAM

handbook, full pagewidth

DIN

CLK

CE

V

SS

1

13-BIT SHIFT

REGISTER

MAJORITY

LOGIC

CINT DBW PDN

3
2

DATA RATE AND

BANDWIDTH CONTROL

V

DD

4

OM4031T

OUTPUT

LATCH

OM4031T

8

5

DOUT

7

A1

6

A0

Fig.1 Block diagram.

PINNING

SYMBOL PIN DESCRIPTION

DIN 1 data input
CE 2 chip enable input
CLK 3 external clock input
V

SS

4 negative supply voltage
DOUT 5 data output (open-drain)
A0 6 data rate and bandwidth control

input 0 (see Table 1)

A1 7 data rate and bandwidth control

input 1 (see Table 1)

V

DD

8 positive supply voltage

handbook, halfpage

MLC273

DIN

1

CE

2
3
4

OM4031T

MLC274

CLK

V

SS

Fig.2 Pin configuration.

8
7
6
5

V

DD
A1
A0
DOUT

October 1994 3

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

FUNCTIONAL DESCRIPTION

The OM4031T digital post-detection filter oversamples the
noisy binary data stream at input DIN (pin 1), and outputs
a noise-reduced data stream via open-drain output DOUT
(pin 5). The filter bandwidth can be doubled to ease the
search for bit synchronization on the data output signal.

Input sampling takes place at 16 times the data rate. For a
typical clock frequency of 38.4 kHz the nominal data rates
are 600, 1200 and 2400 bits/s. A data rate of 4800 bits/s
can be handled at an oversampling rate of 8 and at normal
bandwidth only.

Using a different clock frequency will produce bit rates
equal to the clock frequency divided by 64, 32 or 16. When
the clock frequency is not an integer multiple of the data
rate some edge jitter will be introduced in the output data.

The clock frequency is not very critical for the noise filtering
performance: a clock frequency of 32.768 kHz could be
used at 512, 1200 and 2400 bits/s without loss of
performance.

OM4031T

Filter implementation

The moving average filter is implemented using a 13-bit
register and two state machines (COUNT and CLOCK) for
the majority decision. The first stage of the shift register is
used for input synchronization.

The CLOCK state machine generates the internal clock
signal CINT and the bandwidth selection signal DBW in
accordance with the logic levels on control lines CE, A0
and A1.

The majority decision is taken by state machine COUNT
based on the contents of the input shift register and the
previous decision in the output latch.

The doubled bandwidth is achieved by increasing the
sampling rate by a factor of 2 for 600 and 1200 bits/s. For
2400 bits/s the number of samples for the majority
decision is halved, controlled by the DBW signal. This
signal is derived from the control signals as follows:

DBW CE A0• A1•=

Since no on-chip oscillator is available an external clock
signal is required at input CLK (pin 3). Two control inputs
A0 and A1 (pins 6 and 7) are used for selection of the data
rate and the filter bandwidth.

A separate enable input CE (pin 2) allows the circuit to be
powered down. In power-down mode (CE = LOW) the
system clock is inhibited and the data output DOUT is
made 3-state and remains static.

Moving average noise filter

Noise reduction is achieved by applying a moving average
filter on N samples of the input data signal. In principle N
can be odd or even, but in the OM4031T an even number
is used (N = 12). When there is no absolute majority (equal
number of ones and zeroes) the previous majority output
is maintained.

An odd value for N would always produce an absolute
majority and not require decision feedback. However the
noise performance is worse for odd values of N, because
the output can toggle at every clock (e.g. when a 101010...
pattern is clocked in). For even values of N the output
polarity can only change once every 3 clocks and does not
toggle at all for a 101010... or a 11001100... pattern.

Using 12 out of 16 samples for the majority decision
produces a filter which combines good noise reduction
with a large tolerance for data jitter (maximum
duration).

October 1994 4

1

⁄8-bit

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

Filter characteristic

The frequency characteristic of the moving average filter in
the OM4031T is given in Fig.3 for N = 12 and N = 6.

The horizontal axis shows the normalized frequency f
which is the ratio of the frequency f and the sampling
frequency fs. The value for fs is given in Table 1 for the
various data rates and filter bandwidths.

The vertical axis shows the normalized amplitude AN.

1.0

handbook, full pagewidth

A

N

0.8

0.6

N

OM4031T

At normal bandwidth the oversampling rate is 16, except
for 4800 bits/s where it is 8. At double bandwidth the
oversampling rate is 32, except for 2400 bits/s,
where it is 16.

The 3 dB cut-off frequency is calculated as follows:
N = 12:
N=6:

f

0.0371 fs×=

co

f

0.0748 fs×=

co

MLC275

0.4

0.2

0

0 0.1 0.2 0.3 0.4

(1) N = 12.
(2) N = 6.

(1) (2)

Fig.3 Filter transfer function of the OM4031T.

f

N

0.5

October 1994 5

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

Noise reduction

The performance of the OM4031T was bench tested by
measuring the sensitivity improvement (3% BER) of the
UAA2080H pager receiver at various bit rates using a
stand-alone pager receiver board (OM4647 at 470 MHz).
The results are given in Chapter “AC Characteristics” .

100

handbook, full pagewidth

call

success

rate
(%)

80

60

OM4031T

The OM4031T was also tested in a POCSAG pager
application using software decoding together with the
UAA2080H receiver.

For 12-digit numeric messages at 1200 bits/s the typical
sensitivity for 80% call success rate improved by 2.8 dB,
as shown in Fig.4.

MLC276

40

20

0

120 122121 124123 129

no filter
with OM4031T

125 127126 128

Fig.4 Paging call success rate improvement; 1200 bits/s, 12-digit numeric message.

130

RF level (dBm)

October 1994 6

Philips Semiconductors Preliminary specification

Digital post-detection filter

OM4031T

for FSK data receivers

OPERATING INSTRUCTIONS
Control signals

The operation of the OM4031T is determined by 3 control
signals (CE, A0 and A1) and the clock frequency at input
CLK. Table 1 shows the various possibilities for a typical
clock frequency of 38.4 kHz.

The parameter N is the number of samples used in the
calculation of the average bit value.

Table 1 Data rate and filter bandwidth selection

CE A1 A0

0XXXX X X
1 0 0 12 9.6 600 −
1 1 0 12 19.2 1200 600
1 0 1 6 38.4 4800
1 1 1 12 38.4 2400 1200

N

(samples)

The parameter f
assuming a 38.4 kHz external clock signal.

The logic levels on A0 and A1 can be changed while
CE = HIGH, except to select or deselect 2400 bits/s with
doubled bandwidth (A1 = LOW, A0 = HIGH). This mode
must be entered or left while CE = LOW to avoid data
errors on DOUT.

f

s

(kHz)

is the input sampling frequency,

s

DATA RATE (bits/s)

NORMAL

BANDWIDTH

(1)

BANDWIDTH

DOUBLE

2400

Note

1. At 4800 bits/s the oversampling rate is 8.

Power-down mode

To reduce power consumption the filter can be disabled by
applying a LOW level to input CE. The result is as follows:

• The internal clock is inhibited

• Output DOUT is made 3-state and static.

Reset

The OM4031T is reset internally when power-down mode
is left by applying a HIGH level to input CE. The actual
reset takes place on the second falling edge on input CLK
after CE = HIGH.

The status after reset is as follows:

• The shift register contains a 101010... pattern

• DOUT is made LOW.

After power-up input CE must be kept at a LOW level for
at least one clock period on input CLK. This ensures a
successful reset when CE is made HIGH.

October 1994 7

Philips Semiconductors Preliminary specification

Digital post-detection filter

OM4031T

for FSK data receivers

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

V

I

I

I

I

O

P

tot

T

amb

T

stg

DC CHARACTERISTICS

V

= 1.8 to 6.0 V; VSS=0V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

I

DDPD

I

DD

Inputs A0, A1, CLK and CE

V

IL

V

IH

I

LI

C

I

Output DOUT

I

OL

I

LO

supply voltage −0.5 7.0 V
input voltage on any pin −0.5 VDD+ 0.5 V
DC input current all pins − 20 mA
DC output current all pins − 20 mA
total power dissipation − 150 mW
operating ambient temperature −10 +70 °C
storage temperature −55 +125 °C

= −10 to +70 °C; unless otherwise specified.

amb

supply voltage 1.8 − 6.0 V
power-down supply voltage CE = VSS; note 1 − 1.0 10.0 µA
operating supply current CE = VDD; notes 1 and 2 − 1.5 20.0 µA

LOW level input voltage −0.5 − +0.3V
HIGH level input voltage 0.7V
input leakage current VI=VDDor VI=V

SS

−−1.0 µA

− VDD+ 0.5 V

DD

DD

input capacitance tested on sample basis − 2.0 − pF

LOW level output current VOL= 0.4 V 1.0 −−mA
output leakage current VOH=V

DD

−−1.0 µA

V

Notes

1. V

= 2.0 V; VIL=VSS; VIH=VDD; DOUT is open-circuit; clock signal at input CLK; f

DD

= 38.4 kHz, amplitude:

clk

VSSto VDD; data signal at input DIN: random pattern at 20 kHz to simulate 2400 bits/s data with noise; tr=tf= 5 ns.

2. The operating current will be higher than specified when the input signal amplitude is less than 100%
(equals VSSto VDD) or when longer rise/fall times are used. This is caused by the Schmitt-trigger circuits drawing
extra current.

October 1994 8

Philips Semiconductors Preliminary specification

Digital post-detection filter

OM4031T

for FSK data receivers

AC CHARACTERISTICS

V

= 1.8 to 6.0 V; VSS=0V; T

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
External clock

f

clk

external clock frequency 30 38.4 80 kHz
Filter bandwidth (note 1)
f

co

cut-off frequency (−3 dB) normal bandwidth

Noise reduction (note 2)
P

i(ref)

sensitivity improvement at 3% bit error rate note 3

= −10 to +70 °C; f

amb

= 38.4 kHz; unless otherwise specified.

clk

600 bits/s − 356 − Hz
1200 bits/s − 712 − Hz
2400 bits/s − 1425 − Hz
4800 bits/s − 2872 − Hz

double bandwidth

600 bits/s − 712 − Hz
1200 bits/s − 1425 − Hz
2400 bits/s − 2872 − Hz

600 bits/s, 250 µs slope − 5.3 − dB
1200 bits/s, 250 µs slope − 3.6 − dB
2400 bits/s, 125 µs slope − 2.0 − dB

Notes

1. Filter bandwidth is guaranteed by design. Values supplied are simulation results.

2. Noise reduction is not factory tested, only bench evaluated.

3. Sensitivity improvement was bench tested on the UAA2080H demonstration board OM4747. Test signal: preamble
(101010...), f
See “

UAA2080 data sheet, AC characteristics”

= 469.950 MHz, deviation = ±4.0 kHz, slope = 10 to 90% of amplitude, VP= 2.05 V, T

iRF

.

amb

=25°C.

October 1994 9

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

APPLICATION INFORMATION

ndbook, full pagewidth

V

FSK

RF

RECEIVER

CC

DO

CE

DIN

CE

V

CC

OM4031T

CLK

DOUT

A1
A0

R

pull

38.4 kHz

V

DD

MICROCONTROLLER

MLC277

OM4031T

Fig.5 Typical application example.

The OM4031T will generally operate from the same power
supply (VCC) as the FSK data receiver providing its input
data. The open-drain data output allows level shifting of
the data to suit a microcontroller operating at a higher
power supply voltage (VDD).

The value of the pull-up resistor R

on output DOUT is

pull

determined by the type and number of input circuits to be
driven. The required signal rise time must be balanced
against the current drawn by the pull-up.

For the highest rate (2400 bits/s) the signal rise time
should preferably be below 50 µs.

For a single CMOS input with a 10 pF capacitance
R

=1MΩ gives a rise time of approximately 30 µs

pull

(3 × tRC). At VDD= 2.0 V this corresponds with a current
of 2 µA.

October 1994 10

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

PACKAGE OUTLINE

handbook, full pagewidth

0.7

0.3

8

5.0

4.8

OM4031T

4.0

3.8

0.1 SS

5

1.45

1.25

6.2

5.8

0.7

0.6

A

0.25

0.19

1.75

1.35

Dimensions in mm.

1

pin 1
index

1.27

0.49

0.36

4

0.25 M
(8x)

0.25

0.10

detail A

1.0

0.5

0 to 8

MBC180 - 1

o

Fig.6 Plastic small outline package; 8 leads; body width 3.9 mm (SO8; SOT96-1).

October 1994 11

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

SOLDERING
Plastic small-outline packages

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

OM4031T

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

-HEATED SOLDER TOOL)

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

October 1994 12

Philips Semiconductors Preliminary specification

Digital post-detection filter

OM4031T

for FSK data receivers

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

October 1994 13

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

OM4031T

NOTES

October 1994 14

Philips Semiconductors Preliminary specification

Digital post-detection filter
for FSK data receivers

OM4031T

NOTES

October 1994 15

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil.
P.O. Box 7383 (01064-970).
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

Tel. [phone], Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: P.O. Box 10 63 23, 20043 HAMBURG,

Tel. [phone], Fax. [phone].

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg.,

24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. [phone], Fax. [phone]

India: Philips INDIA Ltd, Shivsagar Estate, A Block ,

Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS S.r.l.,

Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone].

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone].

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone].

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone].

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone].

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States:811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD35 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

Philips Semiconductors