Datasheet nx9811ads Datasheet

NEXSEM

13A SYNCHRONOUS BUCK SWITCHING REGULATOR

WITH 600kHz OPERATION FREQUENCY

NX9811A

PRELIMINARY DATA SHEET

Pb Free Product

DESCRIPTION

The NX9811A is synchronous buck switching converter
in multi chip module designed for step down DC to DC
converter applications. They are optimized to convert
bus voltages from 2V to 25V to as low as 0.8V output
voltage. The output current can be up to 13A. The
NX9811A offers an enable pin that can be used to pro­gram the converter's start up. NX9811A operates at fixed
internal frequency of 600kHz and employ loss-less cur­rent limiting protection by sensing the Rdson of syn­chronous MOSFET followed by latch out feature. Feed­back under voltage protection triggers hiccup.
Other features are: Internal digital soft start; Vcc
undervoltage lock out and shutdown capability via the
enable pin or comp pin. NX9811A is available in 8x8 MCM
package.

Vin1

+12V

C3

200uF

L2 1uH

2 x 10uF

C1

33pF

Cin

C2

3.3nF

R5

13k

VIN

EN
COMP

N X 9 8 1 1 A

FB

FEATURES

n Switching Controller and MOSFETs in one package
n Bus voltage operation from 2V to 25V
n Fixed 600kHz
n Internal Digital Soft Start Function
n Output current up to 13A
n Enable pin to program BUS UVLO
n Programmable current limit triggers latch out by

sensing Rdson of Synchronous MOSFET

n No negative spike at Vout during startup and

shutdown

n Pb-free and RoHS compliant

APPLICATIONS

n Graphic Card on board converters
n On board DC to DC such as 12V to 5V, 3.3V or

1.2V

n Point of load applications
n Area constrained DC to DC step down applications

TYPICAL APPLICATION

R6

VCC

BST

SW

OCP

C4

1uF

10

C7

0.1uF

R4
6k

Vin2

+5V

D1
MBR0530T1

L1 1.5uH

R3

R1

1k

40k

Co
2 x 22uF

Vout
+3.3V,10A

AGND

PGND

C6

390p

R2

16k

Figure 1 - Typical application of 9811A

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX9811ACMTR 0 to 70oC 8X8 MCM-56L 600kHz Yes

Rev.1.1
03/20/07

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1

NEXSEM

NX9811A

ABSOLUTE MAXIMUM RATINGS

VCC to GND & BST to SW voltage .................... -0.3V to 6.5V

VIN to GND ...................................................... 25V

BST to GND Voltage ........................................ -0.3V to 35V

SW to GND ...................................................... -2V to 35V

All other pins .................................................... -0.3V to VCC+0.3V or 6.5V

Storage Temperature Range ............................... -65oC to 150oC

Operating Junction Temperature Range ............... -40oC to 125oC

ESD Susceptibility ........................................... 2kV

Power Dissipation ............................................. TBD(Note1)

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

Note1: Under room temperature, this module can dissipate up to 5.5W on a four layer PCB board with 1ounce
copper.

PACKAGE INFORMATION

56-LEAD PLASTIC MCM 8 x 8

NC

FB

COMP

54

55

56

AGND

HDRV

AGND

OCP

SW

BST

HG
VIN
VIN
VIN
VIN

VIN
VIN

VIN

10
11
12
13
14

1
2
3
4
5
6
7
8
9

15

16

AGND
(PAD1)

VIN
(PAD2)

17

VCC

EN

5253

51

18 19 20

AGND

50

21 22

SW

49

SW

23

SW

4748

SW
(PAD3)

24 25

SW

46

SW

45

26

SW

44

27

SW

43

28

SW

41

37
36

42

40
39
38

35
34

32
31
30
29

33

SW
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND

Rev.1.1
03/20/07

VIN

VIN

VIN

VIN

VIN

VIN

SW

PGND

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PGND

PGND

PGND

PGND

PGND

PGND

2

NEXSEM

Under Voltage Lockout

Oscillator

Error Amplifiers

EN & SS

Ouput Stage

DSON

DSON

OCP Adjust

uA

NX9811A

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc = 5V, VIN = 12V and TA= 0 to 70oC. Typical values
refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the
ambient temperature.

PARAMETER SYM Test Condition Min TYP MAX Units

Reference Voltage

Ref Voltage V
Ref Voltage line regulation 0.2 %

Supply Voltage(Vcc)

VCC Voltage Range V
VCC Supply Current (Static) ICC (Static) Outputs not switching 3 mA
VCC Supply Current
(Dynamic)

Supply Voltage(V

V

Supply Current (Static) I

BST

V

Supply Current

BST

(Dynamic)

BST

)

REF

CC

I

CC

(Dynamic)

(Static) Outputs not switching TBD mA

BST

I

BST

(Dynamic)

4.5

0.8

5

TBD mA

TBD mA

5.5

V

V

VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V

Frequency F
Ramp-Amplitude Voltage V
Max Duty Cycle 95 %

Min Duty Cycle 0 %

Transconductance 2000 umho
Input Bias Current Ib 10 nA

Soft Start time Tss 3.4 mS
Enable HI Threshold 1.25 V
Enable Hysterises 150 mV

High Side MOSFET R
Low Side MOSFET R
Maximum Output Current

OCP current 40

FB Under Voltage Protection

FB Under Voltage Threshold 0.48 V

S

RAMP

15 mohm
15 mohm

600 kHz

3.8

4

1.5 V

13

4.2

V

A

Rev.1.1
03/20/07

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NEXSEM

PIN DESCRIPTIONS

PIN # PIN SYMBOL PIN DESCRIPTION

1,6,51

AGND

Analog ground.

NX9811A

2

3,21

40-50

4
5

7

8-20

22-39

52

OCP

SW

HDRV

BST

HG

VIN

PGND

VCC

This pin is connected to the drain of the external low side MOSFET via resistor and
is the input of the over current protection(OCP) comparator. An internal current
source 40uA is flown to the external resistor which sets the OCP voltage across
the Rdson of the low side MOSFET. Current limit point is this voltage divided by the
Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are latched out.

These pins are connected to source of high side FET and provides return path for
the high side driver. It is also used to hold the low side driver low until this pin is
brought low by the action of high side turning off. LDRV can only go high if SW is
below 1V threshold .

High side MOSFET gate driver output
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capaci-

tor is placed as close as possible to and connected to this pin and SW pin.
High side MOSFET gate pin out which is needed to connected HDRV pin.
Bus input which is connected to high side MOSFET's drain.
Source of low side MOSFET and ground of switching converter.
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as

possible to and connected to this pin and ground pin. The maximum rating of this
pin is 5V.

53

54

55

56

Rev.1.1
03/20/07

EN

FB

COMP

NC

A resistor divider is connected from the respective switcher BUS voltages to these
pins that holds off the controller's soft start until this threshold is reached. An
external low cost transistor can be connected to this pin for external enable control.

This pin is the error amplifier inverting input. It is connected via resistor divider to the
output of the switching regulator to set the output DC voltage. When FB pin voltage
is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048
switching cycles.

This pin is the output of error amplifier and is used to compensate the voltage
control feedback loop. This pin can also be used to perform a shutdown if pulled
lower than 0.3V.

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4

NEXSEM

BLOCK DIAGRAM

NX9811A

VCC

EN

FB

COMP

AGND

Bias
Generator

1.25
/1.15

START

Digital
start Up

0.8V

ramp

START

1.25V

0.8V

OSC

0.6V
CLAMP

UVLO

1.3V
CLAMP

BST

FB

0.6V

POR

START

OC

S

Q

R

Latch Out

PWM

OC

Hiccup Logic

OC

Control
Logic

OCP
comparator

VCC

HDRV

LDRV

40uA

VIN

SW

PGND

OCP

Rev.1.1
03/20/07

Figure 2 - Simplified block diagram of the NX9811A

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5

NEXSEM

Demoboard schematic

NX9811A

VBUS

U2

1

1

OUT

2

GND

IN

L78L05AB/sot89

3

VBUS

C12
220u/16V

VSW

5V

C2
47u

C11

HG

0.1u

L1

DO3316P-102

R12

pot 100k +1k

C20

R9

op

open

C19

op

56

U1

PAD1

C10
OP

R6

8.25k

VSW

D1

BAT54A

R3

3

0

C1
OP

VIN

12

C13
OP

C3

1

0.1u

2

R2
0

C14
OP

PAD2

C6
op

NC

AGND4

1

AGND1

6

AGND2

2

OCP

3

VSW

5

BST

4

HDRV

7

HG

8

VIN1

9

VIN2

10

VIN3

11

VIN4

12

VIN5

13

VIN6

14

VIN7
VIN14

C9
10u,16V

EN

C21

3.3n

R5
13k

C5

33p

55FB54EN53

COMP

R4
10k

R8

open

R7

5k

C18

op

NX9811A

VIN815VIN916VIN1017VIN1118VIN1219VIN1320SW1

C8
10u,16VC7op

21

VSW

52

VCC

VBUS

R1

10

C4

1u

51

AGND3

PGND122PGND223PGND324PGND425PGND526PGND627PGND7

5V

48

SW1250SW1149SW10

28

43

SW947SW846SW745SW644SW5

SW13

SW4
SW3
SW2

PGND18
PGND17
PGND16
PGND15
PGND14
PGND13
PGND12
PGND11
PGND10

PGND9
PGND8

VSW

1

PAD3
42
41
40

39
38
37
36
35
34
33
32
31
30
29

JVSW

5

DO5010P-152HC

R13
10

C24
470p

R10

40k

C22

R11

390p

1k

JVOUT

1

234

5

VOUT

C16
22u,6.3V

C23

0.1u

VOUT

C15
OP

GND

234

L2

12

C17

L3

OP

22u,6.3V

12

Rev.1.1
03/20/07

Title

NX98xx EVALUATION BOARD

Size Document Number Rev

9811-ML-01A A

Date: Sheet of

Figure 3- Demo board schematic based on ORCAD

www.nexsem.com

1 1Wednesday, February 21, 2007

6

NEXSEM

Bill of Materials

Item Quantity Reference Value Manufacture

1 1 C2 47u,electricial
2 3 C3,C11,C23 0.1u
3 1 C4 1u
4 1 C5 33p
5 2 C8,C9 10u/16V ceramic
6 1 C12 220u/16V,electrical
7 2 C16,C17 22u/6.3V, ceramic
8 1 C21 3.3n

9 1 C22 390p
10 1 C24 470p
11 1 D1 BAT54A
12 1 L1 DO3316P-102 Coilcraft
13 1 L2 DO5010P-152HC Coilcraft
14 2 R1,R13 10
15 2 R2,R3 0
16 1 R4 10k
17 1 R5 13k
18 1 R6 8.25k
19 1 R7 5k
20 1 R10 40k
21 1 R11 1k
22 1 R12 100k pot
23 1 U1 NX9811A NEXSEM INC.
24 1 U2 L78L05AB/sot89

NX9811A

Rev.1.1
03/20/07

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7

NEXSEM

Demoboard waveforms

NX9811A

Figure 4 - Output ripple @ VOUT=3.3V

Figure 6 - Output voltage transient response
@VOUT=5V

Figure 5 - Output voltage transient response
@VOUT=1.2V

Figure 7 - Startup @VOUT=3.3V

Figure 8 - Short circuit protection

Rev.1.1
03/20/07

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8

NEXSEM

Eff (%)

Demoboard waveforms(Cont'd)

Efficiency v.s. Output Voltage

Vin=12V, Iout=8A

95.00%

90.00%

85.00%

80.00%

75.00%

70.00%
1 1.5 2 2.5 3 3.5 4 4.5 5

NX9811A

Vout (V)

95.00%

90.00%

85.00%

Eff (%)

80.00%

75.00%

70.00%

Figure 9 - Efficiency chart

Efficiency v.s. Output Voltage

Vin=12V, Iout=10A

1 1.5 2 2.5 3 3.5 4 4.5 5

Vout (V)

Rev.1.1
03/20/07

Figure 10 - Efficiency chart

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9

NEXSEM

Eff (%)

Demoboard waveforms(Cont'd)

Efficiency v.s. Output Voltage

Vin=12V, Iout=13A

95.00%

90.00%

85.00%

80.00%

75.00%

70.00%
1 2 3 4 5

NX9811A

Vout(V)

Figure 11 - Efficiency chart

Rev.1.1
03/20/07

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10

NEXSEM

RIPPLEINS

1

IVF

0.310A12V600kHz

=2.66A

SOUT

8600kHz44uF

NX9811A

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple

Design Example

The following is typical application for NX9811A,
the schematic is figure 1.
VIN = 12V
VOUT=3.3V
FS=600kHz
IOUT=10A
DVRIPPLE <=33mV
DVDROOP<=150mV @ 3A step

Output Inductor Selection

The selection of inductor value is based on induc­tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu­ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli­cation requirements. The inductor value can be calcu­lated by using the following equations:

V-VV

L=
I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.3, then

L=
L=1.33uH

Choose inductor from COILCRAFT DO3316P­152HC with L=1.5uH is a good choice.

Current Ripple is recalculated as

INOUT OUT

OUT

∆

12V-3.3V3.3V1

OUT

OUT

×

×

××

××

...(1)

V-VV

I=

∆××

RIPPLE

INOUT OUT

LVF

OUTINS

12V-3.3V3.3v1

1.5uH12V600kHz

××=

1

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C

Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.

In this example ceramic capacitors are chosen as
output capacitors, both terms in equation (3) need to be
evaluated to determine the overall ripple. Usually when
this type of capacitors are selected, the amount of ca­pacitance per single unit is not sufficient to meet the
transient specification, which results in parallel configu­ration of multiple capacitors. Two 22uF, X5R ceramic
capacitor with 2mΩ ESR is used. The amount of output

ripple is

V2m2.66A

∆=Ω×+

RIPPLE

17.9mV

Although this meets DC ripple spec, however it
needs to be studied for transient requirement.

=

is the value of output capacitors.

OUT

RIPPLE

××

8FC

2.66A

××

...(3)

Rev.1.1
03/20/07

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11

NEXSEM

DROOPTRAN

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.048H

=µ

2m22F1.32us

2

1.03×∆=+×τ

NX9811A

Based On Transient Requirement

Typically, the output voltage droop during transient

is specified as:

V<V∆∆ @ step load DI

During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI
transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the fol­lowing equation.

VESRI

tance of each capacitor if multiple capacitors are used
in parallel.

put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-

pacitance is high and
transient spec is dependent on the ESR of capacitor.

capacitors in parallel. The number of capacitors can be
calculated by the following

overshootstep

where τ is the a function of capacitor, etc.

0ifLL




LI

×∆

τ=




V

OUT



where

ESRCVESRCV

L

==

crit

where ESRE and CE represents ESR and capaci-

The above equation shows that if the selected out-

In most cases, the output capacitors are multiple

ESRI

N

where

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

××××

II

∆∆

stepstep

×∆

Estep

V2LCV

∆×××∆

tranEtran

≤

crit

step

−×≥

2LC

≤ is true. In that case, the

V

OUT

V

OUT

××

STEP

OUT

STEP

...(4)

...(5)

...(6)

...(7)

...(8)

For example, assume voltage droop during tran-

sient is 150mV for 3A load step.

Two 22uF, X5R ceramic capacitor with 2mΩ ESR

is used, the critical inductance is given as

ESRCV

××

L

crit

critical inductance. In that case, the output voltage tran­sient not only dependent on the ESR, but also capaci­tance.

2m22F3.3V

Ω×µ×

The selected inductor is 1.5uH which is bigger than

number of capacitors is

LI

×∆

τ=−×

V

1.5H3A

µ×

=−Ω×µ=

3.3V

ESRI

N

2m3A

Ω×

=+

150mV

21.5H22F150mV

×µ×µ×

=

The number of capacitors has to satisfied both ripple

and transient requirement. Overall, we can choose N=2.

It should be considered that the proposed equa­tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more capaci­tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es­pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.

EEOUT

==

step

OUT

Estep

V2LCV

∆×××∆

3.3V

I

∆

step

3A

ESRC

EE

V

OUT

tranEtran

(1.32us)

×

2

Compensator Design

Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve

Rev.1.1
03/20/07

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12

NEXSEM

F ...(9)

F ...(10)

F ...(11)

F ...(12)

OUT minin1

V1gZZ/R

f

OUT in

Z

VZ

−

NX9811A

accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin.Ideally,the
Bode plot of the closed loop system has crossover fre­quency between1/10 and 1/5 of the switching frequency,
phase margin greater than 50o and the gain crossing
0dB with -20dB/decade. Power stage output capacitors
usually decide the compensator type. If electrolytic
capacitors are chosen as output capacitors, type II com­pensator can be used to compensate the system, be­cause the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensa­tor should be chosen.

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross­over frequency. In this case, it is necessary to compen­sate the system with type III compensator. The follow­ing figures and equations show how to realize the type III
compensator by transconductance amplifier.

To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desir­able if R1||R2||R3>>1/gm can be met at the same time.

C2

Zf

C1

R4

Zin

Vout

R3

R2

C3

Fb

gm

Ve

R1

Vref

Figure 12 - Type III compensator using

transconductance amplifier

Case 1: FLC<FO<F

(ceramic)

ESR

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator for

transconductance amplifier is given by:

V 1gZ

e mf

For the voltage amplifier, the transfer function of
compensator is

=

V

e

=

1

2RC

×π××

42

1

2(RR)C

×π×+×

2RC

×π××

2R

×π××

+×+

233

1

33

1

CC

12

4

CC

12

−×

×
+

power stage

LC

F

Gain(db)

40dB/decade

loop gain

20dB/decade

ESR

F

F

O

Figure 13 - Bode plot of Type III compensator

compensator

F

F

Z1 Z2

F

P1

F

S

F

P2

Rev.1.1
03/20/07

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13

NEXSEM

21.5uH44uF

22m44uF

R=12.8k

==Ω

=(-)

240k9.8kHz450kHz

=44uF

20.219.6kHz13k

×π×××Ω

213k300kHz

2450kHz390pF

NX9811A

Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<F

1.Calculate the location of LC double pole F

and ESR zero F

and FO<=1/10~1/5F

ESR,

.

ESR

F

=

LC

2LC

×π××

=

s.

LC

1

OUTOUT

1

×π××

19.6kHz

=

F

=

ESR

2ESRC

×π××

=

×π×Ω×

3.6MHz

=

1

OUT

1

2. Set R2 equal to 40kΩ.

×

2REF

1

V-V3.3V-0.8V

OUT REF

40k0.8V

Ω×

RV

Choose R1=12.7kΩ.

3. Set zero FZ2 = 0.5FLC and Fp1 =3/4FS .

6. Calculate C1 by equation (12) with pole Fp2 at

half the switching frequency.

C

=

1

2RF

=

40pF

=

1

×π××

4P2

1

×π×Ω×

Choose C1=33pF

7. Calculate R3 by equation (11).

1

2FC

×π××

P13

1

×π××

R

=

3

=

906

=Ω

Choose R3=1kΩ.

Case 2: FLC<FO<F

( low ESR POSCAP,

ESR

OSCON)

4. Calculate R

and C3 with the crossover

4

frequency at 1/10~ 1/5 of the switching frequency. Set
FO=100kHz.

C=(-)

111

3

2RFF

×π×

×π×Ω

×

2z2p1

111

×

=397pF

V2FL

OSCO

R=C

4out

VC

1.5V2100kHz1.5uH
12V390pF

=13.3k

×π××

××

in3

×π××

××

Ω

Choose C3=390pF, R4=13kΩ.

5. Calculate C2 with zero Fz1 at 20% of the LC

double pole by equation (9).

1

2FR

×π××

Z14

1

C

=

2

=

3.1nF

=

power stage

LC

F

Gain(db)

40dB/decade

loop gain

ESR

F

20dB/decade

compensator

F

Z1 Z2

F

F

O

F

F

P1

P2

Figure 14 - Bode plot of Type III compensator

(FLC<FO<F

ESR

)

Choose C2=3.3nF.

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14

NEXSEM

21.5uH560uF

27m560uF

==Ω

R=8k

=(-)

210k5.5kHz40.6kHz

=2.5nF

=560uF

20.755.5kHz10.7k

×π×××Ω

210.7k300kHz

240.6kHz2.7nF

NX9811A

Typical design example of type III compensator in which
one oscon capacitor (560uF, 7mohm) is chosen as output
capacitor is shown as the following steps.

1. Calculate the location of LC double pole F

and ESR zero F

=

F

LC

=

.

ESR

1

×π××

2LC

OUTOUT

1

LC

×π××

=

5.5kHz

=

F

ESR

40.6kHz

×π××

2ESRC

=

×π×Ω×

=

1

OUT

1

2. Set R2 equal to 10kΩ.

RV

2REF

1

V-V1.8V-0.8V

OUT REF

Ω×

10k0.8V

×

Choose R1=8.06kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

111

C=(-)

3

×π×

2RFF

×π×Ω

×

2z2p1

111

×

, calculate C

ESR

3.

1

2FR

×π××

Z14

1

C

=

2

=

3.6nF

=

Choose C2=3.3nF.

6. Calculate C1 by equation (12) with pole Fp2 at

half the switching frequency.

C

=

1

=

49pF

=

1

2RF

×π××

4P2

1

×π×Ω×

Choose C1=47pF.

7. Calculate R3 by equation (11) with Fp1 =F

1

2FC

×π××

P13

1

×π××

R

=

3

=

1.45k

=Ω

Choose R3 =1.43kΩ.

ESR

.

Choose C3=2.7nF.

4. Calculate R4 with the crossover frequency at 1/

10~ 1/5 of the switching frequency. Set FO=60kHz.

V2FL

OSCO

R=C

4out

VC

1.1V260kHz1.5uH
12V2.7nF

=10.7k

×π××

××

in3

×π××

××

Ω

Choose R4=10.7kΩ.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (9).

Rev.1.1
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15

NEXSEM

21uH3000uF

26.5m3000uF

==Ω

R=8k

=(-)

210k2.9kHz8.2kHz

=3.5nF

28.2kHz3.3nF

1.5V260kHz1uH10k5.9k

12V6.5m10k5.9k

×π××Ω×Ω

ΩΩ+Ω

20.752.9kHz26.7k

×π×××Ω

226.7k300kHz

NX9811A

Case 3: FLC<F

power stage

Gain(db)

loop gain

compensator

F

Z1 Z2

ESR<FO

LC

F

ESR

F

F

40dB/decade

F

F

P1

O

20dB/decade

F

P2

2. Set R2 equal to 10kΩ.

RV

2REF

1

V-V1.8V-0.8V

OUT REF

10k0.8V

×

Choose R1=8kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

4. Calculate C3 .

C=(-)

3

111

2RFF

×π×

×π×Ω

×

2z2p1

111

×

Choose C3=3.3nF.

5. Calculate R3 .

1

2FC

×π××

P13

1

×π××

R

=

3

=

5.9k

=Ω

Choose R3 =5.9kΩ.

6. Calculate R4 with FO=60kHz.

Ω×

ESR

.

Figure 15 - Bode plot of Type III compensator

(FLC<F

ESR<FO

)

If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F

and FO<=1/10~1/5Fs is shown

ESR<FO

as the following steps. Here two SANYO MV-WG1500
with 13 mΩ is chosen as output capacitor.

1. Calculate the location of LC double pole F

and ESR zero F

F

=

LC

=

.

ESR

1

2LC

×π××

OUTOUT

1

LC

×π××

2.9kHz

=

F

=

ESR

2ESRC

=

8.2kHz

=

1

×π××

OUT

1

×π×Ω×

R=

=
=26.9k

V2FLRR

OSCO23

4

VESRRR

×π×××

××

in23

+

××
Ω

Choose R4=26.7kΩ.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (9).

1

2FR

×π××

Z14

1

C

=

2

=

2nF

=

Choose C2=2.2nF.

6. Calculate C1 by equation (12) with pole Fp2 at

half the switching frequency.

C

=

1

=

20pF

=

1

2RF

×π××

4P2

1

×π×Ω×

Choose C1=22pF.

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16

NEXSEM

Gain=gR ... (13)

F= ... (14)

F ... (15)

21uH3000uF

26.5m3000uF

==Ω

R=800

B. Type II compensator design

If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa­tor can be used to compensate the system.

Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 17. R3 and C
introduce a zero to cancel the double pole effect. C
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero lo­cation and constant gain.

R

1

××

m3

R+R

12

1

2RC

×π××

31

1

2RC

×π××

32

power stage

loop gain

40dB/decade

20dB/decade

z

≈

p

Gain(db)

NX9811A

Vout

R2

Fb

1

2

R1

Vref

Figure 17 - Type II compensator with
transconductance amplifier

For this type of compensator, FO has to satisfy

FLC<F

tor design. Input voltage is 12V, output voltage is 1.8V,
output inductor is 1uH, output capacitors are two 1500uF
with 13mΩ electrolytic capacitors.

and ESR zero F

<<FO<=1/10~1/5F

ESR

The following is parameters for type II compensa-

1.Calculate the location of LC double pole F
.

ESR

F

=

LC

2LC

×π××

=

×π××

2.9kHz

=

s.

1

OUTOUT

1

gm

Ve

R3

C2

C1

LC

compensator

F

Figure 16 - Bode plot of Type II compensator

Rev.1.1
03/20/07

F

=

ESR

2ESRC

Gain

F

F

LC

Z

ESR

P

F

F

O

swithing frequency, here FO=60kHz.

8.2kHz

2.Set R2 equal to 1kΩ.

1

V-V1.8V-0.8V

Choose R1=806Ω.

3. Set crossover frequency at 1/10~ 1/5 of the

4.Calculate R3 value by the following equation.

×π××

=

×π×Ω×

=

×

RV

2REF

OUT REF

www.nexsem.com

1

OUT

1

Ω×

1k0.8V

17

NEXSEM

12V6.5m2.0mA/V

28.2k0.752.9kHz

p

F

8.2k300kHz

OUT

REF

2REF

OUT REF

IID1-D

4.Calculate R3 value by the following equation.

V2FLV

OSCOOUT

R=

3

VRgV

1.5V260kHz1uH1

=

=8.15k

Choose R3 =8.2kΩ.

5. Calculate C1 by setting compensator zero F

at 75% of the LC double pole.

C=

1

2RF
=
=8.9nF

Choose C1=8.2nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

C=

2

=
=129pF

Choose C1=120pF.

Output Voltage Calculation

Output voltage is set by reference voltage and ex-

ternal voltage divider. The reference voltage is fixed at

0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation and picture show the relationship between

V ,

V and voltage divider..

R=

1

where R2 is part of the compensator, and the value

of R1 value can be set by voltage divider.

See compensator design for R1 and R2 selection.

×π××

×××

inESRmREF

×π××

××

1.8V

×

0.8V

Ω

1

×π××

3z

×π×Ω××

1

RF

π××

3s

1

π×Ω×

RV

×

V-V

1

Ω

1

...(16)

NX9811A

Vout

R2

Fb

R1

Vref

Voltage divider

Figure 18 - Voltage divider

Input Capacitor Selection

Z

Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca­pacitors bypass the high frequency noise, and bulk ca­pacitors supply switching current to the MOSFETs. Usu­ally 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are de­cided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:

=××

RMSOUT

V

OUT

D

=

V

IN

VIN = 12V, VOUT=1.8V, IOUT=9A, the result of input
RMS current is 3.2A.

For higher efficiency, low ESR capacitors are rec­ommended. Two 10uF X5R ceramic capacitors are cho­sen as input bulk capacitors.

Soft Start and Enable

NX9811A has digital soft start for switching con­troller and has one enable pin for this start up. When
the Power Ready (POR) signal is high and the voltage at
enable pin is above 1.25V the internal digital counter
starts to operate and the voltage at positive input of Error
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the de­sired voltage decided by the feedback resistor divider.

...(17)

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18

NEXSEM

2

(9V1.25V)R

SWLDSON

IR+V

OCPOCP

DSON

R8.43k

===Ω

NX9811A

Vbus

+

ON

OFF

10k

R1

R2

EN

1.25V/

1.15V

POR

Digital
start
up

Figure 19 - Enable and Shut down the NX9811A

with Enable pin.

The start up of NX9811A can be programmed
through resistor divider at Enable pin. For example, if
the input bus voltage is12V and we want NX9811A starts
when Vbus is above 9V. We can select using the follow­ing equation.

−×

=

R

1

1.25V

The NX9811A can be turned off by pulling down the
Enable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin is below 1.25V, the digi­tal soft start is reset to zero. In addition, all the high side
and low side driver is off and no negative spike will be
generated during the turn off.

vbus

OCP

I

40uA

OCP

R

SW

OCP

OCP
comparator

Figure 20 - Over current protection

The over current limit can be set by the following

equation

SET

×

KR

×

IR

=

I

According to datasheet the lower MOSFET

R

=15mΩ, the worst case thermal consideration

DSON

K=1.5 and the current limit is set at 15A, then

IKR

SETDSON

OCP

Choose R

××

I40uA

OCP

=8.25kΩ

OCP

15A1.515m

××Ω

Over Current Protection

Over current protection is achieved by sensing cur­rent through the low side MOSFET. An internal current
source of 40uA flows through an external resistor con­nected from OCP pin to SW node sets the over current
protection threshold. When synchronous FET is on, the
voltage at node SW is given as

V=-IR×

The voltage at pin OCP is given as

×

OCPOCPSW

When the voltage is below zero, the over current
occurss as shown in figure 20.

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19