Page 1
NX9548
9A SINGLE CHANNEL MOBILE PWM SWITCHING REGULATOR
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX9548 is buck switching converter in multi chip
module designed for step down DC to DC converter in
portable applications. It is optimized to convert single
supply up to 24V bus voltage to as low as 0.75V output
voltage.The output current can be up to 9A. It can be
selected to operate in synchronous mode or non-synchronous mode to improve the efficiency at light load.
Constant on time control provides fast response, good
line regulation and nearly constant frequency under wide
voltage input range. Over current protection and FB UVLO
followed by latch feature. Other features includes: internal boost schottky diode, 5V gate drive capability, power
good indicator, over current protection, over voltage protection and adaptive dead band control.NX9548 is available in 5x5 MCM package.
PGOOD
100k
5V
10
1u
PGOOD
PVCC
VCC
1u
ENSW
/MODE
N X 9 5 4 8
FEATURES
n Internal Boost Schottky Diode
n Ultrasonic mode operation available
n Bus voltage operation from 4.5V to 24V
n Less than 1uA shutdown current with Enable low
n Excellent dynamic response with constant on time
control
n Selectable between Synchronous CCM mode and
diode emulation mode to improve efficiency at light
load
n Programmable switching frequency
n Current limit and FB UVLO with latch off
n Over voltage protection with latch off
APPLICATIONS
n UMPC, Notebook PCs and Desknotes
n Tablet PCs/Slates
n On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Hand-held portable instruments
TYPICAL APPLICATION
4.7
1M
1n
VIN 8V~22V
2x10uF
1u
10k
3.3uH
Vout 1.5V/9A
2R5TPE330MC
330uF
TON
D1
BST
S1
D2
OCP
Rev.1.6
03/06/09
HG
HDRV
GND
VOUT
S2
FB
330p
7.5k
7.5k
Figure 1 - Typical application of 9548
ORDERING INFORMATION
Device Temperature Package Pb-Free
NX9548CMTR 0 to 70oC 5X5 MCM-32L Yes
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NX9548
ABSOLUTE MAXIMUM RATINGS
VCC,PVCC to GND & BST to SW voltage ........... -0.3V to 6.5V
TON to GND ................................................. .... -0.3V to 28V
HDRV to SW Voltage ....................................... -0.3V to 6.5V
D1 to S1and D2 to S2 ........................................ 30V
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
Power Dissipation ............................................. TBD
Output Current ...................................................TBD
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
32-LEAD PLASTIC MCM 5 x 5
D1
31
32
S1
1
S1
S1
D1
D2
D2
D2
D2
2
3
4
5
6
7
8
9
D1
(PAD2)
10
D1
11
D1
2930
D2
(PAD3)
12
HG
28
13 14
GND
27
GND
(PAD1)
PGOOD
FB
26
15
25
16
VCC
24
23
22
20
19
18
17
TON
VOUT
ENSW/MODE
GND
21
BST
D2
HDRV
NC
Rev.1.6
03/06/09
S2
S2
S2
S2
S2
S2
PVCC
OCP
2
Page 3
NX9548
VCC UVLO
Under-voltage Lockout
Falling VCC threshold
3.9 V
ON and OFF time
TON operating current
VIN=15V, Rton=1Mohm
15
uA
FB voltage
PGOOD
PGOOD delay after softstart
NOTE1
1.6
ms
PGOOD output switch
PGOOD leakage current
1 uA
ENSW/MODE threshold and
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, VIN = 12V and TA= 0 to 70oC. Typical values
refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the
ambient temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
VIN
recommended voltage range 4.5 24
Shut down current ENSW=GND 1
VCC,PVCC Supply
Input voltage range
Operating quiescent current
Shut down current
threshold
V
in
VCC_UVLO
4.5 5.5 V
FB=0.85V, ENSW=5V 1.8 mA
ENSW=GND 1 uA
4.1 V
V
uA
ON -time
Minimum off time 590 ns
Internal FB voltage Vref 0.75 V
Input bias current 200 nA
Line regulation VCC from 4.5V to 5.5V -1 1 %
OUTPUT voltage
Output range 0.75 3.3 V
VOUT shut down discharge
resistance ENSW/MODE=GND 30 ohm
Soft start time 1.5 ms
PGOOD high rising threshold 90 % Vref
PGOOD propagation delay
filter NOTE1 2 us
PGOOD hysteresis
impedance
bias current
PFM/Non Synchronous Mode
Ultrasonic Mode
Synchronous Mode
Shutdown mode 0 0.8 V
VIN=9V,VOUT=0.75V,Rton=
1Mohm 390 ns
5 %
13 ohm
80%
VCC
60%
VCC
Leave it open or use limits in
spec 2
ENSW/MODE=VCC 5 uA
ENSW/MODE=GND -5 uAInput bias current
VCC+0
.3V V
80%
VCC V
60%
VCC V
Rev.1.6
03/06/09
3
Page 4
NX9548
Current Limit
Under voltage
FB threshold
70
%Vref
Over voltage
Over voltage tripp point
125
%Vref
Internal Schottky Diode
Ouput Stage
DSON
PARAMETER SYM Test Condition Min TYP MAX Units
SW zero cross comparator
Offset voltage
Ocset setting current 24 uA
Over temperature
Threshold NOTE1
Hysteresis 15
Forward voltage drop forward current=50mA 500 mV
5 mV
155
o
C
o
C
High Side MOSFET R
Low Side MOSFET R
20 mohm
17 mohm
Output Current 9 A
NOTE1: This parameter is guaranteed by design but not tested in production(GBNT).
Rev.1.6
03/06/09
4
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PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1-3
S1
Source of high side MOSFET.These pins must be connected directly to the drain of
low side MOSFET via a plane connection.
NX9548
4,30-32
PAD2
5-8,19,
PAD3
9-14
15
16
17
18
20
D1
D2
S2
PVCC
OCP
NC
HDRV
BST
Drain of high side MOSFET.
Drain of low side MOSFET and the controller pin out SW.
Source of low side MOSFET and need to be directly connected to power ground via
multiple vias.
This pin provides the voltage supply to the lower MOSFET drivers. Place a high
frequency decoupling capacitor 1uF X5R from this pin to GND.
This pin is connected to the drain of the external low side MOSFET via resistor and
is the input of the over current protection(OCP) comparator. An internal current source
is flown from this pin to the external resistor which sets the OCP voltage across the
Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rdson. Once this threshold is reached the chip is latched out.
Not used.
High side gate driver output which needs to be connected to high side MOSFET gate
HG pin. A small value resistor may be placed between two pins to slow down the high
side MOSFET, reducing the ringing on SW nodes.
This pin supplies voltage to high side FET driver. A minimum high freq 0.47uF ceramic capacitor is placed as close as possible to and connected to this pin and
respected pin 19.A 4.7ohm resister is recommended in series with this capacitor.
22
23
24
25
26
27
21,28
PAD1
29
Rev.1.6
03/06/09
ENSW/
MODE
VOUT
TON
VCC
FB
PGOOD
GND
HG
Switching converter enable input. Connect to VCC for PFM/Non synchronous mode,
connected to an external resistor divider equals to 70%VCC for ultrasonic, connected to GND for shutdown mode, floating or connected to 2V for the synchronous
mode.
This pin is directly connected to the output of the switching regulator and senses the
VOUT voltage. An internal MOSFET discharges the output during turn off.
VIN sensing input. A resistor connects from this pin to VIN will set the frequency. A
1nF capacitor from this pin to GND is recommended to ensure the proper operation.
This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is
placed as close as possible to this pin and ground pin.
This pin is the error amplifiers inverting input. This pin is connected via resistor
divider to the output of the switching regulator to set the output DC voltage from
0.75V to 3.3V.
PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc or
lower voltage. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state.
Ground pin.
High side MOSFET gate.
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BLOCK DIAGRAM
NX9548
VCC
ENSW
/MODE
TON
FB
VOUT
VCC
VREF=0.75V
soft start
1M
1M
Bias
ON time
pulse
genearation
OCP_COMP
start
MODE
SELECTION
OVP
4.3/4.1
Mini offtime
400ns
POR
FBUVLO_latch
Disable
PFM_nonultrasonic
Sync
1.25*Vref/0.7VREF
Disable_B
Thermal
shutdown
R
Q
S
FB
start
HD
OCP_COMP
POR
ODB
FET Driver
HD_IN
Diode
emulation
HD
BST
HDRV
HG
D1
S1
D2
S2
PVCC
OCP
GND
PGOOD
Rev.1.6
03/06/09
FBUVLO_latch
SS_finished
Figure 2 - Simplified block diagram of the NX9548
0.9*Vref
0.7*Vref
FB
start
VOUT
VOUT
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Demoboard design and waveforms
sdfd
NX9548
PGOOD
5V
C6
1u
R5 10
R6
10k
C7
1u
27
PGOOD
15
PVCC
25
VCC
ENSW
22
/MODE
29
HG
18
HDRV
24
TON
4,30-32,PAD2
D1
N X 9 5 4 8
GND
21,28,PAD1
BST
OCP
VOUT
FB
S2
20
1-3
S1
5-8,19,PAD3
D2
16
23
26
9-14
R1 1M
C3
1n
C1
2 x 4.7uF,25V,X5R
R6 4.7
C4
DO5010H-332MLD
1u
L1 3.3uH
R2
10k
C8
330p
VIN 8V~22V
C2
10uF,25V,X5R
Vout 1.5V/9A
2R5TPE330MC
C5 330uF
R3
7.5k
R4
7.5k
Rev.1.6
03/06/09
Figure 3 - Demoboard schematic of NX9548
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Page 8
Bill of Materials
Item Quantity Reference Part Manufacturer
1 2 C1 4.7uF,25V,X5R
2 1 C2 10uF,25V,X5R
3 1 C3 1nF,50V,X7R
4 3 C4,C6,C7 1uF,10V,X7R
5 1 C5 2R5TPE330MC SANYO
6 1 C8 330pF
7 1 R1 1MEG
8 2 R2,R6 10k
9 2 R3,R4 7.5k
10 1 R5 10
11 1 R6 4.7
12 1 L1 DO5010H-332MLD COILCRAFT
13 1 U1 NX9548 NEXSEM INC.
NX9548
Rev.1.6
03/06/09
8
Page 9
Demoboard Waveforms
NX9548
Fig.4 Startup when 5V is present and 12V bus is
started up, output load current is at 1.5A.
Fig.6 Shutdown when 12V bus is present and 5V is
shuted down.
Fig.5 Startup when 12V bus is present and 5V is
started up.
Fig.7Output ripple (VIN=15V IOUT=1.2A)
Fig.8 5A step response(VIN=5V)
Rev.1.6
03/06/09
Fig.9 5A step response(VIN=20V)
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EFFICIENCY
EFFICIENCY
Demoboard Waveforms(Cont')
VIN=12V, VOUT=1.5V
92.00%
90.00%
88.00%
86.00%
84.00%
82.00%
80.00%
78.00%
10 100 1000 10000
OUTPUT CURRENT(mA)
NX9548
79.00%
78.60%
78.20%
77.80%
77.40%
77.00%
Fig.10 Output efficiency at different load
IOUT=10A, VOUT=1.5V
0 5 10 15 20 25
VIN(V)
Rev.1.6
03/06/09
Fig.11 Output efficiency at different VIN bus voltage
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Page 11
NX9548
TONOUT
VTON
(
)
INOUT ON
(22V-1.5V)310nS
SOUT
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX9548, the
schematic is figure 1.
VIN = 8 to 22V
VOUT=1.5V
FS=220kHz
IOUT=9A
DVRIPPLE <=60mV
DVDROOP<=60mV @ 3A step
On_Time and Frequency Calculation
The constant on time control technique used in
NX9548 delivers high efficiency, excellent transient dynamic response, make it a good candidate for step down
notebook applications.
An internal one shot timer turns on the high side
driver with an on time which is proportional to the input
supply VIN as well inversely proportional to the output
voltage VOUT. During this time, the output inductor charges
the output cap increasing the output voltage by the
amount equal to the output ripple. Once the timer turns
off, the Hdrv turns off and cause the output voltage to
decrease until reaching the internal FB voltage of 0.75V
on the PFM comparator. At this point the comparator
trips causing the cycle to repeat itself. A minimum off
time of 400nS is internally set.
The equation setting the On Time is as follows:
12
TON
F
4.4510RV
=
V
OUT
=
S
×
IN
In this application example, the RTON is chosen
to be 1Mohm, when VIN=22V, the TON is 310nS and F
−
×××
V0.5V
−
IN
...(1)
...(2)
is around 220kHz.
Output Inductor Selection
The value of inductor is decided by inductor ripple
current and working frequency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response
and lower efficiency. The ripple current is a design freedom which can be decided by design engineer according to various application requirements. The inductor value
can be calculated by using the following equations:
L=
I=kI××
V-VT
OUT
RIPPLEOUTPUT
I
RIPPLE
...(3)
where k is percentage of output current.
In this example, inductor from COILCRAFT
DO5010H-332 with L=3.3uH is chosen.
Current Ripple is recalculated as below:
(V-V)T
I=
RIPPLE
INOUT ON
=
L
OUT
3.3uH
×
×
...(4)
=1.925A
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both conditions.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(5).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
is the value of output capacitors.
OUT
Typically POSCAP is recommended to use in
NX9548's applications. The amount of the output voltage
ripple is dominated by the first term in equation(5) and
the second term can be neglected.
S
For this example, one POSCAP 2R5TPE330MC
RIPPLE
××
8FC
...(5)
Rev.1.6
03/06/09
11
Page 12
NX9548
ESR=15.5m
==Ω
ERIPPLE
12m1.925A
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
23.76H
=µ
Estep
ESRI
0.9
is chosen as output capacitor, the ESR and inductor
current typically determines the output voltage ripple.
When VIN reach maximum voltage, the output voltage
ripple is in the worst case.
desire
∆
RIPPLE
I1.925A
∆
RIPPLE
30mV
...(6)
V
If low ESR is required, for most applications, multiple capacitors in parallel are needed. The number of
output capacitor can be calculate as the following:
ESRI
N
=
N
=
∆
Ω×
30mV
×∆
V
RIPPLE
...(7)
N =0.77
The number of capacitor has to be round up to a
integer. Choose N =1.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V
droop
∆V
<
@step load DI
STEP
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot
when load from high load to light load with a DI
STEP
transient load, if assuming the bandwidth of system is high
enough, the overshoot can be estimated as the following
equation.
V
VESRI
overshootstep
OUT
2LC
××
OUT
...(8)
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(9
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
...(10)
L
crit
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤
is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(11)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(12)
For example, assume voltage droop during transient is 60mV for 3A load step.
If one POSCAP 2R5TPE330MC(330uF, 12mohm
ESR) is used, the crticial inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
12m3300F1.8V
3A
The selected inductor is 3.3uH which is smaller
than critical inductance. In that case, the output voltage
transient mainly dependent on the ESR.
number of capacitor is
∆
Ω×
60mV
V
×∆
tran
N
=
12m4.5A
=
=
Choose N=1.
Based On Stability Requirement
ESR of the output capacitor can not be chosen too
low which will cause system unstable. The zero caused
Rev.1.6
03/06/09
12
Page 13
by output capacitor's ESR must satisfy the requirement
SW
F
2ESRC4
IID1-D
OUT
REF
2REF
OUT REF
as below:
NX9548
Vout
F
=≤
ESR
1
×π××
OUT
...(13)
Besides that, ESR has to be bigger enough so
that the output voltage ripple can provide enough voltage
ramp to error amplifier through FB pin. If ESR is too
small, the error amplifier can not correctly dectect the
ramp, high side MOSFET will be only turned off for minimum time 400nS. Double pulsing and bigger output ripple
will be observed. In summary, the ESR of output capacitor has to be big enough to make the system stable, but
also has to be small enough to satify the transient and
DC ripple requirements.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
=××
RMSOUT
DTF
=×
ONS
...(14)
When VIN = 22V, VOUT=1.5V, IOUT=9A, the result of
input RMS current is 2.3A.
For higher efficiency, low ESR capacitors are
recommended. One 10uF/X5R/25V and two 4.7uF/X5R
/25V ceramic capacitors are chosen as input capacitors.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at
0.75V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.75V
when the output voltage is at the desired value.
The following equation applies to figure 12, which
shows the relationship between
age divider.
V ,
V and volt-
R2
Fb
R1
Vref
Figure 12 - Voltage Divider
RV
R=
1
where R
of R1 value can be set by voltage divider.
Mode Selection
NX9548 can be operated in PFM mode, ultrasonic
PFM mode, CCM mode and shutdown mode by applying different voltage on ENSW/MODE pin.
When VCC applied to ENSW/MODE pin, NX9548
is In PFM mode. The low side MOSFET emulates the
function of diode when discontinuous continuous mode
happens, often in light load condition. During that time,
the inductor current crosses the zero ampere border and
becomes negative current. When the inductor current
reaches negative territory, the low side MOSFET is
turned off and it takes longer time for the output voltage
to drop, the high side MOSFET waits longer to be turned
on. At the same time, no matter light load and heavy
load, the on time of high side MOSFET keeps the same.
Therefore the lightier load, the lower the switching frequency will be. In ultrosonic PFM mode, the lowest frequency is set to be 25kHz to avoid audio frequency
modulation. This kind of reduction of frequency keeps
the system running at light light with high efficiency.
In CCM mode, inductor current zero-crossing sensing is disabled, low side MOSFET keeps on even when
inductor current becomes negative. In this way the efficiency is lower compared with PFM mode at light load,
but frequency will be kept constant.
×
V-V
is part of the compensator, and the value
2
...(15)
Rev.1.6
03/06/09
13
Page 14
NX9548
SWLDSON
IR+V
IIR/R
R10k
===Ω
Over Current Protection
Over current protection for NX9548 is achieved by
sensing current through the low side MOSFET. An typical internal current source of 24uA flows through an external resistor connected from OCSET pin to SW node
sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as
V=-IR×
The voltage at pin OCSET is given as
×
OCPOCPSW
When the voltage is below zero, the over current
occurs as shown in figure below.
vbus
OCP
I
24uA
OCP
R
OCP
comparator
SW
OCP
reset VCC or EN is necessary.
Under Output Voltage Protection
Typically when the FB pin voltage is under 70% of
V
, the high side and low side MOSFET will be turned
REF
off. To resume the switching operation, VCC or ENSW
has to be reset.
Figure 13 - Over Voltage Protection
The over current limit can be set by the following
equation.
=×
SETOCPOCPDSON
The low side MOSFET R
is 24mΩ at the OCP
DSON
occuring moment, and the current limit is set at 10A,
then
IR
SETDSON
OCP
Choose R
×
I24uA
OCP
OCP
=10kΩ
10A24m
×Ω
Power Good Output
Power good output is open drain output, a pull up
resistor is needed. Typically when softstart is finised
and FB pin voltage is over 90% of V
, the PGOOD
REF
pin is pulled to high after a 1.6ms delay.
Over Output Voltage Protection
Typically when the FB pin voltage is over 125% of
V
, the high side MOSFET will be turned off and the
REF
low side MOSFET will be latched to be on to discharge
the output voltage. To resume the switching operation,
Rev.1.6
03/06/09
14
Page 15
Demoboard Schematic
NX9548
VBUS
VSW
VIN
C11
0.1u
R18
7.5k
5V
22
HG
HDRV
BST
GND2
GND(PAD1)
D2-5
OCP
D1(PAD2)
D1-1
D1-2
D1-3
CIN2
4.7u/25V
EN
NX9548 MLPQ32
S1-11S1-22S1-3
CIN3
4.7u/25V
29
18
20
R8
28
4.7
G
19
R7
16
6k
D1
30
31
32
CIN1
10u/25V
R16
7.5k
C19
330p
21
26
FB
23
VOUT
GND1
17
NC
U1
3
D1-4
4
D2-15D2-26D2-37D2-4
R13
10
C24
470p
8
24
TON
PGOOD
PVCC
VCC
S2-6
S2-5
S2-4
S2-3
S2-2
S2-1
D2(PAD3)
D2
R3
1M
C10
1n
VSW
VBUS
27
15
25
14
13
12
11
10
9
PGOOD
5V
R5
10
C2
1u
R17
100k
C17
1u
5V
L2
12
DO5010H-332HC
VOUT
CO1
2R5TPE330MC
CO2
4.7u
VOUT
GND
Figure 14 - NX9548 schematic for the demoboard layout
Rev.1.6
03/06/09
15
Page 16
Demoboard Layout
NX9548
Figure 15 Top layer
Rev.1.6
03/06/09
Figure 16 Ground layer
16
Page 17
NX9548
Figure 17 Power layer
Rev.1.6
03/06/09
Figure 18 Bottom layer
17
Page 18
MCM 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS
NX9548
Rev.1.6
03/06/09
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
18
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