Page 1
Evaluation board available.
NEXSEM
2A SOURCE/SINK LDO & SYNCHRONOUS SWITCHING
DESCRIPTION
The NX2820 is a combination of synchronous Buck controller IC and 2A internal source/sink LDO regulator. It is
designed for DDR memory application where typically
synchronous controller provides either a 2.5V Vddq for
DDR1 type memory(1.8V for DDRII) and the internal LDO
supplies Vtt from the Vddq supply.
NX2820 features internal digital soft start,VCC
undervoltage lock out, bus enable as well as over current limit by sensing low side MOSFET Rdson. The
source and sink LDO is protected by thermal shutdown
and current limit. The NX2820 is housed in 16 pin MLPQ
Package which provides small yet good thermal capability ideal for computer or graphic card applications.
NX2820
CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product
FEATURES
n Internal 2A Souce and Sink LDO
n Internal current Limit and thermal shutdown for LDO
n Shut down LDO by pulling down Refin pin
n Bus voltage operation from 4V to 25V
n Loss-Less Current Limit via Rdson of Low side FET
n Internal Digital Soft Start Function
n Programmable start up voltage for BUS Supply
using Enable pin
n Shut Down PWM controller via EN pin
n Pb-free and RoHS compliant
APPLICATIONS
n DDR I and II application
n Graphic Card on board converters
n Vddq and VTT Supply in mother board applica-
tions
TYPICAL APPLICATION
ON
OFF
10k
10
R10
C11
1uF
4
VCC
PVCC
R9
6.8k
5
EN
0.9V
C8
560uF,7mohm
4SEPC560M
5 mA
R8
1.24k
C9
1uF
8
10
6
VTT
GNDVTT
VREF-OUT
2N3904
R11
BST
HDRV
SW
OCP
LDRV
PGND
N X 2 8 2 0
COMP
VDDQ
REF-IN
AGND
3
C1
12
1uF
13
15
2kR1
16
11
10
2
FB
R5
1
10k
9
7
C10
1uF
C12
1N5817
C4
0.1uF
ON
VIN
+5V
M114
L2 2.2uH DO5010P-222HC
M2
C5
5.6nF
100pF
OFF
R12
10k
L1 1uH
DO3316P-102
180uF
28mohm
16SVPA180M
1.87k
2.2nF
M3
VIN
C3C2
39uF
31mohm
16SVPA39MAA
R2
R3
15.8k
C6
R4
12.7k
R6
10k
R7
10k
+12V
C7
680uF,6mohm
2R5TPD680M6
VOUT
+1.8V/9A
Figure1 - Typical application of 2820
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2820CMTR 0 to 70oC MLPQ-16L 300kHz Yes
Rev. 2.0
12/19/05
www.nexsem.com
1
Page 2
NEXSEM
46CW
θ≈/
REF
CC
Supply Current
ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
PACKAGE INFORMATION
16-LEAD PLASTIC MLPQ
NX2820
COMP
FB
AGND
VCC
16 15 14
1
2
3
4
SW
OCP
GND-VTT
65
EN
17
REF-OUT
HDRV
13
7
REF-IN
8
BST
VTT
12
11
10
9
LDRV
PGOOD
PGND
VDDQ
o
JA
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, V
125oC. Typical values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
PWM Controller Section
Reference Voltage
Ref Voltage V
Ref Voltage line regulation 0.2 %
Supply Voltage(Vcc)
VCC recommended Voltage V
V
CC
(Static)
ICC (Static) mAOutputs not switching 5.5
BST-VSW
=12V, ENSW=3V, and TA = 0 to
0.8 V
4.5 5.5
V
VCC Supply Current
(Dynamic)
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V
Rev. 2.0
12/19/05
I
CC
(Dynamic)
Freq=300KHz,
LOADHDRV
C
=2500PF
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14 mA
4
V
2
Page 3
NEXSEM
S
RAMP
High Side Driver, Hdrv, BST,
SW (CL=3300pF)
BST-VSW
Section
Reference Buffer
capability
Output Voltage
OS
Load Regulation
2A
Hdrv going Low to Ldrv going
Ldrv going Low to Hdrv going
NX2820
PARAMETER SYM Test Condition Min TYP MAX Units
Oscillator (Rt)
Frequency F
Ramp-Amplitude Voltage V
Max Duty Cycle F=300Khz
Min duty Cycle
Min ON time NOTE2 70 nS
Error Amplifiers
Open Loop Gain NOTE2 65 dB
Input Bias Current Ib 0.28 uA
EN & SS
Soft Start time Tss Fs=300KHz 6.8 mS
Enable HI Threshold 1.2 V
Enable Hysterises 120 mV
300 KHz
1 V
95 %
0
%
Output Impedance, Sourcing
Current
Output Impedance , Sinking
Current
Rise Time THdrv(Rise) VBST-VSW=4.6V 20 ns
Fall Time THdrv(Fall) V
Deadband Time
Low Side Driver , Ldrv,
Output Impedance, Sourcing
Current
Output Impedance , Sinking
Current
N
Rise Time TLdrv(Rise) 10% to 90% 20 ns
Fall Time TLdrv(Fall) 90% to 10% 20 ns
Deadband Time Tdead(H to
OCP Adjust
Ocset current
Blank time before activating
Sounce and Sink LDO
R
(Hdrv) V
source
R
(Hdrv) V
sink
Tdead(L to
H)
R
(Ldrv) I=200mA pulse 1.1 ohm
source
R
(Ldrv) I=200mA pulse 0.5 ohm
source
L)
BST-VSW
pulse
BST-VSW
pulse
8 Clock cycles of 300 Khz 40 uS
=4.6V,I=200mA
=4.6V, I=200mA
=4.6V 20 ns
High, 10% to 10%
High, 10% to 10%
1.1 ohm
50
50
100 uA
ohm0.8
ns
ns
Vref_out current driving
Output Offset Voltage V
Rev. 2.0
12/19/05
1uF at Vref_out 3 mA
IOUT=0A -20 0 20 mV
IL:From 0A to
IL:From 0A to-2A
-20 0 20 mV
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NEXSEM
PARAMETER
SYM
Test Condition
Min
TYP
MAX
Units
Input Voltage
Input voltage Range (DDRI/II)
Vddq
1.7
2.5/1.8
V
Short Circuit Protection
Protection
Temperature
Temperature hysteresis
Refin Shutdown Function
Output=Low
0.2
NX2820
Current Limit
Over Temperature
Thermal Shutdown
Thermal Shutdown
Shutdown Threshold Trigger V
NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).
I
LIMIT
T
SD
2.2 3.1 A
3.3V<=V
3.3V<=V
Ouput=High 0.6
<=5V 150 °C
CNTL
<=5V 35 °C
CNTL
Rev. 2.0
12/19/05
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Page 5
NEXSEM
PIN DESCRIPTIONS
Pin# Pin Symbol Pin Description
1 COMP These pins are the outputs of error amplifiers and are used to compensate the
respective voltage control feedback loops.
2 FB This pin is the error amplifiers inverting input. These pins are connected via resistor
dividers to the output of the switching regulators to set the output DC voltage.
3 AGND Analog ground.
4 Vcc IC’s supply voltage. This pin biases the internal logic circuits. A high freq 1uF
ceramic capacitor is placed as close as possible to and connected to this pin and
ground pin. The maximum rating of this pin is 16V.
5 EN A resistor divider is connected from the respective switcher BUS voltages to these
pins that holds off the controllers soft start until this threshold is reached. An
external low cost MOSFET can be connected to this pin for external enable control.
6 REF-OUT Reference buffer output. It can driver up to 5mA load.
7 REF-IN Source and Sink LDO reference input. A small ceramic capacitor is recommended
to put this pin to ground. The LDO can be shut down by pulling this pin to be below
0.2V.
NX2820
8 VTT Output of source and sink LDO.
9 VDDQ Input supply for the intenral source and sink LDO.
10 PGND Power ground pin for low side drivers.
11 LDRV Low side gate driver outputs.
12 PVcc Supply voltage for the low side fet drivers. A high frequency 1uF ceramic cap must
be connected from this pin to the PGND pin as close as possible to the pins.
13 BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic
capacitor is placed as close as possible to and connected to these pins and
respected SW pins.
14 HDRV High side gate driver outputs.
15 SW These pin are connected to source of high side FETs and provide return path for
the high side drivers. They are also used to hold the low side drivers low until this
pin is brought low by the action of high side turning off. LDRVs can only go high if
SW is below 1V threshold.
16 OCP This pin is connected to the drain of the external low side MOSFET and is the input
of the over current protection(OCP) comparator. An internal current source of
100uA is flown to the external resistor which sets the OCP voltage across the
Rdson of the low side MOSFET.
17(PAD) GNDVTT VTT ground.
Rev. 2.0
12/19/05
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5
Page 6
NEXSEM
BLOCK DIAGRAM
NX2820
VCC
EN
FB
COMP
GND
REFOUT
1.25/1.15
Bias
Generator
Digital
start Up
1.25V
0.8V
OSC
ramp
PWM Controller
4/3.8
set
UVLO
POR
BST
DrvH
Control
Logic
S
Q
R
POR
OCP
comparator
SW
PVCC
DrvL
PGND
OCP
VDDQ
Rev. 2.0
12/19/05
REFIN
0.4
POR
Current Limit
& Thermal
shutdown
Control Logic
Source and Sink LDO
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VTT
VTT_GND
6
Page 7
NEXSEM
NX2820
1
J4
2
1
J5
2
1
J6
2
1
J7
2
1
J8
2
1
J9
2
REF_OUT
VTT_SD
BUS
5V
VDDQ
REF_OUT
VTT
R2
6.8k
13
R1
1.24k
16
C3
1u
C4
1u
10
U1
VCC
EN_BUS
NX2820-TQFP48L
REF_OUT
BUS
R4
op
C11
.1u
5V
VDDQ
J2
1
234
5
C8
C5
R3
1u
10
42
43
46
47
48
34
33
D1
D1N5819
C6
1u
1.5k
C21
OP
R5
0
IRF3706
SW
R7
R6
0
IRF3706
VD
M1
M2
38
PVCC
BST
HDRV
SW
OCP
NC
LDRV
PGND
16SP100M
L1
DO3316P-102
C20
100u
C7
1u
L2 DO5010P-222HC
R14
OP
C17
OP
2R5TPD680M6
C13
C14OPC15
OP
C16
OP
VDDQ
VTT
J1
234
4
FB
1
AGND
7
COMP
REF_IN
VDDQ
18
Q1
2N7002
25
C12
3.3u
5
1
C2
.1u
C1
4SEPC560M
20
VTT_SEN
22
VTT
21
GND_VTT
Figure 2 - Demo board schematic
C19
C9
100p
5.6uR810k
R11
6.8k
R15
C18
2.2n
1.87k
VTT_SD
R10
12.7k
R13
1k
C10
1u
R9
15.8k
R12
1k
PACKAGE: TQFP48L
Size Document Number Rev
A
Date: Sheet of
2820-01A EVALUATION BOARD SCHEMATIC
1 1Thursday, March 24, 2005
A
Rev. 2.0
12/19/05
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Page 8
NEXSEM
Bill of Materials
Item Quantity Reference Part Manufacture
1 1 C1 4SEPC560M SANYO
2 2 C2,C11 .1u
3 6 C3,C4,C5,C6,C7,C10 1u
4 1 C8 16SP100M SANYO
5 1 C9 5.6u
6 1 C12 3.3u
7 1 C13 2R5TPD680M6 SANYO
8 6 R4,R14,C14,C15,C16,C17,C21 OPEN
9 1 C18 2.2n
10 1 C19 100p
11 1 C20 100u
12 1 D1 D1N5819
13 2 J1,J2 SCOPE TP Tektronics
14 6 J4,J5,J6,J7,J8,J9 CON2
15 1 L1 DO3316P-102 Coilcraft
16 1 L2 DO5010P-222HC Coilcraft
17 2 M1,M2 IRF3706 International Rectifier
18 1 Q1 2N7002
19 1 R1 1.24k
20 2 R2,R11 6.8k
21 1 R3 10
22 3 R5,R6 0
23 1 R7 2k
24 1 R8 10k
25 1 R9 15.8k
26 1 R10 12.7k
27 2 R12,R13 1k
28 1 R15 1.87k
29 1 U1 NX2820-TQFP48L NEXSEM INC
NX2820
Rev. 2.0
12/19/05
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NEXSEM
f
Figure 3 - Vddq output voltage ripple @ 1.8V
NX2820
Figure 4 - Vin(CH3),VDddq(CH1),Vtt(CH2) @ softstart
Figure 5 - Vddq change during transient
Figure 7 - Hiccup current limit with short circuit
Rev. 2.0
12/19/05
Figure 8 - Hiccup current limit with overload
www.nexsem.com
Figure 6 - Vtt change during transient
Vddq
Vtt
Hdrv
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NEXSEM
RIPPLEINS
1
IVF
0.39A12V300kHz
=2.3A
SOUT
==Ω
ESR=8.6m
ERIPPLE
6m2.3A
NX2820
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VIN=12V
VOUT=1.8V
IOUT =9A
DVRIPPLE <=20mV
DVTRAN<=100mV @ 9A step
FS=300kHz
Output Inductor Selection
The selection of inductor value is based on
inductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:
V-VV
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
L=1.9uH
Choose LOUT=2.2uH, then coilcraft inductor
DO5010P-222HC is a good choice.
Current Ripple is calculated as
INOUT OUT
OUT
×
12V-1.8V1.8V1
OUT
OUT
××
××
×
...(1)
V-VV 1
INOUT OUT
LVF
12V-1.8V1.8V1
2.2uH12V300kHz
××
OUTINS
××=
...(2)
I=
RIPPLE
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
∆
tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP
2R5TPD680M6 with 6mΩ are chosen.
integer. Choose N =1.
desire
If low ESR is required, for most applications, mul-
ESRI
N
=
Number of Capacitor is calculated as
Ω×
=
N
N =0.7
The number of capacitor has to be round up to a
20mV
is the value of output capacitors.
OUT
V 20mV
RIPPLE
∆
I2.3A
RIPPLE
×∆
V
∆
RIPPLE
RIPPLE
××
8FC
...(5)
...(3)
...(4)
Rev. 2.0
12/19/05
www.nexsem.com
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NEXSEM
8300kHz100uF
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.82H
=µ
6m680F6.92us
2
=+×τ
NX2820
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.3A
RIPPLE
4.6mV9.6mV13.2mV
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the overshoot when load from high load to light load with a
DI
transient load, if assuming the bandwidth of
STEP
system is high enough, the overshoot can be estimated as the following equation.
VESRI
where τ is the a function of capacitor,etc.
where
=+=
∆V
<
droop
overshootstep
0ifLL
LI
×∆τ=
step
V
OUT
@step load DI
≤
crit
−×≥
2LC
2.3A
××
STEP
V
OUT
××
OUT
...(6)
...(7)
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
transient spec is mostly like to dependent on the ESR
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
where
sient is 100mV for 15A load step.
ESR) is used, the crticial inductance is given as
For example, assume voltage droop during tran-
If the POSCAP 2R5TPD680M6 (680uF, 6mohm
Estep
V2LCV
∆×××∆
tranEtran
0ifLL
LI
×∆τ=
step
V
OUT
ESRCV
L
==
crit
6m680F1.8V
Ω×µ×
≤ is true. In that case, the
V
OUT
≤
crit
−×≥
××
EEOUT
I
∆
step
...(9)
...(10)
9A
The selected inductor is 2.2uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitor is
LI
×∆
step
τ=−×
V
OUT
2.2H9A
µ×
=−Ω×µ=
ESRC
EE
1.8V
ESRCVESRCV
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected out-
Rev. 2.0
12/19/05
××××
==
II
∆∆
stepstep
...(8)
N
6m9A
=+
22.2H680F100mV
×µ×µ×
0.83
=
www.nexsem.com
ESRI
×∆
Estep
V2LCV
∆×××∆
tranEtran
Ω×
100mV
1.8V
V
OUT
(6.92us)
×
2
11
Page 12
NEXSEM
F ...(11)
F ...(12)
F ...(13)
F ...(14)
f
OUT in
Z
VZ
−
[
]
42233
(1sRC)1s(RR)C
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=1.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation is gives a good start. For more margin, more capacitors have to choose after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% up 100% (for ceramic)
more capacitors have to chosen since the ESR of capacitors is so low that the PCB parasitics can affect the
results tremendously. More capacitors have to be selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin.Ideally,the Bode
plot of the closed loop system has crossover frequency
between1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should
be chosen.
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo OSCON and POSCAP, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by voltage mode amplifier.
NX2820
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 15.
The transfer function of type III compensator is
given by:
V
V 1
e
VsR(CC)
OUT 221
e
=×
×+
Zin
R3
C3
1
2RC
×π××
42
1
2(RR)C
×π×+×
2RC
×π××
2R
×π××
=
233
1
33
1
CC
×
12
4
CC
+
12
+××++×
(1sR)1sRC
+××+×
433
Vout
C1
C2
R2
Fb
R1
Vref
CC
×
21
CC
+
21
Zf
R4
( )
Ve
Rev. 2.0
12/19/05
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NEXSEM
LC
F
ESR
F
22.2uH680uF
26m680uF
20.754.1kHz10k
×π×××Ω
210k150kHz
21V25kHz2.2uH680uF
239kHz2.2nF
1.87k
=−Ω
R=12.6k
==Ω
Fp2 =0.5*FS .
4. Set R4 equal to 10k Ω.
5. Calculate C1 and C
NX2820
2.
power stage
LC
F
Gain(db)
40dB/decade
loop gain
ESR
F
20dB/decade
compensator
F
Z1
F
Z2
O
F
F
P1
F
P2
Figure 9 - Type III compensator and its bode plot
C
=
2
=
5.2nF
=
1
2FR
×π××
Z14
1
Choose C2=5.6nF.
C
=
1
=
106pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=100pF.
6. Calculate C3 with the crossover frequency
FO=25kHz.
2VFLC
×π××××
C=
3
=
oscO
VR
×
IN4
×π××××
12V10k
×Ω
=1.9nF
The crossover frequency has to be selected as
FLC<FO<F
and FO<=1/10~1/5F
ESR,
for type III
s
compensator .
1.Calculate the location of LC double pole
and ESR zero
F
=
LC
2LC
×π××
=
.
1
OUTOUT
1
×π××
4.1kHz
=
F
ESR
=
2ESRC
×π××
=
1
OUT
1
×π×Ω×
39kHz
=
2. Set FO =25kHz < F
3. Set Fz1 =0.75*F
LC, FZ2
ESR
= F
Fp1 =F
LC,
ESR
and
Choose C3=2.2nF.
7. Calculate R
R
=
3
2FC
×π××
=
.
2, R3
1
P13
1
×π××
1.85k
=Ω
Choose R3=1.87kΩ.
RR
=−
23
1
2FC
×π××
Z23
1
24.1kHz2.2nF
×π××
15.7k
=Ω
Choose R3=15.8kΩ.
8. Calculate R1 .
RV 15.8k0.8V
× Ω×
2REF
Choose R
1
V-V1.8V-0.8V
OUT REF
=12.7kΩ.
3
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NEXSEM
Gain= ... (15)
F= ... (16)
F= ... (17)
21.5uH4500uF
26.33m4500uF
=10k
××Ω
224.8k0.751.94kHz
NX2820
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
R
3
R
2
z
p
Vout
R2
R1
1
2RC
×π××
31
1
2RC
×π××
32
R3
Fb
Vref
C2
C1
Ve
.
to cancel the double pole effect. C2 introduces a pole to
suppress the switching noise. The following equations
show the compensator pole zero location and constant
gain.
For type II compensator, FO has to satisfy
FLC<F
<<FO<=1/10~1/5F
ESR
s.
The following parameters are used as an example
for type II compensator design, three 1500uF with
19mohm Sanyo electrolytic CAP 6MV1500WGL are
used as output capacitors. Coilcraft DO5010P-152HC
1.5uH is used as output inductor. The other power stage
information is that:
VIN=12V, VOUT=1.8V, IOUT =15A, FS=300kHz.
1.Calculate the location of LC double pole F
and ESR zero F
F
=
LC
2LC
=
.
ESR
1
×π××
OUTOUT
1
LC
×π××
1.94kHz
=
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
Z LCFESRFO
P
F
Figure 10 - Type II compensator and its bode plot
Type II compensator can be realized by simple RC
circuit as shown in figure 16.R3 and C1 introduce a zero
F
ESR
=
2ESRC
=
1
×π××
OUT
1
×π×Ω×
5.6kHz
=
2.Set crossover frequency FO=20kHz>>F
ESR
.
3. Set R2 equal to10k Ω. Based on output voltage,
using equation 18, the final selection of R1 is 20k Ω.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCO
32
VR
inESR
1V220kHz1.5uH
12V6.33m
=24.8k
×π××
××
×π××
Ω
Ω
Choose R3 =24.8k Ω.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=4.4nF
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NEXSEM
p
F
24.8k300kHz
OUT
REF
V
2REF
OUT REF
R1.6V1.6V/(1/16W)40
=×=Ω
IID1-D
NX2820
Choose C1=4.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
=64pF
Choose C2=68pF
1
RF
π××
3s
1
π×Ω×
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation and picture show the relationship
between
value of R1 value can be set by voltage divider.
1.8V, the result of R1 is 8kΩ.
including the resistor divider should be less than 5kΩ to
prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A
minimum load for 5kΩ less (<1/16w for most of application) is recommended to put at the output. For example,
V ,
RV
R=
1
V-V
where R2 is part of the compensator, and the
Choose R2=10kO, to set the output voltage at
and voltage divider..
×
...(18)
Vout
R2
Fb
R1
Vref
Voltage divider
Figure 11 Voltage divider
In general, the minimum output load impedance
in this application,
Vout=1.6V
The power loss is 1/16W less
LOAD
Select minimum load is 1kΩ should be good
enough.
Input Capacitor Selection
Input capacitors are usually a mix of high
frequency ceramic capacitors and bulk capacitors.
Ceramic capacitors bypass the high frequency noise,
and bulk capacitors supply current to the MOSFETs.
Usually 1uF ceramic capacitor is chosen to decouple
the high frequency noise.The bulk input capacitors are
decided by voltage rating and RMS current rating. The
RMS current in the input capacitors can be calculated
as:
=××
RMSOUT
V
OUT
D
=
V
IN
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation
(19), the result of input RMS current is 3.2A.
For higher efficiency, low ESR capacitors are
recommended.
One Sanyo OS-CON 16SVPA180M 16V 180uF
28mΩ with 3.43A RMS rating are chosen as input bulk
capacitors.
...(19)
Power MOSFETs Selection
The NX2601 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, I
=75A,R
loss:conduction loss, switching loss and gate driver loss.
ing the gate capacitor and is dissipated in driver circuits.
=9mΩ,Q
DSON
There are three factors causing the MOSFET power
Gate driver loss is the loss generated by discharg-
GATE
=23nC.
D
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NEXSEM
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
R6.8k
==Ω
SWLDSON
IR+V
IIR/R
R1.35k
===Ω
NX2820
It is proportional to frequency and is defined as:
...(20)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
LGS
is
the low side gate source voltage.
According to equation (3), P GATE =0.07W. This
power dissipation should not exceed maximum power
dissipation of the driver device.
Conduction loss is simply defined as:
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
2
×××
2
K
+
...(21)
where the RDS(ON) will increases as MOSFET
junction temperature increases, K is RDS(ON) tempera-
ture dependency. As a result, RDS(ON) should be
selected for the worst case, in which K equals to 1.4
at 125oC according to IRFR3706 datasheet . Using
equation (4), the result of PTOTAL is 0.54W. Conduction
loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
1
2
...(22)
where IOUT is output current, TSW is the sum of TR and
TF which can be found in mosfet datasheet, and FS is
switching frequency. The result of PSW is 1.5W.
Swithing loss PSW is frequency dependent.
Soft Start and Enable
NX2820 has digital soft start for switching controller and has one enable pin for this start up. When the
Power Ready (POR) signal is high and the voltage at
enable pin is above 1.25V, the internal digital counter
starts to operate and the voltage at positive input of Error
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the desired voltage decided by the feedback resistor divider.
Vbus
+
OFF
ON
10k
R1
ENSW1
1.25/1.15
R2
POR
Digital
start
up
Figure 12 Enable and Shut down the NX2820
with Enable pin.
The start up of NX2820 can be programmed through
resistor divider at Enable pin. For example, if the input
bus voltage is 12V and we want NX2820 starts when
Vbus is above 8V. We can select
R2=1.24k
(8V1.25V)R
1
1.25V
−×
2
The NX2820 can be turned off by pulling down the
Enable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin (ENSW) is below 1.15V,
the digital soft start is reset to zero. In addition, all the
high side and low side driver is off and no negative spike
will be generated during the turn off.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2820, the current through OCP pin is
I
=100uA. When synchronous FET is on, the voltage
OCP
at node SW is given as
V=-IR×
The voltage at pin OCP is given as
×
OCPOCPSW
When the voltage is below zero, the over current
occurs. The over current limit can be set by the following
equation
=×
SETRTOCPDSON
If the MOSFET R
is set at 15A, then
IR 15A9m
× ×Ω
SETDSON
OCP
Choose R
I100uA
OCP
RT
=1.5kΩ
=9mΩ, and the current limit
DSON
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NEXSEM
NX2820
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other by-
passing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
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NEXSEM
TYPICAL APPLICATION
10
R10
C11
1uF
4
VCC
PVCC
HDRV
LDRV
PGND
N X 2 8 2 0
COMP
VDDQ
REF-IN
AGND
3
BST
SW
OCP
FB
ON
OFF
10k
R9
5k
5
EN
0.9V
C8
560uF,7mohm
4SEPC560M
5 mA
1uF
R8
5k
8
VTT
10
GNDVTT
6
VREF-OUT
C9
2N3904
R11
NX2820
VIN
+5V
15nF
120pF
OFF
M114
M2
C5
R12
10k
L1 1uH
DO3316P-102
C2
2 x(16SVPA150MAA
150uF,25mohm)
L2 2.2uH DO5010P-222HC
M3
C3
39uF,31mohm
16SVPA39MAA
R3
10k
R4
8k
R6
10k
R7
10k
VIN
+5V
VOUT
+1.8V/9A
C7
3 x (6MV1500WGL
1500uF,19mohm)
C1
12
1uF
1uF
C10
1.6kR1
R5
8.87k
C12
1N5817
C4
0.1uF
ON
13
15
16
11
10
2
1
9
7
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