Page 1
NX2715
SINGLE CHANNEL MOBILE PWM CONTROLLER WITH NMOS
LDO CONTROLLER, PGOOD INDICATOR AND ENABLE
ADVANCE DATA SHEET
Pb Free Product
DESCRIPTION
The NX2715 controller IC is a compact synchronous
Buck controller IC with 16 lead MLPQ package designed for step down DC to DC converter applications with feedforward functionality. Voltage
feedforward provides fast response, good line regulation and nearly constant power stage gain under wide
voltage input range. The NX2715 controller is optimized
to convert single supply up to 24V bus voltage to as
low as 0.8V output voltage. Internal UVLO keeps the
controller off until the bus supply voltage exceeds 7V
where internal digital soft starts get initiated to ramp
up output. The NX2715 employs NMOS LDO controller, programmable current limiting and FB UVLO followed by latchout feature. Other features include: 5V
gate drive, programmable frequency, over voltage protection, adaptive deadband control and Vcc under voltage lockout.
MBR0530T1
VIN3
+5V
8
VIN
1uF
13
PVCC
1uF
10
14
100k
(PAD)
9
4
5
VCC
EN
RT
PGOOD
AGND
1uF
16
BST
0.1uF
1
HDRV
15
SW
6k
10
OCP
3
LDRV
2
PGND
11
FB
12
COMP
N X 2 7 1 5
6
LDO OUT
7
LDO FB
FEATURES
n Bus voltage operation from 7V to 24V
n Less than 1uA shutdown current with Enable low
n Excellent dynamic response with input voltage
feed-forward and voltage mode control
n Programmable switching frequency
n Internal digital soft start function
n Programmable current limit triggers latch out
n FB UVLO followed by latch out feature
n NMOS LDO controller available
n Power Good indicator available
n Start into precharged output
n Pb-free and RoHS compliant
APPLICATIONS
n Notebook PC
n Graphic Card on board converters
n On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Set Top Box and LCD Display
TYPICAL APPLICATION
VIN1
3.9nF
2.7nF
4.22k
1k
12.4k
2.7k
+7V to 20V
6.98k
MTD3055
1k
2*2R5TPE330MC
22uF ceramic
VOUT1
+1.25V@10A
VOUT2
+1V@2A
2.49k
1nF
33uF(25V POSCAP)
Q1
1.5uH
Q2
18nF
Figure1 - Typical application of NX2715
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2715CMTR 0 to 70oC MLPQ -16L 200kHz to 1MHz Yes
Rev. 1.4
01/08/08
1
Page 2
NX2715
CW
θ≈46/
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V
VIN to GND ........................................................ -0.3V to 25V
BST to GND Voltage ......................................... -0.3V to 35V
SW to GND ....................................................... -2V to 35V
All other pins ..................................................... -0.3V to 6.5V
Storage Temperature Range ................................ -65oC to 150oC
Operating Junction Temperature Range ................ -40oC to 125oC
ESD Susceptibility ............................................ 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
16-LEAD PLASTIC MLPQ
o
HDRV
PGND
LDRV
RT
JA
BST
SW
VCC
PVCC
17
7
LDO-FB
LDO-OUT
13
COMP
12
FB
11
OCP
10
EN
9
8
VIN
16
15 14
1
2
3
4
5
PGOOD
AGND
6
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical
values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
REF
Ref Voltage line regulation 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
Operating quiescent current I
Shut down current I
SD
CC
Q
EN=HIGH 3
EN=LOW
4.75 5.25
Vcc UVLO
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V
0.8
4.4
V
V
5
1
mA
uA
V
Rev. 1.4
01/08/08
2
Page 3
NX2715
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
Supply Voltage(Vin)
Vin Voltage Range V
in
7 25
Input Voltage Current Vin=24V 24 40 uA
Shut Down Current EN=LOW
1
Vin UVLO
Vin-Threshold Vin_UVLO Vin Rising
6
Vin-Hysteresis Vin_Hyst Vin Falling 0.5 V
Oscillator (Rt)
Frequency F
Frequency Over Vin
Ramp-Amplitude Voltage V
RAMP
S
RT=open 200 KHz
-5
5
Vin=20V 2 V
Ramp Offset 0.8 V
Ramp/Vin Gain 0.1 V/V
Max Duty Cycle
Min on time
88 %
150
Error Amplifiers
Transconductance 2500 umho
Input Bias Current Ib 100 nA
Comp SD threshold 0.3 V
Vref and Soft Start
Soft Start time Tss RT=open 10 mS
High Side
R
(Hdrv) I=200mA
source
1 ohmOutput Impedance , Sourcing
Current
Output Impedance , Sinking
R
(Hdrv) I=200mA
sink
0.8
Current
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
N
Deadband Time Tdead(L to
H)
High, 10% to 10%
30 ns
V
uA
V
%
nS
ohm
Low Side Driver
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
OCP Adjust
OCP current setting 32 uA
Enable
Enable HI Threshold
Enable LOW Threshold
Rev. 1.4
01/08/08
R
(Ldrv) I=200mA 1 ohm
source
R
(Ldrv) I=200mA 0.5 ohm
sink
30 ns
High, 10% to 10%
1.4
V
0.4
V
3
Page 4
NX2715
Power Good(Pgood)
FBUVLO
Over temperature
C
C
LDO Controller
Low Output Voltage
0.2 V
Over Voltage Protection
PARAMETER SYM Test Condition Min TYP MAX Units
Threshold Voltage as % of
FB ramping up 90 %
Vref
Hysteresis 5 %
Feedback UVLO threshold percent of nominal 65 70 75 %
Threshold
150
Hysteresis 20
o
o
FB Pin- Bias Current 100 nA
LDO FB Voltage 0.8 V
LDO FB UVLO percent of nominal 65 70 75 %
High Output Voltage VIN=12V 10.2 V
High Output Source Current 3 mA
Threshold Voltage as % of
FB ramping up 130 %
Vref
Hysteresis 45 %
Rev. 1.4
01/08/08
4
Page 5
PIN DESCRIPTIONS
PIN SYMBOL PIN DESCRIPTION
This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed
VCC
BST
as close as possible to and connected to this pin and ground pin.
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic
capacitor is placed as close as possible to and connected to this pin and SW pin.
NX2715
AGND
FB
COMP
SW
HDRV
LDRV
VIN
EN
LDO FB
Analog ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor divider to
the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to compensate
the voltage control feedback loop.
This pin is connected to source of high side FETs and provide return path for the high
side driver.
High side gate driver output.
Low side gate driver output.
Bus voltage input provides power supply to oscillator and VIN UVLO signal.
Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down
the controller and resets the soft start.
LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal
comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP
circuitry.
LDO OUT
Rev. 1.4
01/08/08
PGOOD
OCP
PGND
PVCC
RT
LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The
maximum rating of this pin is 16V.
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI
state.
This pin is connected to the drain of the external low side MOSFET and is the input of the
over current protection(OCP) comparator. An internal current source is flown to the
external resistor which sets the OCP voltage across the Rdson of the low side MOSFET.
Current limit point is this voltage divided by the Rds-on.
Power ground.
Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to GND
directly.
Oscillator's frequency can be set by using an external resistor from this pin to GND.
When RT pin is open, the frequency is 200kHz.
5
Page 6
BLOCK DIAGRAM
NX2715
VCC
VIN
RT
FB
COMP
AGND
Vp
Bias
Generator
START
Digital
start Up
Vp
Dis_EA
4.4/4.2
1.25V
0.8V
6/5.75
COMP
0.3V
SS_1/4_done
Dis_EA
SS_half_done
0.6V
CLAMP
EN
OSC
VIN
EN
Hiccup
S
R
POR
R
Latchout logic
POR
Q
latch
Reset dominant
FB
1.30Vref
/0.85Vref
START
START
DISABLE
OVP
PWM
FB
0.85Vref
/0.90Vref
START
FET Drivers
SS_half_done
32uA
VCC
PGOOD
BST
DrvH
SW
PVCC
DRVL
PGND
70%*Vp
FB
OCP
EN
Rev. 1.4
01/08/08
DISABLE
0.6V
SS_1/4_done
70%*Vp
VpLDO
Vp
Figure 2 - Simplified block diagram of the NX2715
LDO OUT
LDO FB
6
Page 7
VIN3
+5V
NX2715
VIN1
3.9nF
1k
12.4k
2.7k
+7V to 20V
6.98k
MTD3055
1k
VOUT1
+1.25V@10A
2*2R5TPE330MC
VOUT2
+1V@2A
22uF ceramic
MBR0530T1
8
1uF
1uF
10
1uF
VIN
13
PVCC
14
VCC
BST
HDRV
SW
OCP
LDRV
PGND
FB
COMP
16
1
15
10
3
2
11
12
0.1uF
6k
2.49k
N X 2 7 1 5
9
EN
4
RT
LDO FB
6
7
100k
(PAD)
5
PGOOD
AGND
LDO OUT
33uF(25V POSCAP)
Q1 FDS8878
1.5uH
Q2 FDS6676AS
18nF
1nF
2.7nF
4.22k
Rev. 1.4
01/08/08
Figure 3 - Simplified Demo board schematic
7
Page 8
NX2715
M4
MTD3055
JLDO_OUT
234
LDO_OUT
1
GNDLDO
1
VIN
5V
VIN
C20
10u (cer)
1
5
C17
0.1u
5V
OUT
C18
22u (cer)
1V
R13
1k
R14
100k
R15
100k
R18
open
R17
0
C6
2.7n
R4
2.7k
R12
4.22k
C11
1u
R16
open
R19
open
8
5
9
6
7
4
C1
1u
14
U1
VIN
PGOOD
EN
LDO_OUT
LDO_FB
RT
R1
10
VCC
13
BST
PVCC
HDRV
SW
OCSET
LDRV
C5
1u
16
1
15
10
3
NX2715
2
PGND
11
FB
12
COMP
PAD
17
D1
MBR0530T1
R5
0
C2
0.1u
R2
6k
C19
open
R6
0
C4
18n
C3
1n
R3
2.49
C8
0.1u
4
5V
C9
25TQC33M
L2
C10
470p
R7
10
L1
SHORT
OUT
C16
3.9n
R9
1k
C12
open
1
C15
0.1u
C13
2R5TPE330MC
R10
6.98k
R11
12.4k
VDD
C7
0.1u
5
6
4
M3B
56789
M1
4
123
SW
56789
M2
123
3
FDS8878
FDS6676AS
7
8
2
1
open
SW
DO5010P-152HC
M3A
open
VIN
JVOUT
234
5
1.25V
C14
R8
1k
2R5TPE330MC
5V1
VIN1
GNDIN1
VOUT
GNDOUT
Rev. 1.4
01/08/08
Figure 4 - Demo board schematic based on ORCAD
8
Page 9
Bill of Materials
Item Quantity Reference Part
1 3 C1,C5,C11 1u
2 5 C2,C7,C8,C15,C17 0.1u
3 1 C3 1n
4 1 C4 18n
5 1 C6 2.7n
6 1 C9 25TQC33M
7 1 C10 470p
8 2 C13,C14 2R5TPE330MC
9 1 C16 3.9n
10 1 C18 22u
11 1 C20 10u
12 1 D1 MBR0530T1
13 1 L2 DO5010P-152HC
14 1 M1 FDS8878
15 1 M2 FDS6676AS
16 1 M4 MTD3055
17 2 R1,R7 10
18 1 R2 6k
19 1 R3 2.49
20 1 R4 2.7k
21 3 R5,R6,R17 0
22 3 R8,R9,R13 1k
23 1 R10 6.98k
24 1 R11 12.4k
25 1 R12 4.22k
26 2 R14,R15 100k
27 1 U1 NX2715
NX2715
Rev. 1.4
01/08/08
9
Page 10
Demoboard waveforms
NX2715
Fig.5 Startup
Fig.7 Voltage Ripple of 1.25V output
Fig.6 Startup with preload
Fig.8 Output short into latch out
Fig. 9 Dynamic response of 1.25V output
Rev. 1.4
01/08/08
Fig. 10 Dynamic response of LDO output
10
Page 11
NX2715
RIPPLEINS
1
IVF
0.410A20V200kHz
=3.9A
SOUT
ESR=6.4m
==Ω
ERIPPLE
12m3.9A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VIN=7-20V
VOUT=1.25V
IOUT =10A
DVRIPPLE <=25mV
DVTRAN<=60mV @ 5A step
FS=200kHz
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:
V-VV
OUT
INOUT OUT
××
×
20V-1.25V1.25V1
×
××
...(1)
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
OUT
L=1.5uH
OUT
Choose LOUT=1.5uH, then coilcraft inductor
DO5010P-152HC is a good choice.
Current Ripple is calculated as
V-VV
I=
RIPPLE
INOUT OUT
20V-1.25V1.25V1
1.5uH20V200kHz
××
LVF
OUTINS
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specification for the load transient. The optimum design may
require a couple of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
is the value of output capaci-
OUT
tors.
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
desire
∆
RIPPLE
I3.9A
∆
RIPPLE
25mV
V
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 25mV output ripple, POSCAP
2R5TPE330MCC2 with 12mΩ are chosen.
ESRI
N
=
∆
×∆
V
RIPPLE
Number of Capacitor is calculated as
N
Ω×
=
25mV
N =1.9
The number of capacitor has to be round up to a
integer. Choose N =2.
RIPPLE
××
8FC
...(3)
...(4)
...(5)
Rev. 1.4
01/08/08
11
Page 12
NX2715
OUT
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.99H
=µ
12m330F2.04us
2
1.74×∆=+×τ
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. The amount of ceramic
capacitor output ripple is :
I
∆
VESRI
∆=×∆+
RIPPLERIPPLE
8200kHzC
RIPPLE
××
Using the above equations, although DC ripple
spec can be met, however it needs to be studied for
transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient is specified as
∆V
droop
∆V
<
@step load DI
STEP
During the transient, the voltage droop during
the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other
section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the
overshoot when load from high load to light load
with a DI
transient load, if assuming the band-
STEP
width of system is high enough, the overshoot can
be estimated as the following equation.
V
VESRI
overshootstep
OUT
2LC
××
OUT
...(6)
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(7)
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
...(8)
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected
output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of
ESR and capacitance is high and
≤ is true. In
that case, the transient spec is mostly like to dependent on the ESR of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 60mV for 5A load step.
If the POSCAP 2R5TPE330MCC2(330uF,
12mohm ESR) is used, the crticial inductance is given
as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
12m330F1.25V
5A
The selected inductor is 1.5uH which is bigger
than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also
capacitance.
number of capacitors is
LI
×∆
step
τ=−×
V
OUT
1.5H5A
µ×
=−Ω×µ=
1.25V
ESRI
N
12m5A
Ω×
=+
60mV
21.5H330F60mV
×µ×µ×
ESRC
EE
Estep
V2LCV
∆×××∆
tranEtran
1.25V
V
OUT
2.04us
×
2
=
Rev. 1.4
01/08/08
12
Page 13
NX2715
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
The number of capacitors has to satisfy both ripple
and transient requirement. Overall, we choose N=2.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for
high frequency capacitor such as high quality POSCAP
especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the
ESR of capacitors is so low that the PCB parasitic can
affect the results tremendously. More capacitors have
to be selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of
the power stage, the power system has 180o phase
shift , and therefore, is unstable by itself. In order to
achieve accurate output voltage and fast transient response, compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain
crossing 0dB with -20dB/decade. Power stage output
capacitors usually decide the compensator type. If
electrolytic capacitors are chosen as output capacitors,
type II compensator can be used to compensate the
system, because the zero caused by output capacitor
ESR is lower than crossover frequency. Otherwise type
III compensator should be chosen.
Voltage feedforward is used in NX2715 to compensate the output voltage variation caused by input
voltage changing. The feedforward funtion is realized
by using VIN pin voltage to program the oscillator ramp
voltage V
vides nearly constant power stage gain under wide voltage input range.
at about 1/10 of VIN voltage, which pro-
OSC
pensate the system with type III compensator. The
following figures and equations show how to realize
the type III compensator by transconductance amplifier.
1
×π××
2RC
42
1
×π×+×
2(RR)C
233
1
×π××
2RC
33
1
×
CC
4
CC
12
+
12
×π××
2R
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same
time.
C2
Zf
C1
R4
Zin
Vout
R3
R2
C3
Fb
gm
Ve
R1
Vref
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to com-
Rev. 1.4
01/08/08
Figure 11 - Type III compensator using
transconductance amplifier
13
Page 14
NX2715
21.5uH660uF
26m660uF
20.755.06kHz2.5k
×π×××Ω
22.5k66.7kHz
1215kHz1.5uH660uF
=3.7nF
240kHz3.9nF
()
23.9nF5.06kHz40kHz
Case 1: FLC<FO<F
ESR
ESR POSCAP, OSCON)
power stage
LC
F
Gain(db)
40dB/decade
loop gain
compensator
F
F
Z1
Z2
F
O
(for most ceramic or low
ESR
F
20dB/decade
F
P1
F
P2
2. Set R4 equal to 2.5kΩ.
3. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
17nF
=
Choose C2=18nF.
4. Calculate C1 by equation (14) with pole Fp2 at
one third of the switching frequency.
C
=
1
=
959pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=1nF.
5. Calculate C
with the crossover frequency F
3
at 15kHz.
O
Figure 12 - Bode plot of Type III compensator
(FLC<FO<F
ESR
)
Typical design example of type III compensator
in which the crossover frequency is selected as
FLC<FO<F
and FO<=1/10~1/5Fs is shown as the
ESR
following steps. In this example, output voltage is
1.25V, output inductor is 1.5uH, output capacitors are
two POSCAP 2R5TPE330MCC2 (330uF, 12mohm
ESR)
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
5.06kHz
=
F
40kHz
Rev. 1.4
01/08/08
=
ESR
2ESRC
×π××
=
×π×Ω×
=
1
OUT
1
V2FLC
OSCOOUT
C=
3
VR
=
102.5k
×π×××
×
IN4
×π×××
×
Ω
Choose C3=3.9nF.
6. Calculate R3 by equation (13) with Fp1 =F
1
2FC
×π××
P13
1
×π××
R
=
3
=
1k
=Ω
Choose R3 =1kΩ.
7. Calculate R2 by setting compensator zero
FZ2 at the LC double pole.
R()
2
7.05k
111
=×−
2CFF
×π×
3Z2P1
=×−
111
×π×
=Ω
Choose R2 =6.98kΩ.
ESR
.
14
Page 15
NX2715
R=12.41k
==Ω
22.2uH2000uF
29m2000uF
20.752.4kHz2.5k
×π×××Ω
22.5k66.7kHz
215kHz1uH
×Ω
28.8kHz1.2k
×π××Ω
8. Calculate R1 .
RV
×
2REF
1
V-V1.25V-0.8V
OUT REF
Choose R1=12.4kΩ.
Case 2: FLC<F
power stage
Gain(db)
loop gain
compensator
6.98k0.8V
Ω×
(for electrolytic capacitors)
ESR<FO
LC
F
40dB/decade
ESR
F
20dB/decade
F
=
ESR
2ESRC
×π××
=
×π×Ω×
8.8kHz
=
1
OUT
1
2. Set R4 equal to 2.5kΩ.
3. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
35nF
=
Choose C2=33nF.
4. Calculate C1 by equation (14) with pole Fp2 at
one third of the switching frequency.
C
≈
1
≈
959pF
≈
1
2RF
×π××
4P2
1
×π×Ω×
F
Z1 Z2
F
P1
F
F
F
O
P2
Figure 13 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<1/10Fs is shown as
ESR<FO
the following steps. Here two SANYO MV-WF1000 with
18 mΩ is chosen as output capacitor, output inductor
is 2.2uH, output voltage is 1.05V, switching frequency
is 200kHz.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
2LC
=
.
ESR
1
×π××
OUTOUT
1
LC
×π××
2.4kHz
=
Choose C1=1nF.
5. Calculate R
with the crossover frequency F
3
at 15kHz.
VESRR
IN4
R=
3
=10
=1.08k
×
V2FL
OSCO
9mohm2.5k
×
×π××
Ω
×
×π××
Choose R3=1.2kΩ.
6. Calculate C3 by equation (13) with Fp1 =F
1
2FR
×π××
P13
1
C
=
3
=
14nF
=
Choose C3 =15nF.
7. Calculate R2 by setting compensator zero
FZ2 at the LC double pole.
ESR
O
.
Rev. 1.4
01/08/08
15
Page 16
NX2715
()
215nF2.4kHz8.8kHz
R=12.8k
==Ω
Gain=gR ...(15)
F= ... (16)
F ... (17)
22.2uH1360uF
220.5m1360uF
R()
2
=×−
3.2k
=Ω
111
=×−
2CFF
×π×
3Z2P1
111
×π×
Choose R2 =4kΩ.
8. Calculate R1 .
RV
×
2REF
1
V-V1.05V-0.8V
OUT REF
4k0.8V
Ω×
Choose R1=12.7kΩ.
B. Type II compensator design
If the electrolytic capacitors are chosen as
power stage output capacitors, usually the Type II
compensator can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<F
<<FO<1/10F
ESR
s.
The following equations show the compensator
pole zero location and constant gain.
R
1
××
m3
R+R
12
1
z
2RC
×π××
≈
p
2RC
31
1
×π××
32
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C1
C2
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
Z
LC
F
ESR
P
F
F
O
Figure 14 - Bode plot of Type II compensator
Type II compensator can also be realized by
simple RC circuit without feedback as shown in figure
15. R3 and C1 introduce a zero to cancel the double
pole effect. C2 introduces a pole to suppress the switching noise.
Rev. 1.4
01/08/08
Figure 15 - Type II compensator with
transconductance amplifier
The following is parameters for type II compen-
sator design. Input voltage is 12V, output voltage is
2.5V, output inductor is 2.2uH, output capacitors are
two 680uF with 41mΩ electrolytic capacitors.
1.Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
2.9kHz
1
OUT
1
=
F
ESR
5.7kHz
×π××
2ESRC
=
×π×Ω×
=
16
Page 17
1.Set R2 equal to10kΩ. Using equation 18, the
1020.5m2.5mA/V
21k0.752.9kHz
p
F
1k300kHz
OUT
REF
2REF
OUT REF
IID1-D
final selection of R1 is 4.7kΩ.
2. Set crossover frequency at 1/20 of the
swithing frequency, here FO=10kHz.
3.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1210kHz2.2uH1
=
=0.8k
Choose R
4. Calculate C1 by setting compensator zero F
×π××
×××
inESRmREF
×π××
××
2.5V
×
0.8V
1
Ω
Ω
=1kΩ.
3
Z
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=70nF
Choose C1=68nF.
5. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
RF
π××
3s
1
π×Ω×
=530pF
Choose C2=560pF.
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation applies to figure 16, which shows
the relationship between
vider.
V ,
V and voltage di-
NX2715
Vout
R2
Fb
R1
Vref
Figure 16 - Voltage divider
RV
R=
1
where R
of R1 value can be set by voltage divider.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors
can be calculated
as:
RMSOUT
D
=
VINMIN = 7V, VOUT=1.05V, IOUT=10A, the result of
input RMS current is 3.8A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON CAP 25SVP56M
25V 56uF 28mΩ with 3.8A RMS rating are chosen
as input bulk capacitors.
×
V-V
is part of the compensator, and the value
2
...(18)
=××
V
OUT
V
INMIN
...(19)
Rev. 1.4
01/08/08
17
Page 18
NX2715
SWLDSON
IR+V
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
×−××
P=I(1D)RK
SWINOUTSWS
PVITF
=××××
Power MOSFETs Selection
The NX2715 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. For example, two IRF7822 are used in application. They have the following parameters: VDS=30V,
ID =18A,R
There are two factors causing the MOSFET
power loss:conduction loss, switching loss.
Conduction loss is simply defined as:
P=IDRK
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to
1.4 at 125oC according to datasheet. Conduction loss
should not exceed package rating or overall system
thermal budget.
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
=6.5mΩ,Q
DSON
2
×××
2
+
GATE
=44nC.
...(20)
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Over Current Limit Protection
Over current protection is achieved by sensing
current through the low side MOSFET. An internal current source of 32uA flows through an external resistor
connected from OCP pin to SW node sets the over
current protection threshold. When synchronous FET
is on, the voltage at node SW is given as
V=-IR×
The voltage at pin OCP is given as
×
OCPOCPSW
When OCP pin voltage is below zero, the over
current occurs after three cycles as shown in figure 17,
both Hdrv and Ldrv will be shut down.
1
2
...(21)
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS is the high side gate source voltage, and
V
is the low side gate source voltage.
LGS
Rev. 1.4
01/08/08
R
OCP
comparator
Figure 17 - Over Current Protection Waveform
and Block Diagram
OCP
I
32uA
OCP
vbus
SW
OCP
R
18
Page 19
NX2715
OCPOCP
DSON
R4.57k
===Ω
RDSONLDOINLDOOUTLOAD
(3.3V2.5V)/2A0.4
=−=Ω
(3.3V2.5V)2A1.6W
gESR
C=
4FR1+gESR
C= =77pF
×Ω
LDOOUTREF
5k0.8V
1.6V0.8V
The over current limit can be set by the following
equation:
SET
If MOSFET R
×
KR
=6.5mΩ, the worst case ther-
DSON
×
IR
=
I
mal consideration K=1.5 and the current limit is set at
15A, then
SETDSON
OCP
Choose R
××
I32uA
OCP
=4.64kΩ.
OCP
15A1.56.5m
××Ω
IKR
For NX2715, if switching channel goes into OCP
and latch up, the LDO will be latch up at the same
time.
LDO Selection Guide
NX2715 offers a LDO controller. The selection
of MOSFET to meet LDO is more straight forward.
The selection is that the Rdson of MOSFET should
meet the dropout requirement. For example.
V
=3.3V
LDOIN
V
I
The maximum Rdson of MOSFET should be
=2.5V
LDOOUT
=2A
Load
R(VV)I
=−×
where FO is the desired crossover frequency.
Typically, in this LDO compensation, crossover
frequency FO has to be higher than zero caused by
ESR. FO is typically around several tens kHz to a few
hundred kHz. For this example, we select Fo=100kHz.
gm is the forward trans-conductance of MOSFET.
LDO input
+
Vref
R
f1
R
f2
Rc Cc
ESR
Co
Rload
Figure 18 - NX2715 LDO controller.
For IRFR3706, gm=53.
Select Rf1=5kohm.
Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.
C
15318m
4100kHz5k1+5318m
×π××Ω×Ω
×
Most of MOSFETs can meet the requirement.
More important is that MOSFET has to be selected
right package to handle the thermal capability. For LDO,
maximum power dissipation is given as
P(VV)I
=−×
LOSSLDOINLDOOUTLOAD
=−×=
Select IR MOSFET IRFR3706 with 9mΩ R
DSON
is sufficient.
LDO Compensation
The diagram of LDO controller including VCC
regulator is shown in the following figure.
For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows.
×
m
×
Rev. 1.4
01/08/08
C
1
×π×××
Of1m
Choose CC=82pF. For electrolytic or POSCAP,
RC is typically selected to be zero.
Rf2 is determined by the desired output voltage.
RV
×
R=
=
Ω
f1REF
f2
VV
−
Ω×
−
=5k
Choose Rf2=5kΩ.
When ceramic capacitors or some low ESR bulk
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency FO has to be chosen much higher
than zero caused by RC and CC and much lower than
zero caused by ESR . For example, 22uF ceramic is
used as output capacitor. We select Fo=100kHz,
Rf1=1kohm and select MOSFET MTD3055(gm=5). R
and C
can be calculated as follows.
C
19
C
Page 20
NX2715
2100kHz22uF
25.4k5S
2FC
×π××
R=R
Cf1
=1k
=5.4k
Ω
×
Ω×
OO
0.5g
×
m
×π××
0.55S
×
Choose RC=5.4kΩ.
10C
×
C=
C
=
=1.3nF
Choose C
O
Rg
×
Cm
1022uF
×
×π×Ω×
=1.2nF.
C
Current Limit for LDO
Current limit of LDO is achieved by sensing
the LDO feedback voltage. When LDO_FB pin is
below 70% of V
, the IC goes into latch up. The IC
REF
will turn off all the channel and latch up.
Over Voltage Protection
When FB pin voltage exceeds
1.04V(130%*V
voltage protection will be triggered. Hdrv turns low
and Ldrv turns high. Ldrv will be from high to low once
FB voltage falls below 0.68V(85%*V
Figure 19 - OVP trigger threshold.
) and be there for three cycles, over
RE F
REF
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-
cally touching the drain pin of the upper MOSFET, a
).
plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane ans as close as possible. A snubber nedds to be
placed as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other by-
Rev. 1.4
01/08/08
20
Page 21
passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2715
Rev. 1.4
01/08/08
21
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