Datasheet nx2710ds, nx2710 Datasheets

NX2710

SINGLE CHANNEL PWM CONTROLLER WITH NMOS LDO

CONTROLLER AND 5V BIAS REGULATOR

ADVANCE DATA SHEET

Pb Free Product

DESCRIPTION

The NX2710 controller IC is a compact synchronous
Buck controller IC with 16 lead SOIC package designed
for step down DC to DC converter applications with
feedforward functionality. Voltage feedforward provides
fast response, good line regulation and nearly constant
power stage gain under wide voltage input range. The
NX2710 controller is optimized to convert single sup­ply up to 24V bus voltage to as low as 0.8V output
voltage. Internal UVLO keeps the regulator off until the
supply voltage exceeds 9V where internal digital soft
starts get initiated to ramp up output. The NX2710 em­ploys programmable current limiting and FB UVLO
followed by HICCUP feature. Other features include:
5V gate drive, Programmable frequency from 300kHz
to 1MHz, Adaptive deadband control, Internal digital
soft start; Vcc under voltage lockout and shutdown ca­pability via comp pin.

MBR0530T1

8

+5V

1.65k

VIN

1uF

1ohm

9

REGCS

10

REGOUT

13

11

5

VCC

REGFB

RT

10uF

5k

1uF

BST

HDRV

SW

OCP

LDRV

GND

Fb

Comp

N X 2 7 1 0

LDO OUT

LDO FB

FEATURES

n Bus voltage operation from 9V to 24V
n 5V bias regulator available
n Excellent dynamic response with input voltage

feed-forward and voltage mode control

n Programmable switching frequency up to 1MHz
n Internal Digital Soft Start Function
n Programmable hiccup current limit
n Shutdown by pulling COMP pin low
n NMOS LDO controller available
n Start into precharged output
n Pb-free and RoHS compliant

APPLICATIONS

n Notebook PC
n Graphic Card on board converters
n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n Set Top Box and LCD Display

TYPICAL APPLICATION

DO3316P-102

2*16SVP330M

1

0.1uF

2

16
12
4
3

14
15

6

7

8.06k

2.5k

680pF

Q1

Q2

0.75uH

3.3nF

1.2k

15nF

82pF

5k

15k

0

7.5k

VIN1

+12V

VOUT1

+1.2V@25A

2*(560uF,7mohm)

VIN2

+3.3V

MTD3055

VOUT2

5k

150uF
18mohm

+1.6V@2A

Figure1 - Typical application of NX2710

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX2710CSTR 0 to 70oC SOIC -16L 300kHz to 1MHz Yes

Rev. 1.3
08/07/07

1

NX2710

CW

θ≈83/

ABSOLUTE MAXIMUM RATINGS

VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V

VIN to GND .......................................................... -0.3V to 25V

BST, HDRV, REGCS to GND Voltage .................. -0.3V to 35V

SW to GND ......................................................... -2V to 35V

REGOUT to GND ................................................. 0.2 to 16V

All other pins ....................................................... -0.3V to 6.5V

Storage Temperature Range ................................. -65oC to 150oC

Operating Junction Temperature Range ................ -40oC to 125oC

ESD Susceptibility .............................................. 2kV

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

16-LEAD PLASTIC SOIC

o

JA

BST

HDRV

GND

LDRV

RT

LDO-OUT

LDO-FB

VIN

1
2
3
4
5
6
7
8 9

16
15
14
13
12
11
10

SW

COMP
FB
VCC

OCP
REGSEN
REGOUT
REGCS

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = 0 to 70oC. Typical
values refer to TA = 25oC.

PARAMETER SYM Test Condition Min TYP MAX Units

Reference Voltage

Ref Voltage V

REF

Ref Voltage line regulation 0.2 %

Supply Voltage(Vcc)

VCC Voltage Range V
Operating quiescent current I

CC
Q

switching is off 3

4.75 5.25

Vcc UVLO

VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V

Supply Voltage(Vin)

Vin Voltage Range V

in

9 25

Input Voltage Current Vin=24V 9

Rev. 1.3
08/07/07

0.8

4.4

5

10

V

V

mA

V

V

mA

2

NX2710

(CL=3300pF)

Ldrv going Low to Hdrv going

PARAMETER SYM Test Condition Min TYP MAX Units

Vin UVLO

Vin-Threshold Vin_UVLO Vin Rising
Vin-Hysteresis Vin_Hyst Vin Falling 0.8 V

Oscillator (Rt)

Frequency F
Frequency Over Vin
Ramp-Amplitude Voltage V

RAMP

S

RT=open 300 KHz

-5

Vin=20V 2 V
Ramp Offset 0.8 V
Ramp/Vin Gain 0.1 V/V
Max Duty Cycle
Min on time

Error Amplifiers

Transconductance 2500 umho
Input Bias Current Ib 100 nA
Comp SD threshold 0.3 V

Vref and Soft Start

Soft Start time Tss Fs=300kHz 6.8 mS

High Side Driver

8.8

5

90 %

150

V

%

nS

R

(Hdrv) I=200mA

source

1 ohmOutput Impedance , Sourcing

Current
Output Impedance , Sinking

R

(Hdrv) I=200mA

sink

ohm0.8

Current
Rise Time THdrv(Rise) 10% to 90% 50 ns

Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time

Low Side Driver

N

Tdead(L to

H)

ns30

High, 10% to 10%

(CL=3300pF)

Output Impedance, Sourcing

R

(Ldrv) I=200mA 1 ohm

source

Current
Output Impedance, Sinking

R

(Ldrv) I=200mA 0.5 ohm

sink

Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns

Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going

30

ns

High, 10% to 10%

OCP Adjust

OCP current setting 32 uA

FBUVLO

Feedback UVLO threshold percent of nominal

65

70

75

%

Over temperature

Threshold

150

°C

Hysteresis 20 °C

Rev. 1.3
08/07/07

3

NX2710

LDO Controller

5V AUX REG

PARAMETER SYM Test Condition Min TYP MAX Units

FB Pin- Bias Current 100 nA
LDO FB Voltage LDO_OUT=LDO_FB 0.8 V
LDO FB UVLO percent of nominal 65 70 75 %
High Output Voltage VIN=12V, LDO_FB=0.7V

I

O_SOURCE

=1.4mA

Low Output Voltage VIN=12V, LDO_FB=0.9V

I

=1.4mA

O_SINK

High Output Source Current 3 mA

Current limit threshold 100 mV
FB Pin- Bias Current 0 uA
RegFb Voltage Regout=RegFb 1.25 V
Regout Output Voltage High VIN=12V, RegFb=1.1V

I

O_SOURCE

=1.4mA

Regout Output Voltage Low VIN=12V, RegFb=1.4V

I

=1.4mA

O_SINK

Open Loop Gain GBNT(Note1) 50 DB

Note 1: This parameter is guaranteed by design but not tested in production(GBNT).

10.2 V

0.2

11 V

0.2

V

V

Rev. 1.3
08/07/07

4

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed

VCC

BST

as close as possible to and connected to this pin and ground pin.
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic

capacitor is placed as close as possible to and connected to this pin and SW pin.

NX2710

GND

FB

COMP

SW

HDRV

LDRV

VIN

RT

LDO FB

Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor divider to

the output of the switching regulator to set the output DC voltage.

This pin is the output of the error amplifier and together with FB pin is used to compensate
the voltage control feedback loop.

This pin is connected to source of high side FETs and provide return path for the high
side driver.

High side gate driver output.
Low side gate driver output.

Bus voltage input provides power supply to oscillator, VIN UVLO signal and 5V regulator
controller.

Oscillator's frequency can be set by using an external resistor from this pin to GND.
LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal

comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP
circuitry.

LDO OUT

REGOUT

REGSEN

Rev. 1.3
08/07/07

REGCS

OCP

LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The
maximum rating of this pin is 16V.

This pin is 5V regulator current limit pin. It compares the voltage drop on the resistor
which is connected between Vin and REGCS pin with internal offset 100mV. 1ohm
resistor sets the current limit 100mA.

The output of the 5V regulator controller that drives a low current low cost external
bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived from
bus voltage. This eliminates an otherwise external regulator needed in applications where
5V is not available.

Feedback pin of the 5V regulator controller. A resistor divider is connected from the
output of the 5V regulator to this pin to complete the loop.

This pin is connected to the drain of the external low side MOSFET and is the input of the
over current protection(OCP) comparator. An internal current source is flown to the
external resistor which sets the OCP voltage across the Rdson of the low side MOSFET.
Current limit point is this voltage divided by the Rds-on.

5

BLOCK DIAGRAM

RegCs

VIN

+

100mV

VCC

Bias
Generator

1.25V

0.8V

COMP

4.4/4.2

6/5.75

0.3V

Ref

EN

three
cycle
delay

Hiccup

START

POR

Reset dominant

R

Q

S

START

START

LDIN

NX2710

Regout

Regsen

BST

DrvH

SW

RT

FB

COMP

GND

Vp

START

Digital
start Up

Vp

Dis_EA

SS_1/4_done

Dis_EA

SS_half_done

0.6V
CLAMP

VIN

OSC

0.6V

EN

S

R

POR

Hiccup

R

Hiccup logic

FET Drivers

HDin

Vp

Disable

SS_done

VpLDO

70%*Vp

32uA

VCC

Q

3 cycle
filter

HDIN

3 cycle
filter

LDIN

START

SS_1/4_done

3 cycle
filter

70%*Vp

VCC

DRVL

FB

OCP

LDO_out

Rev. 1.3
08/07/07

LDO_FB

Figure 2 - Simplified block diagram of the NX2710

6

+5V

5k

1.65k

2N3904

1uF

1ohm

NX2710

DO3316P-102

VIN1

+12V

2*(560uF,7mohm)

+3.3V

100uF

MTD3055

220uF
39mohm

VOUT1

+1.2V@25A

VIN2

VOUT2

+2.5V@2A

2.5k

Q1

Q2

2 *
10uF

0.75uH

15nF

150pF

16MV1500WG

3.3nF

7.5k

1.2k

15k

470

1k

MBR0530T1

8

VIN

1uF

9

REGCS

5k

10

1uF

10

13

11

5

REGOUT
VCC

N X 2 7 1 0

REGFB

LDO OUT

RT

BST

HDRV

SW

OCP

LDRV

GND

Fb

Comp

LDO FB

1

2

16
12
4
3

14
15

6

7

0.1uF

6k

680pF

Rev. 1.3
08/07/07

Figure 3 - Simplified Demo board schematic

7

NX2710

U1

9

REG_CS

10

REG_OUT

R34
op

11

REG_SENSE

13

VCC

C1
1u

6

LDO_OUT

R31
0

C8
150p

7

LDO_FB

5

RT

R30
op

C20

op

R29
1

Q1
MBR3904

M6
op

VCC

C26
1u

3.3V

3

JP112

VOUT

LDO_OUT

GNDLDO

Title

NX2710 HC APPLICATION

Size Document Number Rev

2710-SO-02A A

Date: Sheet of

LDO_IN

LDO_OUT

panasonic FM 220uF

JLDO

1

234

5

C24

0.1u

MTD3055

R27

5k

C22
100u

C23

R25

4.99k

R26
op

C7
op

R28

1.65k

R1

10

M7

R33
1k

R32
474

1 1Thursday, September 14, 2006

C21

1u

C25

0.1u

8

1

VIN

BST

2

HDRV

16

SW

12

OCP

NX2710

4

LDRV

14

FB

15

COMP

GND

3

VCC

D1
MBR0530T1

R22
0

C2

0.1u

R4

6k

C3
op

C5
680p

R23

0

R24

0

R12

0

R13

HDRV

0

D5
op

R14

0

R15

0

LDRV

R16

0

C4

15n

R3
open

C6
open

1

L3

DO3316H-102

2

C12

open

C9

10u

UG1

UG2

SW

LG1

LG2

LG3

R2

2.5k

C11

VDD

C10

10u

M1 NTD70N03R

NTD70N03R

M2

SW

D2

D3

M3 NTD110N02R

M4 NTD110N02R

R19

1.2k

R21
15k

J1

3.3V

1

3.3V1

3.3V

2

3.3V2

3

GND

5V

4

5V1

5

GND1

5V

16MV1500WG

D4 C14

R17
10

M5 NTD110N02R

C13
470p

R20

7.5k
C16

3.3n

LG1

6

5V

7

GND2

8

PWR_OK

9

5VSB

12V

10

12V1

L1

1 2

PG0077.801

L2

1 2

OP

UG1 UG2

4

56789

op

M13

4

123

4SEPC560MX

123

SW

LG2

MH1

3.3V

MH1

-12V

GND3

PS_ON

GND4
GND5
GND6

-5V
5V2
5V3

MH2

ATX con

MH2

56789

M11

4

3.3V

11
12
13

R5

14

1k

15
16
17
18

5V

19

5V

20

4SEPC560MX

C15

VDD

op

4

SW

56789

op

M14

LG3

123

J2

1

op

56789

M12

123

4

12V

MH1

GND1

12V1

MH1

GND2212V2

MH2

ATX-12V

MH2

C17

0.1u

VOUT

C19

op

56789

M15

123

1

C18
47u

4
3

JVOUT

5

op

1

1

12V
12V

234

R18
1k

GNDOUT

BUS

GND

VOUT

Rev. 1.3
08/07/07

Figure 4 - Demo board schematic based on ORCAD

8

Bill of Materials

Item Quantity Reference Part

1 3 C1,C21,C26 1u
2 4 C2,C17,C24,C25 0.1u
3 1 C4 15n
4 1 C5 680p
5 1 C8 150p
6 2 C9,C10 10u
7 1 C11 16MV1500WG
8 1 C13 470p

9 2 C14,C15 4SEPC560MX
10 1 C16 3.3n
11 1 C18 47u
12 1 C22 100u
13 1 C23 panasonic FM 220uF
14 1 D1 MBR0530T1
15 1 L1 PG0077.801
16 1 L3 DO3316H-102
17 2 M1,M2 NTD70N03R
18 3 M3,M4,M5 NTD110N02R
19 1 M7 MTD3055
20 1 Q1 MBR3904
21 2 R1,R17 10
22 1 R2 2.5k
23 1 R4 6k
24 3 R5,R18,R33 1k
25 9 R12,R13,R14,R15,R16,R22, 0
26 R23,R24,R31
27 1 R19 1.2k

1 R20 7.5k
28 1 R21 15k
29 1 R25 4.99k
30 1 R27 5k
31 1 R28 1.65k
32 1 R29 1
33 1 R32 474
34 1 U1 NX2710

NX2710

Rev. 1.3
08/07/07

9

Demoboard waveforms

NX2710

Figure 5 - Output ripple

Figure 7 - Transient response @ LDO

Figure 6 - Transient response @ 1.2 output

Figure 8 - Soft start

Figure 9 - 1.2V over current proteciton Figure 10 - LDO over current protection

Rev. 1.3
08/07/07

10

NX2710

RIPPLEINS

1

IVF

0.225A12V300kHz

=4.8A

SOUT

ESR=4.2m

==Ω

ERIPPLE

7m4.8A

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple

Design Example

Power stage design requirements:
VIN=12V
VOUT=1.2V
IOUT =25A
DVRIPPLE <=20mV
DVTRAN<=60mV @ 10A step
FS=300kHz

Output Inductor Selection

The selection of inductor value is based on in­ductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:

V-VV

OUT

INOUT OUT

××

×

12V-1.2V1.2V1

×

××

...(1)

L=
I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.2, then

L=

OUT

L=0.72uH

OUT

Choose LOUT=0.75uH, then Pulse inductor
PG0077.801 is a good choice.

Current Ripple is calculated as

V-VV

I=

RIPPLE

INOUT OUT

LVF

12V-1.2V1.2V1

0.75uH12V300kHz

××

OUTINS

××=

1

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specifica­tion for the load transient. The optimum design may
require a couple of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C

is the value of output capaci-

OUT

tors.

Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.

For this example, OSCON are chosen as output
capacitors, the ESR and inductor current typically de­termines the output voltage ripple.

desire

∆

RIPPLE

I4.8A

∆

RIPPLE

15mV

V

If low ESR is required, for most applications, mul­tiple capacitors in parallel are better than a big capaci­tor. For example, for 15mV output ripple, OSCON
4SEPC560MX with 7mΩ are chosen.

ESRI

N

=

∆

×∆

V

RIPPLE

Number of Capacitor is calculated as

N

Ω×

=

20mV

N =1.68

The number of capacitor has to be round up to a
integer. Choose N =2.

RIPPLE

××

8FC

...(3)

...(4)

...(5)

Rev. 1.3
08/07/07

11

NX2710

OUT

tran

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.94H

=µ

Estep

ESRI

1.296

If ceramic capacitors are chosen as output ca­pacitors, both terms in equation (3) need to be evalu­ated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capaci­tance per single unit is not sufficient to meet the tran­sient specification, which results in parallel configura­tion of multiple capacitors. The amount of ceramic

capacitor output ripple is :

I

∆

VESRI

∆=×∆+

RIPPLERIPPLE

8300kHzC

RIPPLE

××

Using the above equations, although DC ripple
spec can be met, however it needs to be studied for

transient requirement.

Based On Transient Requirement

Typically, the output voltage droop during tran­sient is specified as

∆V

droop

∆V

<

@step load DI

STEP

During the transient, the voltage droop during
the transient is composed of two sections. One sec­tion is dependent on the ESR of capacitor, the other
section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the
overshoot when load from high load to light load
with a DI

transient load, if assuming the band-

STEP

width of system is high enough, the overshoot can
be estimated as the following equation.

V

VESRI

overshootstep

OUT

2LC

××

OUT

...(6)

where τ is the a function of capacitor,etc.

output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency ca­pacitor such as electrolytic capacitor, the product of

ESR and capacitance is high and

≤ is true. In

that case, the transient spec is mostly like to depen­dent on the ESR of capacitor.

Most case, the output capacitor is multiple ca­pacitor in parallel. The number of capacitor can be cal­culated by the following

ESRI

×∆

N

Estep

V2LCV

∆×××∆

tranEtran

V

OUT

...(9)

where

0ifLL




LI

×∆

τ=




V



≤

crit

step

−×≥

OUT

...(10)

For example, assume voltage droop during tran­sient is 60mV for 10A load step.

If the OSCON 4SEPC560MX(560uF, 7mohm
ESR) is used, the crticial inductance is given as

ESRCV

××

EEOUT

==

I

∆

step

L

crit

7m560F1.2V

Ω×µ×

5A

The selected inductor is 0.75uH which is smaller
than critical inductance. In that case, the output volt­age transient mainly dependent on the ESR.

number of capacitor is

0ifLL




LI

×∆

τ=




V

OUT



≤

step

−×≥

where

ESRCVESRCV

××××

==

II

∆∆

stepstep

L

crit

where ESRE and CE represents ESR and capaci­tance of each capacitor if multiple capacitors are used
in parallel.

The above equation shows that if the selected

Rev. 1.3
08/07/07

∆

Ω×

60mV

V

×∆

tran

crit

N

=

...(7)

7m5A

=
=

The number of capacitors has to satisfied both

...(8)

ripple and transient requirement. Overall, we choose
N=2.

12

NX2710

F ...(11)

F ...(12)

F ...(13)

F ...(14)

OUT minin1

V1gZZ/R

f

OUT in

Z

VZ

−

It should be considered that the proposed equa­tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more ca­pacitors have to be chosen after the test. Typically, for
high frequency capacitor such as high quality POSCAP
especially ceramic capacitor, 20% to 100% (for ce­ramic) more capacitors have to be chosen since the
ESR of capacitors is so low that the PCB parasitic can
affect the results tremendously. More capacitors have
to be selected to compensate these parasitic param­eters.

Compensator Design

Due to the double pole generated by LC filter of
the power stage, the power system has 180o phase
shift , and therefore, is unstable by itself. In order to
achieve accurate output voltage and fast transient re­sponse, compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching fre­quency, phase margin greater than 50o and the gain
crossing 0dB with -20dB/decade. Power stage output
capacitors usually decide the compensator type. If
electrolytic capacitors are chosen as output capacitors,
type II compensator can be used to compensate the
system, because the zero caused by output capacitor
ESR is lower than crossover frequency. Otherwise type
III compensator should be chosen.

Voltage feedforward compensation is used in
NX2710 to compensate the output voltage variation
caused by input voltage changing. The feedforward
funtion is realized by using VIN pin voltage to program
the oscillator ramp voltage V

=0.1VIN, which pro-

OSC

vides nearly constant power stage gain under wide volt­age input range.

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross­over frequency. In this case, it is necessary to com­pensate the system with type III compensator. The

following figures and equations show how to realize
the type III compensator by transconductance ampli­fier.

1

×π××

2RC

42

1

×π×+×

2(RR)C

233

1

×π××

2RC

33

1

×

CC

4

CC

12

+

12

×π××

2R

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator for

transconductance amplifier is given by:

V 1gZ

e mf

=

−×

+×+

For the voltage amplifier, the transfer function of
compensator is

V

e

=

To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be de­sirable if R1||R2||R3>>1/gm can be met at the same
time,

C2

Zf

C1

R4

Zin

Vout

R3

R2

C3

Fb

gm

Ve

R1

Vref

Figure 11 - Type III compensator using

transconductance amplifier

Rev. 1.3
08/07/07

13

NX2710

20.75uH1120uF

23.5m1120uF

20.755.5kHz2.5k

×π×××Ω

22.5k100kHz

1215kHz0.75uH1120uF

=3.2nF

240.6kHz3.3nF

()

23.3nF5.5kHz40.6kHz

Case 1: FLC<FO<F

ESR

ESR POSCAP, OSCON)

power stage

LC

F

Gain(db)

40dB/decade

loop gain

compensator

(for most ceramic or low

ESR

F

20dB/decade

3. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

1

2FR

×π××

Z14

1

C

=

2

=

15nF

=

Choose C2=15nF.

4. Calculate C1 by equation (14) with pole Fp2 at

one third of the switching frequency.

C

≈

1

≈

639pF

≈

1

2RF

×π××

4P2

1

×π×Ω×

Choose C1=680pF.

5. Calculate C

with the crossover frequency F

3

at 15kHz.

O

F

Z1 Z2

F

F

O

F

F

P1

P2

Figure 12 - Bode plot of Type III compensator

(FLC<FO<F

ESR

)

Typical design example of type III compensator
in which the crossover frequency is selected as
FLC<FO<F

and FO<=1/10Fs is shown as the following

ESR

steps.

1. Calculate the location of LC double pole F

and ESR zero F

ESR

.

LC

F

=

LC

2LC

=

×π××

5.5kHz

=

F

=

ESR

2ESRC

×π××

=

×π×Ω×

40.6kHz

=

2. Set R4 equal to 2.5kΩ.

1

×π××

OUTOUT

1

1

OUT

1

V2FLC

C=

3

VR

=

102.5k

×π×××

OSCOOUT

×

IN4

×π×××

×

Ω

Choose C3=3.3nF.

6. Calculate R3 by equation (13) with Fp1 =F

1

2FC

×π××

P13

1

×π××

R

=

3

=

1.18k

=Ω

Choose R3 =1.2kΩ.

7. Calculate R2 by setting compensator zero

FZ2 at the LC double pole.

R()

2

7.6k

111

=×−

2CFF

×π×

3Z2P1

=×−

111

×π×

=Ω

Choose R2 =7.5kΩ.

8. Calculate R1 .

ESR

.

Rev. 1.3
08/07/07

14

RV

R=15k

==Ω

22.2uH2000uF

29m2000uF

20.752.4kHz2.5k

×π×××Ω

22.5k66.7kHz

215kHz1uH

×Ω

×

2REF

1

V-V1.2V-0.8V

OUT REF

Choose R1=15kΩ.

Case 2: FLC<F

ESR<FO

7.5k0.8V

Ω×

(for electrolytic capacitors)

F

=

LC

2LC

×π××

=

×π××

2.4kHz

=

NX2710

1

OUTOUT

1

power stage

LC

F

ESR

F

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

F

Z1 Z2

F

P1

F

F

F

O

P2

Figure 13 - Bode plot of Type III compensator

(FLC<F

ESR<FO

)

F

=

ESR

2ESRC

=

8.8kHz

=

1

×π××

OUT

1

×π×Ω×

2. Set R4 equal to 2.5kΩ.

3. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

1

2FR

×π××

Z14

1

C

=

2

=

35nF

=

Choose C2=33nF.

4. Calculate C1 by equation (14) with pole Fp2 at

one third of the switching frequency.

C

≈

1

≈

959pF

≈

1

2RF

×π××

4P2

1

×π×Ω×

If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F

ESR<FO

the following steps. Here two SANYO MV-WF1000 with
18 mΩ is chosen as output capacitor, output inductor
is 2.2uH, output voltage is 1.2V, switching frequency
is 200kHz.

1. Calculate the location of LC double pole F

and ESR zero F

Rev. 1.3
08/07/07

ESR

.

and FO<=1/10Fs is shown as

LC

Choose C1=1nF.

5. Calculate R

with the crossover frequency FO at

3

15kHz.

VESRR

IN4

R=

3

=10
=1.08k

×

V2FL

OSCO

9mohm2.5k

×

×π××

Ω

×

×π××

Choose R3=1.2kΩ.

6. Calculate C3 by equation (13) with Fp1 =F

ESR

.

15

NX2710

Gain=gR ... (15)

F= ... (16)

F ... (17)

22.2uH1360uF

28.8kHz1.2k

×π××Ω

()

215nF2.4kHz8.8kHz

R=15k

==Ω

1

2FR

×π××

P13

1

C

=

3

=

14nF

=

Choose C3 =15nF.

7. Calculate R2 by setting compensator zero

FZ2 at the LC double pole.

R()

2

=×−

3.2k

=Ω

111

=×−

2CFF

×π×

3Z2P1

111

×π×

Choose R2 =4kΩ.

8. Calculate R1 .

×

2REF

1

V-V1.2V-0.8V

OUT REF

7.5k0.8V

Ω×

RV

Choose R1=15kΩ.

power stage

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

P

F

F

F

LC

Z

ESR

F

F

O

Figure 14 - Bode plot of Type II compensator

Vout

B. Type II compensator design

If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa­tor can be used to compensate the system.

For this type of compensator, FO need to
satisfy FLC<F

Type II compensator can also be realized by
simple RC circuit without feedback as shown in the
following figure. R3 and C1 introduce a zero to cancel
the double pole effect. C2 introduces a pole to sup­press the switching noise. The following equations show
the compensator pole zero location and constant gain.

z

p

<<FO<=1/10F

ESR

R

1

××

m3

R+R

12

s.

1

2RC

×π××

31

≈

1

2RC

×π××

32

R2

Fb

gm

R1

Vref

Ve

R3

C2

C1

Figure 15 - Type II compensator with
transconductance amplifier

The following is parameters for type II compen-

sator design. Input voltage is 12V, output voltage is

2.5V, output inductor is 2.2uH, output capacitors are

two 680uF with 41m

1.Calculate the location of LC double pole F

and ESR zero F

=

F

LC

2LC

=

Ω electrolytic capacitors.

.

ESR

1

×π××

OUTOUT

1

LC

×π××

=

2.9kHz

Rev. 1.3
08/07/07

16

NX2710

220.5m1360uF

20.5m2.5mA/V

22.55k0.752.9kHz

p

F

2.55k300kHz

OUT

REF

2REF

OUT REF

IID1-D

1

×π××

OUT

1

×π×Ω×

=

F

ESR

2ESRC

=
=

5.7kHz

2.Set R2 equal to10kΩ. Using equation 18, the

final selection of R1 is 4.7kΩ.

3. Set crossover frequency at 1/10 of the

swithing frequency, here FO=30kHz.

4.Calculate R3 value by the following equation.

V2FLV

OSCOOUT

R=

3

VRgV

=0.1

=2.53k

Choose R

5. Calculate C1 by setting compensator zero F

×π××

×××

inESRmREF

230kHz2.2uH1

×π××

××

2.5V

×

0.8V

1

Ω

Ω

=2.55kΩ.

3

Z

at 75% of the LC double pole.

C=

1

=

1

2RF

×π××

3z

1

×π×Ω××

=28nF

Choose C1=27nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

C=

2

=
=207pF

1

RF

π××

3s

1

π×Ω×

Choose C2=220pF.

Output Voltage Calculation

Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value.

The following equation applies to figure16, which

shows the relationship between

V ,

V and volt-

age divider.

Vout

R2

Fb

R1

Vref

Figure 16 - Voltage Divider

RV

R=

1

where R

of R1 value can be set by voltage divider.

Input Capacitor Selection

Input capacitors are usually a mix of high fre­quency ceramic capacitors and bulk capacitors. Ce­ramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS cur­rent rating. The RMS current in the input capacitors
can be calculated

as:

RMSOUT

D

=

VIN = 12V, VOUT=1.2V, IOUT=25A, the result of input
RMS current is 7.5A.

For higher efficiency, low ESR capacitors are
recommended. Two Sanyo OS-CON 16SVP330M

16V 330uF 16m

as input capacitors.

×

V-V

is part of the compensator, and the value

2

...(18)

=××

V

OUT

V

IN

Ω with 4.72A RMS rating are chosen

...(19)

Rev. 1.3
08/07/07

17

NX2710

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

SWLDSON

IR+V

OCPOCP

DSON

R6.1k

===Ω

×−××

P=I(1D)RK

SWINOUTSWS

PVITF

=××××

Power MOSFETs Selection

The NX2710 requires at least two N-Channel
power MOSFETs. The selection of MOSFETs is based
on maximum drain source voltage, gate source volt­age, maximum current rating, MOSFET on resistance
and power dissipation. The main consideration is the
power loss contribution of MOSFETs to the overall con­verter efficiency. In 25A output application, five
IRFR3706 can be used, two for high side, three for low
side. They have the following parameters: VDS=30V, I
=75A,R

power loss:conduction loss, switching loss.

where the RDS(ON) will increases as MOSFET junc­tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to

1.4 at 125oC according to IRFR3706 datasheet. Con­duction loss should not exceed package rating or overall
system thermal budget.

conduction at the switching transition. The total
switching loss can be approximated.

where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.

ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis­charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:

charge,QLGATE is the low side MOSFETs gate

=9mΩ,Q

DSON

GATE

=23nC.

There are two factors causing the MOSFET

Conduction loss is simply defined as:

2

P=IDRK

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

×××

2

...(20)

+

Switching loss is mainly caused by crossover

1

2

...(21)

Also MOSFET gate driver loss should be consid-

...(22)

where QHGATE is the high side MOSFETs gate

charge,VHGS is the high side gate source voltage, and
V

is the low side gate source voltage.

LGS

This power dissipation should not exceed maxi-

mum power dissipation of the driver device.

Over Current Limit Protection

Over current protection is achieved by sensing
current through the low side MOSFET. An internal cur­rent source of 32uA flows through an external resistor
connected from OCP pin to SW node sets the over

D

current protection threshold. When synchronous FET
is on, the voltage at node SW is given as

V=-IR×

The voltage at pin OCP is given as

×

OCPOCPSW

When the voltage is below zero, the over current
occurss as shown in figure 17.

vbus

OCP

I

32uA

OCP

R

SW

OCP

OCP
comparator

Figure 17 - Over Current Protection

The over current limit can be set by the following
equation:

SET

R

If two MOSFETs R

×

KR

=6.5mΩ, the worst case

DSON

×

IR

=

I

thermal consideration K=1.5 and the current limit is
set at 40A, then

SETDSON

OCP

Choose R

××

I32uA2

OCP

=6kΩ.

OCP

40A1.56.5m

××Ω

×

IKR

For NX2710, if switching channel goes into hic­cup current limit, the LDO will go to hiccup too.

LDO Selection Guide

NX2710 offers a LDO controller. The selection
of MOSFET to meet LDO is more straight forward.
The selection is that the Rdson of MOSFET should

Rev. 1.3
08/07/07

18

NX2710

RDSONLDOINLDOOUTLOAD

(3.3V2.5V)/2A0.4

=−=Ω

(3.3V2.5V)2A1.6W

gESR

C=

4FR1+gESR

C= =91pF

×Ω

LDOOUTREF

5k0.8V

1.6V0.8V

2100kHz10uF

1010uF

12.7k5S

meet the dropout requirement. For example.

V

=3.3V

LDOIN

V
I

Load

LDOOUT

=2A

=2.5V

The maximum Rdson of MOSFET should be

R(VV)I

=−×

Most of MOSFETs can meet the requirement.
Moreimportant is that MOSFET has to be selected right
package to handle the thermal capability. For LDO,
maximum power dissipation is given as

P(VV)I

=−×

LOSSLDOINLDOOUTLOAD

=−×=

Select IR MOSFET IRFR3706 with 9mΩ R

DSON

is sufficient.

LDO Compensation

The diagram of LDO controller including VCC
regulator is shown in the following figure.

LDO input

+

Vref

R

f1

R

f2

Rc Cc

Figure 18 - NX2710 LDO controller.

ESR

Co

Rload

gm is the forward trans-conductance of MOSFET.

For IRF3706, gm=53.
Select Rf1=5kohm.
Output capacitor is Sanyo POSCAP 4TPE150M

with 150uF, ESR=25mohm.

C

15325m

4100kHz5k1+5325m

×π××Ω×Ω

×

Choose CC=100pF. For electrolytic or POSCAP,
RC is typically selected to be zero.

Rf2 is determined by the desired output voltage.

RV

×

R=

f2

=

Ω

f1REF

VV

−

Ω×

−

=5k

Choose Rf2=5kΩ.
When ceramic capacitors or some low ESR bulk
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency FO has to be chosen much higher
than zero caused by RC and CC and much lower than
zero caused by ESR . For example, 10uF ceramic is
used as output capacitor. We select Fo=100kHz,
Rf1=5kohm and select MOSFET MTD3055(gm=5S).
RC and C

can be calculated as follows.

C

2FC

×π××

R=R

=5k

Ω

Cf1

=12.56k

×

Ω×

OO

0.5g

×

m

×π××

0.55S

×

For most low frequency capacitor such as elec­trolytic, POSCAP, OSCON, etc, the compensation pa­rameter can be calculated as follows.

C

1

×π×××

Of1m

×

m

×

where FO is the desired crossover frequency.

Typically, in this LDO compensation, crossover
frequency FO has to be higher than zero caused by
ESR. FO is typically around several tens kHz to a few
hundred kHz. For this example, we select Fo=100kHz.

Rev. 1.3
08/07/07

Choose RC=12.7kΩ.

10C

×

C=

C

=

=1.6nF

Choose C

O

Rg

×

Cm

×

Ω×

=1.5nF.

C

19

NX2710

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below
70% of V
turn off all the channel for 4096 cycles and start to
restart system again.

, the IC goes into hiccup mode. The IC will

REF

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

There are two sets of components considered in
the layout which are power components and small sig­nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en­vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay­out which includes power plane, ground plane and sig­nal plane is recommended .

Layout guidelines:

1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.

2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-

cally touching the drain pin of the upper MOSFET, a

plane connection is a must.

3. The output capacitors should be placed as close
as to the load as possible and plane connection is re­quired.

4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane ans as close as possible. A snubber nedds to be
placed as close to this junction as possible.

5. Source of the lower MOSFET needs to be con­nected to the GND plane with multiple vias. One is not

enough. This is very important. The same applies to
the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by­passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.

8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.

9. All GNDs need to go directly thru via to GND
plane.

10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.

11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana­log control function.

Rev. 1.3
08/07/07

20

SOIC16 PACKAGE OUTLINE DIMENSIONS

NX2710

Rev. 1.3
08/07/07

21

NX2710

Rev. 1.3
08/07/07

22

Customer Service

NEXSEM Inc.

NX2710

500 Wald

Irvine, CA 92618

U.S.A.

Tel: [phone]

Fax: [phone]

WWW.NEXSEM.COM

Rev. 1.3
08/07/07

23