Datasheet nx2601ds, nx2601 Datasheets

Evaluation board available.

NX2601

DUAL SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO

CONTROLLER & 5V BIAS REGULATOR

PRELIMINARY DATA SHEET

Pb Free Product

DESCRIPTION

The NX2601 controller IC is a triple controller with a dual
channel synchronous Buck controller IC and an LDO con­troller designed for multiple converters such as PCIe
graphic card applications .The two synchronous PWM
controllers are 180 degree out of phase which reduces
the input ripple current, allowing to reduce the # of input
capacitors.Another main feature of the part is that it can
operate from single 12V supply while maintaining a regu­lated 5V supply for the biasing and the internal drivers.
Other features of NX2601 are: programmable frequency
from 200kHz to 1MHz, independent digital soft start and
enable pins for each controller which allows for different
power sequencing, Adaptive driver provides optimized ef­ficiency while maintain sufficient deadband, Vcc
undervoltage lock out and current limiting using an Rds­on of the external MOSFET with HICCUP feature.

10

C16

R15

62k

1nF

R11

11

10

9

8

7

3

1

2

6

30
31

REG FB

REG OUT
AUXVCC
LDO OUT

LDO FB

ENLDO

ENSW1

ENSW2

RT

VP
VREF

C15
1uF

5

VCC

HDRV1

PGND1

N X 2 6 0 1

PGND2

GND

4

1uFC24

150pF

R17

2.35k

C25
1uF

R21

1.25k

R12
5k

R13

1.65k

C18

Figure1 - Typical application of 2601

+5V

VIN1

VIN2

+3.3V

C20

150uF

VOUT3

+2.5V/2A

OFF

R25

10k

ON

2N3904

R26

10k

VIN1

ON

PATENT PENDING

2N3904

R18

1.5k

OFF

C17

68uF

47pF

5k

M5

0

R16

C19

5k

150uF

R19

1.25k

R20

6.8k

R27

10k

2N3904

R28

10k

R24

C21

n Two channel PWM with out of phase operation
n Individual digital soft start for two PWM output

and LDO controller

n Bus voltage operation from 2V to 25V
n Hiccup Current limit by sensing Rdson of MOSFET
n Adjustable frequency up to 1Mhz per channel
n Adaptive deadband time
n Three enable pin available allows for independent

power sequencing

n MLPQ-32L package offers small size
n Pb-free and RoHS compliant

APPLICATIONS

n PCI Graphic Card on board converters
n Vddq Supply in mother board applications
n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n FPGA and Set Top Box Applications

TYPICAL APPLICATION

C1

PVCC1

BST1

SW1

OCP1

LDRV1

Fb1

Comp1

PVCC2

BST2

HDRV2

SW2

OCP2

LDRV2

Fb2

Comp2

23

24

25

26
27

22
21
29

28

18

17

16

15
14

19
20

12

13

1uF

R1

R5 5k

C8
1uF

R6

C22

C23

10.5k

6k

R10
5k

D1

C4

0.1uF

220pF

D2

C11

0.1uF

220pF

+5V

M1

M2

+5V

C12

10nF

C58.2nF

L2 0.78uH

M3

L4 1.5uH

M4

L1 1uH

C2

180uF

2.7nF

C9

180uF

3.3nF

R2

1.5k
C6

R7

820
C13

C3

100uF

R4

20.8k

R9

6.97k

C7
2 x (2R5TPD680M6,680uF,6mohm)

R3

10.4k

C14
3 x (4TPE150M,150uF,18mohm)

R8

8.7k

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX2601CMTR 0 to 70oC MLPQ-32L 200kHz to 1MHz Yes

FEATURES

VIN1
+12V

VOUT1
+1.2V@15A

VOUT2
+1.8V/10A

Rev. 2.3
12/01/06

1

NX2601

C/W

ABSOLUTE MAXIMUM RATINGS

Vcc,PVcc & BST to SW voltage ......................... 6.5V

BST Voltage ...................................................... 35V

SW ................................................................... -5V(Note1) to 35V

AUXVCC .......................................................... 35V

All other pins .................................................... GND to Vcc+0.3V

Storage Temperature Range ............................... -65oC to 150oC

Operating Junction Temperature Range ............... -40oC to 125oC

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

32-LEAD 5x5 PLASTIC MLPQ

COMP1

FB1

VP

VREF

28293031

NX2601

101112 13 14

FB2

COMP2

REG FB

REG OUT

27

OCP1

26

15 16

OCP2

SW1

SW2

HDRV1

25

HDRV2

BST1

24

PVCC1

23

LDRV1

22

PGnd1

21

PGnd2

20
19

LDRV2
PVCC2

18
17

BST2

θ≈35

o

JA

ENSW1
ENSW2
ENLDO

GND

VCC

LDO FB

LDO OUT

NC

32
1
2
3
4
5

RT

6
7
8

9

AUXVCC

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc = 5V, V
ENLDO=HIGH, and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which
keeps junction and case temperatures equal to the ambient temperature.

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

Reference Voltage

FB Voltage

V

4.5 < Vcc < 5.5

REF

FB Voltage Line Regulation

Vcc Supply Voltage

Vcc Voltage Range
Vcc Static Supply Current

Vcc Dynamic Supply
Current
V

Voltage Range

BST

V

Static Supply Current

BST

V

Dynamic Supply

BST

Current

Rev. 2.3
12/01/06

V
I
I

I

I

CC

CC_STA

CC_DYN

V

BST
BST_STA
BST_DYN

Outputs not switching
Freq=600kHz,
C

= 3300pF

LOAD

Outputs not switching
Freq = 600KHz,
C

= 3300pF

LOAD

BST-VSW

=5V, ENSW1=HIGH, ENSW2=HIGH,

4.5

4.5

0.800

0.4

5.0

5.5

2.0
8

4.

5.0

5.5

2.0

TBD

V

%

V
mA
mA

V
mA
mA

2

NX2601

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Under Voltage Lockout

UVLO Threshold - Vcc V
UVLO Hysteresis - Vcc V
UVLO Threshold - V
UVLO Hysteresis - V

AUXVcc

AUXVcc VAUX_HYST

V

CC_UVLO
CC__HYST
AUX_UVLO

Error Amplifiers

Open Loop Gain
Input Bias Current
Input Offset Voltage

Oscillator

Frequency F

Ramp Amplitude V

EN & SS

Soft Start Time T
Enable Threshold Voltage
Enable Hysterises

LDO Controller

LDO FB Voltage
FB Pin Bias Current
LDO_out Output Voltage High

LDO_out Output Voltage Low

Open Loop Gain

5V AUX REG

REG FB Voltage
FB Pin Bias Current
REG_out Output Voltage
High
REG_out Output Voltage
Low
Open Loop Gain

High Side driver
(CL=3300pF)

Output Impedance, Sourcing R

source_H

Current
Output Impedance , Sinking R

sink_H

Current
Rise Time T
Fall Time T
Deadband Time T

HDRV_RISE

HDRV_FALL

DEAD_LH

RAMP

SS

Supply Ramping Up
Supply Ramping Down
Supply Ramping Up
Supply Ramping Down

Rt=30k,measured at the

S

output drive

Fs=600KHz

Enable ramp up

LDOOUT=LDOFB

AUXVCC=24V,LDO FB=0.7V
I

O_SOURCE

=1.4mA
AUXVCC=24V,LDO FB=0.9V
I

=1.4mA

O_SINK

GBNT(Note2)

REGOUT=REGFB

AUXVCC=24V,REG FB=1.1V
I

O_SOURCE

=1.4mA
AUXVCC=24V,REG FB=1.4V
I

=1.4mA

O_SINK

GBNT(Note2)

10% to 90%
90% to 10%
LDRV going Low to HDRV
going High, 10% to 10%

-0.2
22

50

-0.2
22

50

4

0.2
7

0.7

65

0.3
0

600

1

3.41

1.25
100

0.8
0

23.5

0.2

1.25
0

23.5

0.2

0.85

0.65

25
20
30

V
V
V
V

dB
uA

mV

KHz

V

mS

V

mV

V

µA

V

V

dB

V

µA

V

V

dB

ohm

ohm

ns
ns
ns

Rev. 2.3
12/01/06

3

NX2601

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Low Side driver
(CL=3300pF)

Output Impedance, Sourcing R
Current
Output Impedance , Sinking R
Current
Rise Time T
Fall Time T
Deadband Time T

Note 1: 500ns transient. This pin can withstand -2V DC.
Note 2: This parameter is guaranteed by design but not tested in production(GBNT).

source_L

sink_L

LDRV_RISE

LDRV_FALL

DEAD_HL

10% to 90%
90% to 10%
SW going Low to LDRV going
High, 10% to 10%

0.85

0.5
25
20
20

ohm

ohm

ns
ns
ns

Rev. 2.3
12/01/06

4

PIN DESCRIPTIONS

PIN # PIN SYMBOL PIN DESCRIPTION

A resistor divider is connected from the respective switcher BUS voltages to these

1
2

3

ENSW1
ENSW2

ENLDO

pins that holds off the controllers soft start until this threshold is reached. An
external low cost MOSFET or NPN transisitor can be connected to this pin for
external enable control.

A resistor divider is connected from the LDO bus voltage to this pin that holds off
the LDO soft start until this threshold is reached. An external low cost MOSFET
can be connected to this pin for external enable control.

NX2601

10

4

5

6

7

8

9

GND

VCC

RT

LDO FB

LDO OUT

AUXVCC

REGOUT

RER

Analog ground.
IC's supply voltage. This pin biases the internal logic circuits. A high freq 1uF

ceramic capacitor is placed as close as possible to and connected to this pin and
ground pin.

Oscillator's frequency can be set by using an external resistor from this pin to
GND. This frequency is the master clock frequency which is internally divided by
two to set each controller frequency.

LDO controller feedback input. If the LDOFB pin is pulled below 0.5*Vref, an
internal comparator after certain delay and pulls down LDOOUT pin and initiates
the HICCUP circuitry. During the startup this latch is not activated, allowing the
LDOFB pin to come up and follow the Soft started Vref voltage.

LDO controller output. This pin is controlling the gate of an external NCH
MOSFET. The maximum rating of this pin is 16V.

This pin is the supply voltage for the LDO controller as well as the 5V regulator
controller that regulates the voltage at Vcc derived from the BUS voltage. The
maximum voltage applied to this pin is 30V.

The output of the 5V regulator controller that drives a low current low cost external
BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin
derived from BUS voltage. This eliminates an otherwise external regulator needed
in applications where 5V is not available.

Rev. 2.3
12/01/06

11

12
29
13
28

REGFB

FB2

FB1
COMP2
COMP1

Feedback pin of the 5V regulator controller. A resistor divider is connected from
the output of the 5V regulator to this pin to complete the loop.

This pin is the error amplifiers inverting input. These pins are connected via
resistor dividers to the output of the switching regulators to set the output DC
voltage.

These pins are the outputs of error amplifiers and are used to compensate the
respective voltage control feedback loops.

5

PIN DESCRIPTIONS

PIN # PIN SYMBOL PIN DESCRIPTION

This pin is connected to the drain of the external low side MOSFET and is the

14

27

15
26

OCP2

OCP1

SW2
SW1

input of the over current protection(OCP) comparator. An internal current source
which equals 1.25V divided by Rt resistor is flown to the external resistor which
sets the OCP voltage across the Rdson of the low side MOSFET. Current limit
point is this voltage divided by the Rds-on. Once this threshold is reached the
Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that
recycles the soft start circuit after 2048 switching cycles.

These pins are connected to source of high side FETs and provide return path for
the high side drivers. They are also used to hold the low side drivers low until this
pin is brought low by the action of high side turning off. LDRVs can only go high if
SW is below 1V threshold .

NX2601

16
25

17
24
18
23
19

22
20

21

30

31

HDRV2
HDRV1

BST2

BST1
PVCC2
PVCC1

LDRV2
LDRV1

PGND2
PGND1

VP

VREF

High side gate driver outputs.

This pin supplies voltage to high side FET driver. A high freq 1uF ceramic capaci­tor is placed as close as possible to and connected to these pins and respected
SW pins.

Supply voltage for the low side fet drivers. A high frequency 1uF ceramic cap must
be connected from this pin to the PGND1 and PGND2 pin as close as possible to
the pins.

Low side gate driver outputs.

Power ground pin for low side drivers.

This pin is the first error amplifier non-inverting input. This pin should be con­nected either to an external reference voltage (tracking application) or to the
internal reference voltage provided by this device.

Reference voltage available. A 100pF capacitor can be connected from this pin to
GND. This pin is held low until internal Vcc UVLO and the ENSW1 pin are good,
allowing it to soft start.

Rev. 2.3
12/01/06

32

NC

6

BLOCK DIAGRAM

AUXVCC

Bias

NX2601

REGFB

REGOUT

VCC

Vref

ENSW1

RT

VP

FB1

COMP1

ENSW2

FB2

COMP2

1.25/1.15

Bias
Generator

Digital
start Up

9.6/9.2

1.25V

two phase
OSC

ramp1

4/3.8

0.8V

Channel 1 PWM Controller

Channel 2 PWM controller (exclude oscillator)

set1

UVLO

UVLO

POR_LDO

POR_SW

BST1

DRVH1

Control
Logic

S
R

POR_SW

Q

OCP
comparator

SW1

PVCC1

DRVL1

PGND1

OCP1

BST2

DrvH2
SW2

PVCC2

DrvL2

PGND2

OCP2

Rev. 2.3
12/01/06

ENLDO

GND

1.25/1.15
POR_LDO

LDO
control
logic

digital
start up

0.4

LDOOUT

FBLDO

7

+5V

VIN1

VIN3

+3.3V

VOUT3

+2.5V/2A

C8

33uF

C5

150uF

VIN1

VIN2

C4

150uF

NX2601

10

R19

47pF

0

R2

R16
5k

C7

R15

1.65k

R10

C3

150pF

R6

2.35k

R5

1.25k

R4

1.25k

R3

1.25k

62k

100pF

R1
1k

100pF

C17

68uF

R13
5k

Q2

M5

R11

5k

R7

1.5k

R8

6.8k

R9

2.7k

C1

C2

11

10

9
8

7

3

1

2

6

30

31

REG FB

REG OUT
AUXVCC
LDO OUT

LDO FB

ENLDO

ENSW1

ENSW2

RT

VP

VREF

C10
1uF

5

VCC

N X 2 6 0 1

GND

4

PVCC1

BST1

HDRV1

SW1

OCP1

LDRV1

PGND1

Comp1

PVCC2

BST2

HDRV2

SW2

OCP2

LDRV2

PGND2

Comp2

Fb1

Fb2

C41

23

24

25

26
27

22
21

29
28

18

17

16

15
14

19
20

12

13

1uF

R22

C42
1uF

R32

C18

R24

C32

5k

5k

R33

10.5k

3k

D1

C11

0.1uF

220pF

D2

C31

0.1uF

220pF

Q4

Q5

+5V

8.2nF
C17

+5V

Q6

Q7

C37

10nF

C24

1uF

L1 0.78uH

R23
20k

C12

470pF

C38
1uF

L3 1.5uH

R34
20k

C34

470pF

L2 1uH

R26

1.5k

C19

2.7nF

330

C25

8.2nF

C23

180uF

R28

R25

20.8k

L4 1uH

180uF

R35

2.7k

R27

10.4k

C36

R29

3.5k

C21

39uF

C13,C14
680uF,6mohm

C33

39uF

C26,27,28

150uF,18mohm

VIN1
+12V

VOUT1
+1.2V@15A

VIN2
+5V

VOUT2
+1.8V@10A

Rev. 2.3
12/01/06

Simplified Demo board schematic

8

NX2601

SW1_IN

16TQC33M

TP1

C5

4TPE150M

LDO_OUT

TP2

J1

234

5

J9

1
2

LDO_IN
LDO_IN

SW2_IN

SW2_IN

SW1_IN

TP3

R17

0

LDO_IN

1

C6

.1u

LDO_OUT

J8

1
2
3
4
5
6
7
8
9

10

Q3

OP

Q2

C8

2N3904

4.99k

Q1

MTD3055E

C4

4TPE150M

11

LDO_IN

12
13
14
15
16
17
18
19

SW2_IN

20

SW2_IN

R13

0

R12

0

R11

4.99k

LDO_IN

SW1_IN

SW2_IN

TP6

R36

1k

R14

C7

47p

R16

4.99k

R15

1.65k

C3

150pf

R10

0

R6

2.35k

R7

1.5k

R5

1.25k

R8

6.8k

R4

1.25k

R9

2.7k

R3

1.25k

R2

62k

C1

100p

C2

100p

R19

R18

C9

6TPB68M

11

10

32

30

R1

1k

31

10

0

U1

REG_Fb

REG_OUT

9

AUX_VCC

8

LDO_OUT

NC

7

LDO_FB

3

EN_LDO

1

EN_SW1

2

EN_SW2

6

Rt

Vp

Vref

PVCC

TP7

NX2601_MLPQ

AGND

4

5

VCC

BST1

Hdrv1

SW1

OCP1

Ldrv1

PVCC1

PGND1

Fb1

Comp1

BST2

Hdrv2

SW2

OCP2

Ldrv2

PVCC2

PGND2

Fb2

Comp2

C10

1u

24

25

26
27

op

22
23

21
29

28

17

16

15
14

19
18

20
12

13

J6

234

D1N5819

C11

.1u

SW1

C20

C41

1u

C17

220p

R24

4.99k

D2

D1N5819

C31

.1u

SW2

C30

op

C42

1u

C32

220p

R33

4.99k

1

5

D1

R20

0

R22

10.5k

R21

0

PVCC

C18

8.2n

PVCC

R30

0

R32

3k

R31

0

IRF7822

PVCC

C37

10n

SW1

PVCC

IRF3706

IRF3706

R25

20.8k

4

4

Q7

R35

2.7k

8

8

Q4

Q5

567

123

567

123

J7

1

SW2

234

5

Vcc1

TP4

L2

DO1603C-102

C21

16SVPA39MAA

L1

C24

16SVPA180M

1u

SW1_OUT

C23

C22

OP

DO5010P-781HC

R23

20k

C12

470p

R26

1.5k

R27

10.4k

C19

2.7n

Vcc2

C13

2R5TPD680M6

C14

2R5TPD680M6

C15

Op

C16

OP

1

C39

.1u

TP5

L4

DO1603C-102

C33

16SVPA39MAA

Q6

IRF7822

L3

C38

1u

16SVPA180M

SW2_OUT

C36

C35

OP

DO5010P-222HC

R34

20k

C34

470p

R28

330

R29

3.5k

C25

8.2nF

C26

4TPE150M

C27

4TPE150M

C28

4TPE150M

C29

op

1

C40

.1u

PACKAGE: MLPQ32L

Size Document Number Rev

NX2601-02 EVL BRD SCHEMATIC

Date: Sheet of

1 1Thursday, March 24, 2005

SW1_IN

J2

1
2

J4

5

SW2_IN

J3

1
2

J5

5

234

234

A

Rev. 2.3
12/01/06

Figure 2 - Demo board schematic based on ORCAD

9

Bill of Materials

Item number

Quantity Value Manufacture
1 2 C2,C1 100p
2 1 C3 150pf
3 5 C4,C5,C26,C27,C28 4TPE150M SANYO
4 5 C6,C11,C31,C39,C40 .1u
5 1 C7 47p
6 1 C8 16TQC33M SANYO
7 1 C9 6TPB68M SANYO
8 5 C10,C24,C38,C41,C42 1u
9 2 C12,C34 470p

10 2 C14,C13 2R5TPD680M6 SANYO
11 9 Q3,R14,C15,C16,C20,C22, OP

C29,C30,C35
12 2 C17,C32 220p
13 1 C18 8.2n
14 1 C19 2.7n
15 2 C21,C33 16SVPA39MAA SANYO
16 2 C36,C23 16SVPA180M SANYO
17 1 C25 8.2nF
18 1 C37 10n
19 2 D1,D2 D1N5819
20 5 J1,J4,J5,J6,J7 SCOPE TP Tektronics
21 3 J2,J3,J9 CON2
22 1 J8 CON20B
23 1 L1 DO5010P-781HC Coilcraft
24 2 L2,L4 DO1603C-102
25 1 L3 DO5010P-222HC
26 1 Q1 MTD3055E
27 1 Q2 2N3904
28 2 Q4,Q5 IRF3706 International Rectifier
29 2 Q7,Q6 IRF7822 International Rectifier
30 1 R1 1k
31 1 R2 62k
32 3 R3,R4,R5 1.25k
33 1 R6 2.35k
34 2 R7,R26 1.5k
35 1 R8 6.8k
36 2 R35,R9 2.7k
37 8 R10,R12,R17,R18,R20,R21, 0

R30,R31
38 5 R11,R13,R16,R24,R33 4.99k
39 1 R15 1.65k
40 1 R19 10
41 1 R22 10.5k
42 2 R34,R23 20k
43 1 R25 20.8k
44 1 R27 10.4k
45 1 R28 330
46 1 R29 3.5k
47 1 R32 3k
48 1 R36 10k
49 7 TP1,TP2,TP3,TP4,TP5,TP6, TP

TP7
50 1 U1 NX2601_MLPQ NEXSEM INC.

NX2601

Rev. 2.3
12/01/06

10

Demoboard waveforms

NX2601

Figure 3 - Start up waveform of VCC by internal regulator.
Ch1(AUXVCC), Ch3( VCC&PVCC)

1.8V output

Figure 6 - Output ripple for power output CH1 and CH2

Figure 7-Transient response for first channel 1.2V outputFigure 4 - Soft start for Channel 1 1.2V and chanel 2

Figure 5 - Soft start for Channel 1 1.2V and LDO output

Rev. 2.3
12/01/06

Figure 8 -Transient reponse for Channel 1. (zoomed)

11

Demo Board Waveforms (Cont')

NX2601

Figure 9 - Ch2 1.8V output transient 0 to 9A.

Figure 10 - Ch2 1.8V transient (zoomed)

Figure 12 - Ch1 is short. All channels go into hiccup.

Figure 13 - Ch2 is in short. All channels are in hiccup.

Figure 11 - Transient response for 2.5V LDO output

Rev. 2.3
12/01/06

Figure 14 - LDO in short. All channels go into hiccup.

12

NX2601

RIPPLEINS

1

IVF

0.315A12V300kHz

=4.6A

SOUT

==Ω

ESR=4.3m

ERIPPLE

6m4.6A

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple

Design Example

Power stage design requirements:
VIN=12V
VOUT=1.2V
IOUT =15A
DVRIPPLE<=20mV
DVTRAN<=100mV @ 15A step
FS=300kHz

Output Inductor Selection

The selection of inductor value is based on induc­tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and higher cost. Usually
the ripple current ranges from 20% to 40% of the output
current. This is a design freedom which can be decided
by design engineer according to various application re­quirements. The inductor value can be calculated by using
the following equations:

V-VV

OUT

∆

INOUT OUT

××

×

12V-1.2V1.2V1

OUT

OUT

×

××

...(1)

L=
I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.3, then

L=
L=0.8uH

Choose LOUT=0.78uH, then coilcraft inductor
DO5010P-781HC is a good choice.

Current Ripple is calculated as

V-VV

I=

∆××

RIPPLE

INOUT OUT

LVF

OUTINS

12V-1.2V1.2V1

0.78uH12V300kHz

××=

1

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C

is the value of output capacitors.

OUT

Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.

For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically de­termines the output voltage ripple.

desire

V

RIPPLE

∆

I4.6A

RIPPLE

20mV

∆

If low ESR is required, for most applications, mul­tiple capacitors in parallel are better than a big capaci­tor. For example, for 20mV output ripple, POSCAP
2R5TPD680M6 with 6mΩ are chosen.

ESRI

N

=

∆

×∆

V

RIPPLE

Number of Capacitor is calculated as

20mV

Ω×

=

N

N =1.38

The number of capacitor has to be round up to a
integer. Choose N =2.

RIPPLE

××

8FC

...(3)

...(4)

...(5)

Rev. 2.3
12/01/06

13

NX2601

tran

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.33H

=µ

6m680F5.67us

2

(5.67us)

1.3×∆=+×τ

If ceramic capacitors are chosen as output ca­pacitors, both terms in equation (3) need to be evaluated
to determine the overall ripple. Usually when this type of
capacitors are selected, the amount of capacitance per
single unit is not sufficient to meet the transient specifi­cation, which results in parallel configuration of multiple
capacitors.

Based On Transient Requirement

Typically, the output voltage droop during transient
is specified as

∆V

droop

∆V

<

@step load DI

STEP

During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot
when load from high load to light load with a DI

STEP

tran­sient load, if assuming the bandwidth of system is high
enough, the overshoot can be estimated as the following
equation.

V

VESRI

overshootstep

OUT

2LC

××

OUT

...(6)

where τ is the a function of capacitor, etc.

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(7)

where

ESRCVESRCV

××××

==

II

∆∆

stepstep

...(8)

L

crit

where ESRE and CE represents ESR and capaci­tance of each capacitor if multiple capacitors are used
in parallel.

The above equation shows that if the selected out­put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-

pacitance is high and

≤ is true. In that case, the

transient spec is likely to dependent on the ESR of ca­pacitor.

For most cases, the output capacitors are mul-

tiple capacitor in parallel. The number of capacitors can
be calculated by the following

ESRI

×∆

N

Estep

V2LCV

∆×××∆

tranEtran

V

OUT

...(9)

where

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(10)

For example, assume voltage droop during tran-

sient is 100mV for 15A load step.

If the POSCAP 2R5TPD680M6 (680uF, 6mohm

ESR) is used, the crticial inductance is given as

ESRCV

××

EEOUT

==

I

∆

step

L

crit

6m680F1.2V

Ω×µ×

15A

The selected inductor is 0.78uH which is bigger
than critical inductance. In that case, the output voltage
transient not only dependent on the ESR, but also ca­pacitance.

number of capacitors is

LI

×∆

step

τ=−×

V

OUT

0.78H15A

µ×

=−Ω×µ=

1.2V

ESRI

N

6m15A

Ω×

=+

100mV

20.78H680F100mV

×µ×µ×

ESRC

EE

Estep

V2LCV

∆×××∆

tranEtran

1.2V

V

OUT

×

2

=

The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.

It should be considered that the proposed equa­tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more capaci­tors have to choose after the test. Typically, for high

Rev. 2.3
12/01/06

14

NX2601

F ...(11)

F ...(12)

F ...(13)

F ...(14)

[

]

42233

(1sRC)1s(RR)C

frequency capacitor such as high quality POSCAP es­pecially ceramic capacitor, 20% up 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitics can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.

Compensator Design

Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin.Ideally,the Bode
plot of the closed loop system has crossover frequency
between1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0db with ­20db/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than cross­over frequency. Otherwise type III compensator should
be chosen.

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator. Their locations are shown in figure 15.

The transfer function of type III compensator is

given by:

V

e

=×

VsR(CC)

OUT 221

1

×+

Vout

Zin

R3

+××++×

CC

×

(1sR)1sRC

+××+×

21

433

CC

21

+

( )

Zf

C1

C2

R4

R2

C3

Fb

Ve

R1

Vref

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo OSCON and POSCAP, the frequency of ESR zero
caused by output capacitors is higher than the cross­over frequency. In this case, it is necessary to compen­sate the system with type III compensator. The follow­ing figures and equations show how to realize the type III
compensator by voltage mode amplifier.

1

2RC

×π××

42

1

2(RR)C

×π×+×

233

1

2RC

×π××

33

1

CC

×

2R

×π××

4

CC

12

+

12

=

Z1

=

Z2

=

P1

=

P2

power stage

LC

F

Gain(db)

40dB/decade

loop gain

ESR

F

20dB/decade

compensator

F

Z1 Z2

F

F

O

F

P1

F

P2

Figure 15 - Type III compensator and its bode plot

Rev. 2.3
12/01/06

15

The crossover frequency usually is selected as

LC

F

ESR

F

20.78uH1320uF

23m1360uF

R=20.8k

==Ω

=(-)

210.4k4.89kHz39kHz

=2.8nF

=1360uF

20.754.89kHz5k

×π×××Ω

25k150kHz

239kHz2.7nF

Gain= ... (15)

F= ... (16)

F= ... (17)

FLC<FO<F

and FO<=1/10~1/5F

ESR,

for type III

s

compensator .

1.Calculate the location of LC double pole

and ESR zero

F

LC

=

2LC

×π××

=

.

1

OUTOUT

1

×π××

4.89kHz

=

F

=

ESR

=

39kHz

=

2.Set R

RV

1

V-V1.2V-0.8V

2ESRC

×π××

×π×Ω×

equal to10.4kΩ.

2

×

2REF

OUT REF

1

OUT

1

10.4k0.8V

Ω×

Choose R1= 20.8kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

ESR

.

4. Calculate R4 and C3 with the crossover frequency
smaller than 1/10~ 1/5 of the swithing frequency. Set
FO=25kHz.

C=(-)

3

111

2RFF

×π×

×π×Ω

×

2z2p1

111

×

Choose C3=2.7nF.

V2FL

R=C

4out

VC

1V225kHz0.8uH

12V2.7nF

=5.3k

×π××

OSCO

××

in3

×π××

××

Ω

Choose R4=5k

5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).

NX2601

C

=

2

2FR

=

8.8nF

=

Choose C2=8.2nF

6. Calculate C1 by equation (14) with pole Fp2 at

half the swithing frequency.

C

=

1

=

212pF

=

Choose C1=220pF

7. Calculate R3 by equation (13).

1

×π××

Z14

1

1

2RF

×π××

4P2

1

×π×Ω×

R

=

3

=

1.5k

=Ω

Choose R3= 1.5kΩ.

B. Type II compensator design

If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa­tor can be used to compensate the system.

Type II compensator can be realized by simple
RC circuit as shown in figure 16.R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise. The following equa­tions show the compensator pole zero location and con­stant gain.

z

2RC

p

2RC

1

2FC

×π××

P13

1

×π××

R

3

R

2

1

×π××

31

1

×π××

32

Rev. 2.3
12/01/06

16

NX2601

21.5uH4500uF

26.33m4500uF

=10k

=24.8k

××Ω

224.8k0.751.94kHz

p

F

24.8k200kHz

Vout

R2

R1

power stage

Gain(db)

loop gain

Vref

Fb

R3

C2

C1

40dB/decade

20dB/decade

Ve

F

=

LC

2LC

×π××

=

1

OUTOUT

1

×π××

1.94kHz

=

F

=

ESR

2ESRC

=

5.6kHz

=

2.Set crossover frequency FO=20kHz>>F

1

×π××

OUT

1

×π×Ω×

ESR

.

3. Set R2 equal to10kΩ. Based on output voltage,

using equation 18, the final selection of R1 is 20kΩ.

4.Calculate R3 value by the following equation.

V2FL

R=R

OSCO

32

VESR

in

1V220kHz1.5uH

12V6.33m

×π××

××

×π××

Ω

Ω

compensator

Gain

F

F

LC

Z

ESRFO

P

F

F

Figure 16 - Type II compensator and its bode plot

For type II compensator, FO has to satisfy

FLC<F

<<FO<=1/10~1/5F

ESR

s.

The following parameters are used as an ex­ample for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P­152HC 1.5uH is used as output inductor. The other
power stage information is that:

V

IN=12V, VOUT=1.2V, IOUT =15A, FS=200kHz.

1.Calculate the location of LC double pole F

and ESR zero F

ESR

.

LC

Choose R3 =24.8kΩ.

5. Calculate C1 by setting compensator zero F

at 75% of the LC double pole.

C=

1

=

1

2RF

×π××

3z

1

×π×Ω××

=4.4nF

Choose C1=4.7nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

C=

2

=

1

RF

π××

3s

1

π×Ω×

=64pF

Choose C2=68pF

Z

Rev. 2.3
12/01/06

17

NX2601

OUT

REF

2REF

OUT REF

R1.6V1.6V/(1/16W)40

=×=Ω

IID1-D

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

Output Voltage Calculation

Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation and picture show the relationship
between

V ,

R=

1

V and voltage divider..

RV

×

V-V

...(18)

where R2 is part of the compensator, and the
value of R1 value can be set by voltage divider.

Choose R2=10kΩ, to set the output voltage at

1.8V, the result of R1 is 8kΩ.

Vout

R2

Fb

R1

Vref

Voltage divider

Figure 17 - Voltage divider

In general, the minimum output load impedance
including the resistor divider should be less than 5kΩ to
prevent overcharge the output voltage by leakage cur­rent (e.g. Error Amplifier feedback pin bias current). A
minimum load for 5kΩ less (<1/16w for most of applica­tion) is recommended to put at the output. For example,
in this application,

Vout=1.6V

The power loss is 1/16W less

LOAD

Select minimum load is 1kΩ should be good
enough.

Input Capacitor Selection

Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca­pacitors bypass the high frequency noise, and bulk ca-

pacitors supply current to the MOSFETs. Usually 1uF
ceramic capacitor is chosen to decouple the high fre­quency noise. The bulk input capacitors are decided by
voltage rating and RMS current rating. The RMS current
in the input capacitor can be calculated

=××

RMSOUT

V

OUT

D

=

V

IN

...(19)
VIN = 12V, VOUT=1.2V, IOUT=15A, using equation
(19), the result of input RMS current is 4.5A.

For higher efficiency, low ESR capacitors are

recommended.

Two Sanyo OS-CON SVPA180M 16V 180uF

29m

O with 3.4A RMS rating are chosen as input bulk

capacitors.

Power MOSFETs Selection

The NX2601 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, I
=75A,R

=9mΩ,Q

DSON

GATE

=23nC.

There are three factors causing the MOSFET power
loss:conduction loss, switching loss and gate driver loss.

Gate driver loss is the loss generated by discharg­ing the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:

...(20)

where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V

LGS

is

the low side gate source voltage.

According to equation (3), PGATE =0.07W. This
power dissipation should not exceed maximum power
dissipation of the driver device.

Conduction loss is simply defined as:

D

Rev. 2.3
12/01/06

18

NX2601

P=I(1D)RK

×−××

SWINOUTSWS

PVITF

=××××

R6.8k

==Ω

Frequency(khz)

P=IDRK

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

2

×××

2

+

...(21)

where the RDS(ON) will increases as MOSFET junc­tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K equals to 1.4 at 125oC
according to IRFR3706 datasheet. Using equation (4),
the result of PTOTAL is 0.54W. Conduction loss should
not exceed package rating or overall system thermal
budget.

Switching loss is mainly caused by crossover con­duction at the switching transition. The total switching
loss can be approximated.

1
2

...(22)

where IOUT is output current, TSW is the sum of TR and
TF which can be found in mosfet datasheet, and FS is
switching frequency. The result of PSW is 1.5W.
Swithing loss PSW is frequency dependent.

Soft Start and Enable

NX2601 has two switching controller and one LDO
controller. Each of them has individual digital soft start.
Each channel has one enable pin for start up. When the
Power Ready (POR) signal is high and the voltage at
enable pin is above 1.25V, the internal digital counter
starts to operate and the voltage at positive input of Error
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the de­sired voltage decided by the feedback resistor divider

The start up of NX2601 can be programmed through
resistor divider at Enable pin. For example, for channel
1, if the input bus voltage is 12V and we want NX2601
starts when Vbus is above 8V. We can select

R2=1.24k

(8V1.25V)R

1

1.25V

−×

2

The NX2601 can be turned off by pulling down the
ENable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin (ENSW1) is below 1.15V,
the digital soft start is reset to zero. In addition, all the
high side is off and output voltage is turned off.

Frequency Selection

The frequency can be set by external Rt resistor.
The relationship between frequency and RT pin is shown
as follows.

Frequency(kHz) vs. RT

900
800
700
600
500
400
300
200
100

0

20 30 40 50 60 70

Rt(kohm)

Vbus

+

OFF

ON

10k

R1

R2

Figure 18 - Enable and Shut down the NX2601

with Enable pin.

Rev. 2.3
12/01/06

ENSW1

1.25/1.15

POR

Digital
start
up

Figure 19 - Frequency versus Rt resistor

For example, for 300kHz operation, Rt is about
62kohm.

Over Current Limit Protection

Over current limit for step down converter is
achieved by sensing current through the low side

19

NX2601

1.25

I=

SWLDSON

IR+V

IIR/R

I20uA

RR9mohm9kohm

RDSONLDOINLDOOUTLOAD

(3.3V2.5V)/2A0.4

=−=Ω

(3.3V2.5V)2A1.6W

C=

2FR1+gESR

C= =155pF

×Ω

MOSFET. Inside NX2601, the current through Rt pin is
mirrored and injecting to the pin OCP. Since the current
through Rt pin is decided as

RT

R

t

This current is very accurate and does not change
with silicon process and temperature, the over current
limit tripping point can be set more accurate than tradi­tional current source. This scheme is the property of
Nexsem. When synchronous FET is on, the voltage at
node SW is given as

V=-IR×

The voltage at pin OCP is given as

×

OCPOCPSW

When the voltage is below zero, the over current
occurs. The over current limit can be set by the following
equation

=×

SETRTOCPDSON

For example, For 20A current limit and 9mohm
Rdson for IRFR3706, the OCP set resistor is calculated
as

1.25V

limit, the other channels include LDO will go to hiccup
too.

==

RT

62k

I

SET

=×=×=

OCPDSON

I20uA

RT

20A

Select OCP set resistor R=10.5k.

For NX2601, if one channel goes to hiccup current

important is that MOSFET has to be selected right pack­age to handle the thermal capability. For LDO, maxi­mum power dissipation is given as

P(VV)I

=−×

LOSSLDOINLDOOUTLOAD

=−×=

Select IR MOSFET IRFR3706 with 9mΩ R

DSON

is

sufficient.

LDO Compensation

The diagram of LDO controller including VCC regu­lator is shown in above figure 20. For low frequency
capacitor such as electrolytic, POSCAP, OSCON, etc,
The compensation parameter can be calculated as fol­lows.

gESR

C

×π×××

Of1m

where FO is the desired loop gain.

1

Vref

R

f1

R

f2

Rc Cc

Figure 20 - NX2601 LDO controller.

×

m

×

LDO input

+

ESR

Rload

Co

LDO Selection Guide

NX2601 offers a LDO controller. The selection of
MOSFET to meet LDO is more straight forward. The
selection is that the Rdson of MOSFET should meet
the dropout requirement. For example.

V

=3.3V

LDOIN

V

I

Load

The maximum Rdson of MOSFET should be

R(VV)I

Most of MOSFETs can meet the requirement. More

Rev. 2.3
12/01/06

=2.5V

LDOOUT

=2A

=−×

Typically, FO has to be higher than zero caused by
ESR. FO is typically around several tens kHz to a few
hundred kHz. For this example, we select Fo=100kHz.
gm is the forward trans-conductance of MOSFET.

For IRFR3706, gm=53.

Select Rf1=5kohm.

Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.

C

15318m

2100kHz5k1+5318m

×π××Ω×Ω

×

Choose CC=150pF.

20

NX2601

5k0.8V/(2.5V0.8)2.35k

=Ω×−=Ω

For electrolytic or POSCAP, RC is typically
selected to be zero.

Rf2 is determined by the desired output voltage

RRV/(VV)

=×−

f2f1REFLDOOUTREF

Choose Rf2=2.34kΩ.

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below 0.4V,
the IC goes into hiccup mode. The IC will turn off all the
channel (Channel 1 and Channel 2 ) for 2096 cycles and

start to restart system again.

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

There are two sets of components considered in
the layout which are power components and small sig­nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch­ing power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in­cludes power plane, ground plane and signal plane is
recommended .

Layout guidelines:

1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.

2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch­ing the drain pin of the upper MOSFET, a plane connec­tion is a must.

3. The output capacitors should be placed as close

as to the load as possible and plane connection is re­quired.

4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.

5. Source of the lower MOSFET needs to be con­nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by­passing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.

8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.

9. All GNDs need to go directly thru via to GND
plane.

10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.

11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana­log control function.

Rev. 2.3
12/01/06

21

TYPICAL APPLICATIONS

10

R15

100k

1nF

1uF

150pF

R17

2.35k

R21

1.25k

R23

1.25k

R12
5k

R13

1.65k

C18

R19

1.25k

R11

11

10

9
8

7

3

1

2

6

30
31

REG FB

REG OUT
AUXVCC

LDO OUT

LDO FB

ENLDO

ENSW1

ENSW2

RT

VP
VREF

+5V

VIN2

+3.3V

VOUT3

+2.5V/2A

OFF

ON

VIN1

R25

C17

68uF

47pF

C16

2N3904

2N3904

6.8k

R18

1.5k

R20

6.8k

R22

R16

C24

0

5k

C25

1uF

R24

C21

C20

150uF

2N3904

M5

C19

150uF

10k

R26

10k

VIN1

OFF

R27

ON

10k

R28

10k

C15
1uF

5

VCC

N X 2 6 0 1

GND

4

PVCC1

BST1

HDRV1

SW1

OCP1

LDRV1

PGND1

Fb1

Comp1

PVCC2

BST2

HDRV2

SW2

OCP2

LDRV2

PGND2

Comp2

Fb2

NX2601

C1

23

24

25

26
27

22
21
29

28

18

17

16

15
14

19
20

12

13

1uF

R1

R6

1uF

C8

24.8k

R10
25k

C23

10.5k

R5

3k

C22

68pF

D1

C4

0.1uF

D2

C11

0.1uF

68pF

+5V

M1

M2

+5V

C5

4.7nF

C12

4.7nF

L2 1.5uH

M3

L4 1.5uH

M4

L1 1uH

C2

180uF

C9

180uF

C3

100uF

R3
10k

R4

20.8k

R8

10k

R9
10k

VIN1
+12V

VOUT1

C7
3 x (1500uF,19mohm)

+1.2V@15A

VOUT2

C14

2 x (1500uF,19mohm)

+1.6V/10A

Figure 21 - NX2601 application with electrolytic capacitors as output capacitors

Rev. 2.3
12/01/06

22

TYPICAL APPLICATIONS(cont')

10

R15

30k

1nF

1uFC24

100pF

R17

2.35k

R21

1.25k

R23

1.25k

R12
5k

R13

1.65k

C18

R19

1.25k

R11

11

10

9
8

7

3

1

2

6

30
31

REG FB

REG OUT
AUXVCC
LDO OUT

LDO FB

ENLDO

ENSW1

ENSW2

RT

VP
VREF

C15
1uF

5

VCC

N X 2 6 0 1

GND

4

VIN2

+3.3V

VOUT3

+2.5V/2A

OFF

ON

VIN1

R25

+5V

C17

2.2uF

R29

10k

C16
33pF

2N3904

C20

M5

10uF

C19

47uF

10k

2N3904

R26

10k

VIN1

OFF

R27

ON

10k

R28

10k

2N3904

1.5k

6.8k

6.8k

R20

R22

R18

R16

5k

R24

C21

2.5k

C25

1uF

PVCC1

BST1

HDRV1

SW1

OCP1

LDRV1

PGND1

Fb1

Comp1

PVCC2

BST2

HDRV2

SW2

OCP2

LDRV2

PGND2

Comp2

Fb2

NX2601

C1

23

24

25

26
27

22
21
29

28

18

17

16

15
14

19
20

12

13

+5V

1uF

D1

C4

0.1uF
M1

R1

10.5k

M2

C5

R5

5k

3.9nF

C22

100pF

C8

+5V

1uF

D2

C11

0.1uF

R6

3k

C12

R10
5k

3.9nF

C23

100pF

L2 0.68uH

M3

L4 2.2uH

M4

L1 1uH

C2

180uF

C9

39uF

440

C6

1.2nF

440
C6

1.2nF

VIN1

C3

100uF

+12V

VOUT1

C7

R3
11k

R4
22k

6 x 47uF

R2

+1.2V@10A

VOUT2

C14

11k

R9

R8

8.9k

2 x47uF

R7

+1.8V/5A

Figure 22 - NX2601 application with ceramic capacitors as output capacitors

Rev. 2.3
12/01/06

23

MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS

D

NX2601

TOP VIEW

D/2

D2

D2/2

E/2

L

E

A

SIDE VIEW

A1

e

2

1

N N-1

BTM VIEW

A3

R

E2/2

E2

Exposed Pad

B

SEATING

PLANE

32 PIN 5 x 5 SYMBOL

NAME

MIN NOM MAX

A 0.80 0.90 1.00
A1 0.00 0.02 0.05
A3 0.20REF

B 0.18 0.25 0.30

D 5.00BSC

D2 3.30 3.45 3.55

E 5.00BSC
E2 3.30 3.45 3.55

e 0.50BSC
L 0.30 0.40 0.50

R 0.09 --- ---

ND 6

NE 6

NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

Rev. 2.3
12/01/06

24

MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION

NX2601

Rev. 2.3
12/01/06

NOTE:

1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.

2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.

25