Page 1
NX2423
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH
INTEGRATED FET DRIVER, DIFFERENTIAL CURRENT SENSE
& 5V BIAS REGULATOR
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2423 is a two-phase PWM controller with integrated FET driver designed for low voltage high current
application. The two phase synchronous buck converter
offers ripple cancelation for both input and output. The
NX2423 uses differential remote sensing using either current sense resistor or inductor DCR sensing to achieve
accurate current matching between the two channels.
Differential sensing eliminates the error caused by PCB
board trace resistance that otherwise presents when using a single ended voltage sensing.
In addition the NX2423 offers high drive current capability especially for keeping the synchronous MOSFET off
during SW node transition, can provide regulated 5V to
IC biasing and drivers via 5V bias regulator, allows the
slave channel on and off via EN2_B pin while the main
channel is working. Other features: PGOOD output, programmable switching frequency and hiccup current limiting circuitry.
2N3904
R10
VCCDRV
HDRV1
C27
PVCC
5VCC
REFIN
AGND
CSCOMP
RT
IOUT/IMAX
VCOMP
FB
EN2_B
PGND(PAD)
LDRV1
N X 2 4 2 3
HDRV2
LDRV2
INREFOUT/POK
Figure1 - Typical application of NX2423
2N3904
R13
5V
R14
C31
R16
R17
R19
R20
VOUT
C30
R15
R18
R11
C29
C28
C26
C25
Device Temperature Package Frequency Pb-Free
NX2423CMTR 0 to 70oC MLPQ 4x4 - 24L 50kHz to 1MHz Yes
FEATURES
n Differential inductor DCR sensing eliminates the
problem with layout parasitic
n 5V bias regulator available
n Low Impedance On-board Drivers
n Hiccup current limit and IOUT indication
n Power Good for power sequencing
n EN2_B pin allows the slave channel on and off while
the master channel is working
n Programmable frequency
n Prebias start up
n OVP without negative spike at output
n Selectable between internal and external reference
n Internal Schottky diode from PVCC to BST
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic card High Current Vcore Supply
n High Current on board DC to DC converter
applications
TYPICAL APPLICATION
12V BUS
VOUT
BST1
SW1
CS+1
CS-1
BST2
SW2
CS+2
CS-2
C24
C11
C12
C19
R24
C10
Q1
Q2
Q3
Q4
Ref for external circuitry
C17
R29
R27
L1
C15
C18
L2
C22
C13
R28
R26
C20
C14
C21
ORDERING INFORMATION
Rev. 2.1
12/01/08
1
Page 2
NX2423
CW
θ≈30.5/
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply Voltage(Vcc)
REFIN=5V, EN2_B=GND,
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC To 150oC
Operating Junction Temperature Range ............... -40oC To 125oC
Lead temperature(Soldering 5s) ........................... 260oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
24 LEAD PLASTIC MLPQ
o
HDRV1
BST1
5VCC
AGND
EN2_B
CS+1
SW1
LDRV1
23
24
1
2
3
4
5
6
7
CS-1
PGND(PAD)
8
9
CS-2
PVCC
2122
10 11
CS+2
LDRV2
VCCDRV
20
19
12
RT
IOUT/IMAX
SW2
18
17
16
15
14
13
VCOMP
HDRV2
BST2
INREFOUT/POK
REFIN
CSCOMP
FB
JA
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over 5Vcc = 5V, PVcc= 5V, V
BST-VSW
and TA = 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and
case temperatures equal to the ambient temperature.
5V
,PVCC Voltage Range V
CC
CC
4.5 5 5.5 V
=5V, EN2_B=GND,
5VCC Supply Current (static)
PVCC Supply Current
(Dynamic)
V
Voltage Range V
BST
V
Supply Current
BST
((Dynamic))
Rev. 2.1
12/01/08
ICC (Static)
ICC
(Dynamic)
to V
BST
V
SW
BST
(Dynamic)
REFIN=GND, EN2_B=5V - 6.7
REFIN=5V, EN2_B=GND,
Freq=200Khz per phase
C
=2200PF
LOAD
4.4 mA
4.5 5 5.5 V
Freq=200Khz per phase
C
=2200PF
LOAD
mA
mA4.5
2
Page 3
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Under Voltage, Vcc & EN2_B
VCC-Hysteresis
VCC_Hyst
V
EN2_B
Rising
Reference Voltage
Oscillator (Rt)
Amplifiers(CSCOMP)
Output Current Source
5
mA
SS (Internal )
POK/INFEROUT
Ldrv going Low to Hdrv going
NX2423
VCC-Threshold VCC_UVLO VCC Rising
4.1 V
0.4 V
EN2_B Threshold
0.82 V
EN2_B Hysteresis 80 mV
Ref Voltage V
REF
4.5V<5Vcc<5.5V
0.6
V
Ref Voltage line regulation 0.2 %
Frequency for each phase Fs Rt=100kohm 400 KHz
Ramp-Amplitude Voltage V
RAMP
1.02 V
Ramp Peak 2.2 V
Ramp Valley 1.18 V
Max Duty Cycle 200Khz/Phase 97 %
Min Duty Cycle 0 %
Transconductance
Open Loop Gain 50 65 dB
Transconductance 1600 umoh
Voltage Mode Error
Open Loop Gain 50 dB
Input Offset Voltage Vio_v 0 mV
Output Current Sink 5 mA
Output HI Voltage Vcc-1.5 V
Output LOW Voltage 0.5 V
Soft Start time Tss 400Khz/Phase 2.5 mS
Threshold VFB Rising 73 %V
Hysteresis 5 %
POK Voltage I
=5mA(sourcing) 1.191 1.215 1.24 V
OUT
High Side Driver
(CL=4700pF)
Output Impedance , Sourcing
R
source
(Hdrv)
I=200mA
1
ohm
Current
Output Impedance , Sinking
R
sink
(Hdrv)
0.7 I=200mA
ohm
Current
Rise Time THdrv(Rise) 10% to 90% 19 ns
Fall Time THdrv(Fall) 90% to 10% 18.5 ns
Deadband Time Tdead(L to
H)
High, 10%-10%
40 ns
Low Side Driver
(CL=10000pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 1 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 0.5 ohm
sink
Current
Rev. 2.1
12/01/08
P
3
Page 4
NX2423
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Amplifier(CS+, CS-)
OVP Threshold
FB UVLO Threshold
FB UVLO Threshold
percent of Vp
70
%
REFIN VOLTAGE
5V AUX REG
Internal Schottky Diode
Rise Time TLdrv(Rise) 10% to 90% 34 ns
Fall Time TLdrv(Fall) 90% to 10% 18 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
High, 10% to 10%
Low
Current Sense
Input Offset Voltage -2 2 mV
Voltage Gain 29.7 30 30.3 V/V
OVP Threshold percent of Vp 130 %
REFIN Voltage Range 0.4 2.5 V
Disable Voltage Threshold 0.3 0.35 0.4 V
Threshold Enable Internal
Reference
75 %VCC
10 ns
14
nsPropagation Delay Tdealy(H) IN going High to Ldrv going
Regout Output Voltage High VIN=12V, PVCC=3V 11 V
Regout Output Voltage Low VIN=12V, PVCC=5.8V,
VCCDRV connected to 12V
by 1k resistor
Forward voltage drop forward current=10mA 600 mV
2
V
Rev. 2.1
12/01/08
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Page 5
PIN DESCRIPTIONS
SYMBOL PIN DESCRIPTION
HDRV1
High side gate driver for Channel 1.
NX2423
BST1
5VCC
AGND
EN2_B
CS+1
CS-1
CS-2
CS+2
IOUT/IMAX
Bootstrap supply for Channel 1.
IC’s supply voltage. This pin biases the internal logic circuits. A minimum 1uF
ceramic capacitor is recommended to connect from this pin to ground plane.
Controller analog ground pin.
This pin is used to startup or shutdown the channel2 only while 5VCC and REFIN is
ready. For two phase opeartion, EN2_B is preferred to be tied to GND. For one
phase opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is
not recommended to change EN2_B voltage.
Positive input of the channel 1 differential current sense amplifiers. It is connected
directly to the RC junction of the respective phase’s output inductor.
Negative input of the channel 1 differential current sense amplifiers. It is connected directly to the negative side of the respective phase’s output inductor.
Negative input of the channel 2 differential current sense amplifiers. It is connected directly to the negative side of the respective phase’s output inductor.
Positive input of the channel 2 differential current sense amplifiers. It is connected
directly to the RC junction of the respective phase’s output inductor.
This pin indicates average output current level and sets OCP threshold using a
resistor from this pin to ground. A no more than 1nF ceramic capacitor is recommended to connect this pin to ground plane to filter the noise on this pin.
Rev. 2.1
12/01/08
RT
VCOMP
FB
CSCOMP
REFIN
INREFOUT/
POK
This pin programs the internal oscillator frequency using a resistor from this pin to
ground.
This is the output pin of the error amplifier.
This pin is the error amplifier inverting input. It is connected to the output voltage via
a voltage divider.
The output of the transconductance op amp for current balance circuit. An
external RC is connected from this pin to GND to stabilize the current loop.
External reference input. If pull-up to >4.5V, internal reference is used. If driven by
an external voltage ranged from 0.4V to 2.5V, external reference is used with slew
rate following SS rate. If REFIN is below 0.4V, device is disabled.
This pin has dual functions. When FB pin is below 75% of internal 0.6V reference,
this pin is held low. When FB reaches above this threshold, this pin is tied to an
internal 1.25V reference, allowing it to be used as a reference for any external op
amp circuitry as well as an indicator of power OK. This pin can not be connected
directly to an output capacitor. An RC network is needed which also provides a slow
ramp up of the reference for the external op amp.
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Page 6
SYMBOL PIN DESCRIPTION
BST2
Bootstrap supply for Channel 2.
NX2423
HDRV2
SW2
LDRV2
PVCC
LDRV1
SW1
PGND
VCCDRV
High side gate driver for Channel 2.
Switch node for Channel2.
Low side gate driver for Channel 2.
This pin provide the supply voltage for the lower MOSFET drivers. This pin provide
the supply voltage for the lower MOSFET drivers. A high frequency ceramic 1uF
must be placed close to this pin and tied to PGND to provide peak current
needed for low side MOSFETs.
Low side gate driver for Channel 1.
Switch node for Channel 1.
This is the ground connection for the power stage of the controller.
The output of the 5V regulator controller that drives a low current low cost external BIPOLAR transistor or an external MOSFET to regulate the voltage at Vcc pin
derived from BUS voltage. A resistor with value from 1k to 10k is used to connect
VCCDRV and VBUS. Pulling down VCCDRV is used to disable chip in NX2423
application .
Rev. 2.1
12/01/08
6
Page 7
BLOCK DIAGRAM
+12V
VCCDRV
OFF
ON
+5V
+5V
ON
OFF
DAC
5VCC
EN2_B
REFIN
VOUT
FB
VCOMP
Rt
INREFOUT/POK
AGND
0.82/0.74
0.35
/0.3V
3.6
/3.3V
Vp*130%
FB
Vp*75%
SS_finished
Bias
generator
0.6V
Digital
start
1.25V
Vp*70%
1.25V
0.6V
1.6V
1.25V
ENBUS_2
SS_finish
Dis_EA
ramp1
Two phase
OSC
ramp2
FILTER
SS_FINISHED
Hiccup
FILTER
Hiccup
UVLO
Vp
Set1
set2
OVP
UVLO
Hiccup
Logic
start
R
Q
S
K=30
V1.25
CS01
CS02
V1.25
Slave channel control
Σ
6 Cycles
filter
OVP
ENBUS_2
KR
KR
KR
V1.25
÷
2
FET
driver
R
R
PWM control
logic
and driver
KR
R
R
gm=0.04A/V
Σ
1.25V
PVCC
BST1
DrvH1
SW1
DrvL1
PGND
BST2
DrvH2
SW2
DrvL2
CS+1
CS-1
CS+2
CS-2
CScomp(SS/EN)
IOUT/IMAX
NX2423
+5V
+12V
VOUT
+1.2V/50A
Rev. 2.1
12/01/08
FB
Figure 2 - Block diagram of NX2423
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Page 8
NX2423
RIPPLEINS
1
IVF
12V400kHz
L=0.54uH
=3.97A
ESR=3.022m
==Ω
ERIPPLE
7m3.97A
12mV
SRIPPLE
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Operation frequency for each channel
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2423.
VIN = 12V
VOUT=1.2V
IOUT=50A
IOUT_max=60A
DVRIPPLE <=12mV
DVDROOP<=120mV @30A step
FS=400kHz
Phase number N=2
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
L=
∆×
where k is between 0.2 to 0.4.
Select k=0.2, then
L=
INOUT OUT
OUT
∆
I=k
RIPPLE
12V-1.2V1.2V1
OUT
0.2
××
I
OUTPUT
N
50A
×
2
××
...(1)
OUT
Choose inductor from Vishay IHLP_5050FD-01
with L=0.68uH DCR=1.4mΩ.
Current Ripple is recalculated as
V-VV
I=
∆××
RIPPLE
INOUT OUT
LVF
OUTINS
12V-1.2V1.2V1
0.68uH12V400kHz
××=
1
...(2)
Output Capacitor Selection
Output capacitor value is basically decided by the
output voltage ripple, capacitor RMS current rating and
load transient.
Based on Voltage Ripple
For electrolytic, POSCAP bulk capacitor, the ESR
(equivalent series resistance) and inductor current typically determines the output voltage ripple.
V
∆
tiple capacitors in parallel are better than a big capacitor. For example, for 12mV output ripple, SANYO OSCON capacitors 2R5SEPC1000MX(1000uF 7mΩ) are
chosen.
mined by the number of capacitor instead of ESR
that the output voltage droop during the transient can
not meet the spec although ripple is small.
desire
If low ESR is required, for most applications, mul-
N
=
Number of Capacitor is calculated as
N
=
N =2.3
For ceramic capacitor, the current ripple is deter-
C
OUT
Typically, the calculated capacitance is so small
RIPPLE
I3.97A
∆
RIPPLE
ESRI
∆
Ω×
=
8FV
××∆
×∆
V
RIPPLE
I
∆
RIPPLE
12mV
...(3)
...(4)
...(5)
Rev. 2.1
12/01/08
8
Page 9
NX2423
DROOPTRAN
2
∆=×∆+×τ
OUTEFFcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEEFFcrit
ESRCifLL
0.28H
=µ
7m1000F1.5us
2
1.78×∆=+×τ
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
V<V∆∆ @ step load DI
STEP
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, overshoot caused by
DISTEP transient load which is from high load to low load,
can be estimated as the following equation,if assuming
the bandwidth of system is high enough.
V
VESRI
overshootstep
OUT
2LC
××
OUT
...(6)
where τ is the a function of capacitor, etc.
0ifLL
LI
EFFstep
V
×∆
OUT
τ=
≤
EFFcrit
−×≥
...(7)
where
L
L0.34uH
===
EFF
ESRCVESRCV
L
==
crit
0.68uH
OUT
N2
××××
II
∆∆
stepstep
...(8)
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and capacitance is high and
≤ is true. In that case, the
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
EFFstep
V
×∆
OUT
τ=
≤
EFFcrit
−×≥
...(10)
For example, assume voltage droop during transient
is 120mV for 30A load step.
If the OS-CON capacitors (1000uF, 7mΩ ) is used,
the critical inductance is given as
ESRCV
××
L
crit
7m1000F1.2V
Ω×µ×
The effective inductor value is 0.34uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also
capacitance.
number of capacitors is
τ=−×
=−Ω×µ=
N
=+
20.34H1000F120mV
×µ×µ×
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
EEOUT
==
I
∆
step
30A
LI
×∆
EFFstep
V
OUT
0.34H30A
µ×
ESRC
EE
1.2V
ESRI
Estep
V2LCV
∆×××∆
tranEFFEtran
7m30A
Ω×
V
OUT
120mV
1.2V
×
(1.5us)
2
Rev. 2.1
12/01/08
9
Page 10
NX2423
Gain= ... (11)
F= ... (12)
F ... (13)
Control Loop Compensator Design
NX2423 can control and drive two channel synchro-
nous bucks with 180
o
phase shift between each other.
One of two channels is called master, the other is called
slave. They are connected together by sharing the same
output capacitors. Voltage loop is designed to regulate
output voltage. In order to achieve the current balance in
these two synchronous buck converters, current loop
compensation network is employed to to make sure the
currents in slave is following the master.
Voltage Loop Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II
compensator can be used to compensate the system,
because the zero caused by output capacitor ESR is
lower than crossover frequency. Otherwise type III compensator should be chosen.
R
3
R
2
1
z
2RC
×π××
31
≈
p
1
2RC
×π××
32
C2
Vout
R3
C1
R2
Fb
R1
Vref
Figure 3 - Type II compensator
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
Ve
A. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 3. R3 and C1
introduce a zero to cancel the double pole effect. C2
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero location and constant gain.
Rev. 2.1
12/01/08
F
F
LC
Z
ESRFO
Gain
F
P
F
Figure 4 - Bode plot of Type II compensator
For this type of compensator, FO has to satisfy
compensator
FLC<F
<< FO and FO <=1/10~1/5F
ESR
s.
Here a type II compensator is designed for the case
which has six electrolytic capacitors(1800uF, 13mΩ) and
10
Page 11
NX2423
20.75uH10800uF
213m1800uF
R=10k
==Ω
=10k
=27.3k
××Ω
227.4k0.751.768kHz
p
F
27.4k400kHz
F ...(14)
F ...(15)
F ...(16)
F ...(17)
two 1.5uH inductors.
1.Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
EFFOUT
1
×π××
1.768kHz
=
1
OUT
1
F
=
ESR
2ESRC
×π××
=
×π×Ω×
6.801kHz
=
LC
B. Type III compensator design
Sanyo OSCON and POSCAP, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator.
used as output capacitors. The system is compensated
with type III compensator. The following figures and equations show how to realize the this type III compensator
with electrolytic capacitors.
2.Set R2 equal to10kΩ and calculate R1.
×
2REF
1
V-V1.2V-0.6V
OUT REF
10k0.6V
Ω×
RV
3. Set crossover frequency FO=15kHz.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCOEFF
32
VESR
in
1V215kHz0.75uH
12V2.16m
×π××
××
×π××
Ω
Ω
the compensator.
Choose R3 =27.4kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=4.4nF
For low ESR output capacitors, typically such as
In design example, six electrolytic capacitors are
1
×π××
2RC
42
1
×π×+×
2(RR)C
233
1
×π××
2RC
33
1
×
CC
4
CC
12
+
12
×π××
2R
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
C2
Fb
Zf
C1
R4
Zin
Vout
R3
R2
C3
Ve
R1
Vref
Choose C1=4.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
RF
π××
3s
1
π×Ω×
=30pF
Choose C2=33pF.
Rev. 2.1
12/01/08
Figure 5 - Type III compensator
11
Page 12
power stage
[
]
42233
(1sRC)1s(RR)C
20.34uH2000uF
23.5m2000uF
R=10k
==Ω
=(-)
210k6.1kHz22.7kHz
=1.9nF
222.7kHz1.8nF
1V240kHz0.34uH10k3.92k
12V3.5m10k3.92k
×π××Ω×Ω
ΩΩ+Ω
20.756.1kHz5.62k
×π×××Ω
25.62k200kHz
Gain(db)
loop gain
LC
F
40dB/decade
F
ESR
20dB/decade
×
2REF
1
V-V1.2V-0.6V
OUT REF
10k0.6V
RV
Choose R1=10kΩ.
3. Calculate C3 by setting FZ2 = F
C=(-)
3
111
2RFF
×π×
×π×Ω
×
2z2p1
111
×
Ω×
NX2423
and Fp1 =F
LC
ESR
.
compensator
P1
Z2
Z1
F
F
F
F
O
F
P2
Figure 6 - Bode plot of Type III compensator
The transfer function of type III compensator
is given by:
V
e
=×
VsR(CC)
OUT 221
1
×+
+××++×
CC
×
(1sR)1sRC
+××+×
21
433
CC
21
+
( )
Use the same power stage requirement as demo
board. The crossover frequency has to be selected as
FLC<F
and ESR zero F
, and usually FO<=1/10~1/5FS.
ESR<FO
1.Calculate the location of LC double pole F
.
ESR
F
=
LC
2LC
=
1
×π××
EFFOUT
1
LC
×π××
6.1kHz
=
F
ESR
22.7kHz
=
2ESRC
=
=
1
×π××
OUT
1
×π×Ω×
2.Set R2 equal to10kΩ.
Choose C3=1.8nF.
5. Calculate R3 by equation (13).
R
=
3
=
3.89k
=Ω
1
2FC
×π××
P13
1
×π××
Choose R3=3.92kΩ.
6. Calculate R4 by choosing FO=40kHz.
V2FLRR
R=
4
VESRRR
=
=5.73k
×π×××
OSCOEFF23
××
in23
+
××
Ω
Choose R4=5.62kΩ.
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
6.2nF
=
Choose C2=6.8nF.
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
141pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=150pF.
Rev. 2.1
12/01/08
12
Page 13
Current Loop Compensator Design
NX2423
Power stage
Master
channel
Ramp for
slave channel
1
Compensation
D(s)
Current Sensing
Amplifier Gain
Vosc
d
s*L+Req
s*L+DCR
Rs*Cs*s+1
Inductor Current
sense
Figure 7 - Current loop control diagram
V
IN
Vbias
V
IN
PWM control
logic
and driver
Vbias
Vin
iL
master channel
L
Rs
Rs
Slave channel 1
L
Rs
Rs
DCR
Cs
DCR
Cs
V
OUT
Rev. 2.1
12/01/08
CSCOMP
Rcc
Slave channel control
C2
Slave channel control
Slave channel
Figure 8 - Function diagram of current loop
C1
13
Page 14
NX2423
L
DCR
S_ILL
VDCRi
=×
1
CF
=µ
S
DCRC
486
==Ω
S
DCRC
01101
004
.(.)
Inductor Current Sensing
V
IN
Control &
Driver
Current
Sensing
Rs
L
Rs
i
L
DCR
V
OUT
Cs
V
S_IL
Amplifier
Figure 9 - Inductor current sensing using RC network.
The inductor current can be sensed through a RC
network as shown above. The advantage of the RC network is the lossless comparing with a resistor in series
with output inductor.
The selection of the resistor sensing network is
chosen by the following equation:
RC
×=
SS
...(18)
racy during the transient if droop function is required.
The illustration is shown in the following figure.
Overshoot caused
by inductor
V
S_IL
----Voltage accross
nonlinearity
the sensing
capacitor Cs
iL--- inductor current
Output voltage
with droop function
Droop misbehavoir
caused by
overshoot of V
S_IL
Figure 10 - Droop accuracy affected by the nonlinearity
of inductor.
If the above equation is satisfied, the voltage across
the sensing capacitor Cs will be equal to the inductor
current times DCR of inductor for all frequency domain.
If the sensing capacitor is chosen
S
CS must be X7R or COG ceramic capacitor.
The sensing resistor is calculated as
R
S
L
=
×
For example, for 0.68uH inductor with 1.4mΩ
DCR, we have
068
.H
R
S
µ
141
.mF
Ω×µ
In most of cases, the selection of sensing resistor based on the above equation will be sufficient. However, for some inductor such as toroid coiled inductor
with micrometal, even the product of sensing resistor
and capacitor is perfectly match with L/DCR, the voltage
across the capacitor still has overshoot due to the
nonlinearity of inductor. This will affect the droop accu-
In this case, the sensing resistor has to be chosen
R
S
L
≥
×
to compensate the overshoot. This selection only affects the small signal mode of current loop. For DC accuracy, there is no effect since the DC voltage across
the sensing capacitor will equal to the DCR times inductor current at DC load no matter what Rs is. In this example, Rs=620Ω.
RS value is preferred to be less than 400Ω in
NX2423's application, therefore we need to reiterate the
calculation, choose CS 2.2uF instead. RS value is finally
chosen as 301Ω .
Powe dissipation of Rs resistor is calculated as
followed:
(VV)V
−
P(R)D(D)
DS
=×+×−
=
INOUTOUT
=×+×−
121212
(V.V)(.V)
−
301301
.W
22
RR
SS
22
1
ΩΩ
The power rating of Rs should be over 0.04W.
Rev. 2.1
12/01/08
14
Page 15
NX2423
F.kHz
12
RCC
oosc
gVKDCR
229
K.
442
==Ω
430
=Ω
214
CnF
×π×
dson_con
dson_syn
R.m
=Ω
Current Loop Compensation
Slave channel
power stage
Current loop
compensation
Loop gain
for slave
channel
Fp1
Fzc Fpc
-20 dB
-20dB
0 DB
-40dB
Fo
Figure 11 - Bode plot of current loop
The diagram and bode plot for current loop of
NX2423 is shown in above figure. The current signal
through inductor sensing is amplified by current sensing
differential amplifier. The amplified slave current signal
is compared with the amplified inductor current from
master channel (channel 1 for NX2423) through a
transconductance amplifier, the difference between channel current will change the output of transconductance
amplifier, which will compare with a internal ramp signal
and changes the duty cycle of slave channel buck converter. If the inductor are perfectly matched and the PWM
controller has no offset, the DC current in slave channel
will equal to the DC current of master channel (channel
1) due to the gain of current loop.
From the bode plot, the power stage has one pole
located at
R
FL=
1
P
eq
2
where Req is the equivalent resistor and it is given by
VV
RDCRRR
≈+×+×−
eqdson_condson_syn
R
is the Rdson of control FET and
OUTOUT
VV
ININ
1
R
is
the Rdson of synchronous FET. For this example,
74
eq
The pole is located as
R
eq
===
1
P
22068
L.H
×π××π×µ
74
.m
Ω
17
The current compensation transfer function is
given as
1
sRCg
D(s)
=×
m
sCC
×+
( )
12
1
+××
cc
s
+×
1
cc
××
CC
+
12
It has one zero and one pole. The ideal is to
choose resistor Rcc to achieve desired loop gain such
as 50kHz. Rcc can be calculated as
2
FLV
R
×π×××
=
cc
mINC
×××
...(19)
where
60
k
⋅Ω
≈=
C
2
kR
Ω+
S
60kΩ and 2kΩ is the internal resistance for the current
sensing amplifier.
For fast response, we can set the current loop
cross-over frequency one and half times of voltage loop
cross-over frequency. Since the voltage loop cross-over
frequency is typically selected as 1/10 of switching frequency, we choose FO=50kHz.
2500681
R
cc
×π××µ×
161222914
.mA/VV..m
kHz.HV
×××Ω
Select
R
cc
.
The selection of capacitor C1 is such that the zero
of compensation will cancel the pole of power stage,
therefore,
L.H
===
1
RR.m
×Ω×Ω
eqcc
068
µ
74430
Typically, the capacitor C1 is so big that the current loop may start slowly during the start up. Therefore, smaller capacitor can be selected. However, the
selected capacitor can not reduce too much to cause
phase droop.
Select C1=220nF.
The capacitor C2 is an option and it is used to
filter out the switching noise. C2 can be calculated as
Rev. 2.1
12/01/08
15
Page 16
NX2423
185
C.nF
40000000
Frequency(kHz)
75
I.A
0
D
(
)
Iout
OCP
1.25V21
0.04mA/V60kDCRI
RFkHz
π××π×Ω×
ccS
430400
11
===
2
Select C2=2.2nF.
Frequency Selection
The frequency can be set by external Rt resistor.
The relationship between frequency per phase and RT
pin around 400kHz is shown as follows.
RF≈
T
1200
1000
800
600
400
200
0
0 50 100 150 200 250 300
Figure 12 - Frequency vs Rt chart
...(20)
S
Frequency(kHz) vs Rt(kohm)
Rt(kohm)
0.2*Iout=0.2*50A=10A.
A combination of ceramic and electrolytic(SANYO
WG or WF series) or OSCON type capacitors can
achieve both ripple current capability together with having enough capacitance such that input voltage will not
sag too much. In this application, one OSCON
SVPC180M(180uF, 16V, 2.8A) and three 10uF X5R ceramic capacitors are selected.
A 1uH input inductor is recommended to slow down
the input current transient. Suppose power stage efficiency is 0.8, then input current can estimated by
IV
INPUT
V.V
η××
IN
×
OUTOUT
===
6012
A.V
×
0812
In this application, Coilcraft DO3316P_102HC with
RMS rating 10A is chosen.
0.5
0.4
Singlephase
RMS
0.3
INI
0.2
0.1
Three
Two
phase
phase
Input Filter Selection
The selection criteria of input capacitor are voltage
rating and the RMS current rating. For conservative consideration, the capacitor voltage rating should be 1.5
times higher than the maximum input voltage. The RMS
current rating of the input capacitor for multi-phase converter can be estimated from the above Figure 13.
First, determine the duty cycle of the converter (VO/
VIN). The ratio of input RMS current over output current
can be obtained. Then the total input RMS current can
be calculated. From this figure, it is obvious that a multiphase converter can have a much smaller input RMS
current, which results in a lower amount of input capacitors that are required.
For example, Vin=12V, Vout=1.2V. The duty cycle
is D=Vout/Vin=1.2/12=10%. From the figure, for two
phase, the normlized RMS current is
Rev. 2.1
12/01/08
0
0.1 0.2 0.3 0.4 0.5
Figure 13 - Normalized input RMS current vs. duty cycle
Over Current/Short Circuit Protection
The converter will go into hiccup mode if the
output current reaches a programmed limit I
determined by the resistor value R
2kR
Ω+
R
=×××
OCP
Where I
is the desired over current protection
ocp
S
Ω
at pin IOUT/IMAX.
ocp
...(21)
level, RS is the current sensing matching resistor when
using DCR sensing method.
OCP
16
Page 17
NX2423
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
SW
T
S
dt1024T
Over Voltage Protection
Over voltage protection is achieved by sensing the
output voltage through resistor divider. The sensed voltage on FB pin is compared with 130%*V
to generate
REF
the OVP signal.
Power MOSFETs Selection
The NX2423 requires two N-Channel power
MOSFETs for each channels. The selection of
MOSFETs is based on maximum drain source voltage,
gate source voltage, maximum current rating, MOSFET
on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to
the overall converter efficiency. In this design example,
eight NTD60N02 are used. They have the following parameters: VDS=25V, ID =62A,R
=12mΩ,Q
DSON
GATE
=9nC.
There are three factors causing the MOSFET power
loss:conduction loss, switching loss and gate driver loss.
Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
LGS
is
the low side gate source voltage. This power dissipation
should not exceed maximum power dissipation of the
driver device.
Conduction loss is simply defined as:
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
Where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency and should be selected for the worst case.
Conduction loss should not exceed package rating or
overall system thermal budget.
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
loss can be approximated.
2
×××
2
+
1
2
K
...(23)
...(24)
is the sum of TR and TF which can be found in
mosfet datasheet, IOUT is output current, and FS is switching frequency. Swithing loss PSW is frequency depen-
dent.
Soft Start and Enable Signal Operation
The NX2423's master channel will start operation
after 5VCC and REFIN have reached their threshold
voltages. Pulling down VCCDRV will cause 5VCC drop
below to its threshold, then shuts down NX2423.
The slave channel will start operation only when
EN2_B is less than 0.8V, 5VCC and REFIN have reached
their respective thresholds. For two phase opeartion,
EN2_B is preferred to be tied to GND. For one phase
opeartion, EN2_B is preferred to be tied to 5VCC. During the operation, it is not recommended to change EN2_B
voltage.
Once the converter starts, there is a soft start sequence of 1024 steps between 0 and V
. The ramp
REF
rate is determined by the switching frequency.
dVV
OO
=
...(25)
×
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
Rev. 2.1
12/01/08
17
Page 18
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touching
the drain pin of the upper MOSFET, a plane connection
is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
12. Inductor current sense line should be connected directly to the inductor solder pad.
NX2423
Rev. 2.1
12/01/08
18
Page 19
MLPQ 24 PIN 4 x 4 PACKAGE OUTLINE DIMENSIONS
NX2423
Rev. 2.1
12/01/08
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
19
Page 20
MLPQ 24 PIN 4 x 4 TAPE AND REEL INFORMATION
NX2423
Rev. 2.1
12/01/08
NOTE:
1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.
2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
20
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