Datasheet nx2415 Datasheets

Evaluation board available.

NEXSEM

NX2415

TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH

INTEGRATED FET DRIVER AND DIFFERENTIAL CURRENT SENSE

PRELIMINARY DATA SHEET

Pb Free Product

DESCRIPTION

The NX2415 is a two-phase PWM controller with inte­grated FET driver designed for low voltage high current
application. The two phase synchronous buck converter
offers ripple cancelation for both input and output. The
NX2415 uses differential remote sensing using either
current sense resistor or inductor DCR sensing to achieve
accurate current matching between the two channels.
Differential sensing eliminates the error caused by PCB
board trace resistance that is otherwise is present when
using a single ended voltage sensing. In addition the
NX2415 offers high drive current capability especially for
keeping the synchronous MOSFET off during SW node
transition, accurate programmable droop allowing to re­duce number of output capacitors, accurate enable cir­cuit provides programmable start up point for Bus volt­age, PGOOD output, programmable switching frequency
and hiccup current limiting circuitry.

10

VOUT

1.8nF

2N3906

+5V

+12V

+5V

1k

10k

3.92k

20k

10k

430

20k

6.49k

1.65k

2.2nF

5.62k

10nF

10k

op

45.3k
10k

220nF

150pF

10nF

1nF

100k180k

31

VCC

1uF

30

EN

29

ENBUS

7

DROOP

2

RT

28

PGOOD

11

CSCOMP

3

PGSEN

1nF

5

FB

6.8nF

6

VCOMP

4

VP

8

OCP

1

VREF

14

IOUT

AGND

Figure1 - Typical application of NX2415

PVCC1

BST1

HDRV1

SW1

LDRV1

PGND1

CS+1
CS-1

PVCC2

N X 2 4 1 5

BST2

HDRV2

SW2

LDRV2

PGND2

CS+2

CS-2

32

n Differential inductor DCR sensing eliminates the
problem with layout parasitic

n External programmable voltage droop
n Low Impedance On-board Drivers
n Hiccup current limit
n Power Good for power sequencing
n Enable Signal allows external shutdown as well as

programming the BUS voltage start up threshold

n Programmable frequency
n Prebias start up
n Over voltage protection without negative spike at

output
n Pb-free and RoHS compliant

APPLICATIONS

n Graphic card High Current Vcore Supply
n High Current +40A on board DC to DC converter

applications

TYPICAL APPLICATION

23

24

25

26

22

21

9
10

18

17

16

15

19

20

12
13

1uF

1uF

0.22uF

2.15

0.22uF

2.15

+5V

+5V

1uH

2 x 10uF

180uF

M1

0.68uH

M2

620

1uF

620

10uF

M3

0.68uH

M4

620

1uF

620

FEATURES

VIN1
+12V

100uF

VOUT
+1.2V/50A

2 x (1000uF,7mohm ESR)

Rev.4.8
05/06/08

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX2415CMTR 0 to 70oC MLPQ-32L 200kHz to 1MHz Yes

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1

NEXSEM

PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

Supply Voltage(Vcc)

EN&ENBUS HIGH,

θ≈35/

CW

NX2415

ABSOLUTE MAXIMUM RATINGS

Vcc to PGND & BST to SW voltage .................... -0.3V to 6.5V

BST to PGND Voltage ...................................... -0.3V to 35V

SW to PGND .................................................... -2V to 35V

All other pins .................................................... -0.3V to 6.5V

Storage Temperature Range ............................... -65oC To 150oC

Operating Junction Temperature Range ............... -40oC To 125oC

Lead temperature(Soldering 5s) ........................... 260oC

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

32-LEAD PLASTIC MLPQ 5 x 5

ENBUS

PGOOD

EN

VCC

2930

31

28

NX2415

101112 13 14

CS-1

CS+2

CSCOMP

CS-2

HDRV1

NC

SW1

25

27

26

BST1

24

PVCC1

23

LDRV1

IOUT

22
21

PGnd1

PGnd2

20
19

LDRV2

PVCC2

18
17

BST2

16

15

SW2

HDRV2

o

JA

VREF

RT

PGSEN

VP

COMP

DROOP

OCP

AGND

32
1
2
3
4

FB

5
6
7
8

9

CS+1

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc = 5V, V

BST-VSW

Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.

V

,PVCC Voltage Range V

CC

VCC Supply Current (static)

CC

ICC (Static)

EN=LOW - 6.6

=5V, EN=HIGH, and TA = 0 to 70oC.

4.5 5 5.5 V
mA

PVCC Supply Current
(Dynamic)

V

BST

V

BST

((Dynamic))

Rev.4.8
05/06/08

Voltage Range V
Supply Current

ICC

(Dynamic)

to V

BST

V

SW

BST

(Dynamic)

EN&ENBUS HIGH,
Freq=200Khz per phase
C

=2200PF

LOAD

Freq=200Khz per phase
C

=2200PF

LOAD

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4 mA

4.5 5 5.5 V

4 mA

2

NEXSEM

PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

Under Voltage, Vcc ,

Enable(EN) & ENBUS

VCC-Hysteresis

VCC_Hyst

Vcc Rising

V

BUS

Rising

Reference Voltage

Oscillator (Rt)

Amplifiers(CSCOMP)

SS (Internal )

Power Good(Pgood)

H)

Ldrv going Low to Hdrv going

High, 10%-10%

NX2415

VCC-Threshold VCC_UVLO

EN Threshold
EN Hysteresis 0.1 V
ENBUS Threshold
ENBUS Hysteresis 0.16 V

Ref Voltage V
Ref Voltage line regulation 1 %

Frequency for each phase Fs Rt=45kohm 400 KHz
Ramp-Amplitude Voltage V

Ramp Peak 2.5 V
Ramp Valley 1.5 V
Max Duty Cycle 200Khz/Phase 95 %
Min Duty Cycle 0 %

Transconductance

Open Loop Gain 50 65 dB
Transconductance 1600 umoh

Voltage Mode Error
Amplifier

Open Loop Gain 50 dB
Input Offset Voltage Vio_v 0 mV
Output Current Source 5 mA

Output Current Sink 5 mA
Output HI Voltage Vcc-1.5 V

Output LOW Voltage 0.5 V

REF

RAMP

VCC Rising

4.5V<Vcc<5.5V

4

0.2 V

0.6 V

1.6 V

1 V

0.8

V

V

Soft Start time Tss 200Khz/Phase 20 mS

Threshold V
Hysteresis 5 %

PGood Voltage Low I

High Side Driver(CL=4700pF)

Output Impedance , Sourcing
Current

Current
Rise Time THdrv(Rise) V

Fall Time THdrv(Fall) V
Deadband Time Tdead(L to

Rev.4.8
05/06/08

R

(Hdrv) I=200mA

source

R

(Hdrv) I=200mA

sink

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Falling 74 %V

SEN

=-5mA 0.5 V

PGood

1.1 ohm

0.8

BST-VSW
BST-VSW

=4.5V 24 ns
=4.5V 24 ns

30 ns

ID

ohmOutput Impedance , Sinking

3

NEXSEM

PARAMETER

SYM

TEST CONDITION

MIN

TYP

MAX

UNITS

(C

=4700pF)

Current

Amplifier(CS+, CS-)

Mismatch

Source(Droop)

OCP Adjust

Vref

OVP Threshold

kohm

Low Side Driver

NX2415

Output Impedance, Sourcing

Output Impedance, Sinking
Current
Rise Time TLdrv(Rise) 10% to 90% 40 ns
Fall Time TLdrv(Fall) 90% to 10% 36 ns

Current Sense

Current Sense Amplifier

Voltage Gain K 29.7 30 30.3 V/V

Droop Voltage Current

Blank time before activating
OCP

Reference Voltage 1.6 V
Driving current ability 5 mA

R

(Ldrv) I=200mA 1.1 ohm

source

R

(Ldrv) I=200mA 0.5 ohm

sink

30

High, 10% to 10%

0 mV

V(IOUT)=0.6V,feedback

resistor=10kohm,Rdroop=60

200Khz/Phase 15 uS

nsDeadband Time Tdead(H to L)SW going Low to Ldrv going

uADroop Voltage Current Source 100

OVP Threshold 0.96 V

Rev.4.8
05/06/08

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4

NEXSEM

PIN DESCRIPTIONS

PIN # SYMBOL PIN DESCRIPTION

31

VCC

IC’s supply voltage. This pin biases the internal logic circuits. A minimum 1uF
ceramic capacitor is recommended to connect from this pin to ground plane.

NX2415

25,

16

22,

19
30

24, 17

26,15

23,

18
28

4

5

HDRV1,

HDRV2

LDRV1,

LDRV2

EN

BST1,BST2

SW1,SW2

PVCC1,

PVCC2

PGOOD

VP

FB

High side gate driver outputs.

Low side gate driver outputs.

This pin is used to remotely turn off the controller. The pin has a threshold
voltage of 0.6 volts.

These pins supplies voltage to high side FET drivers.
These pins are connected to the source pins of the upper fets.
These pins provide the supply voltage for the lower MOSFET drivers.

This pin is an open collector output. If used, it should be pulled to 5V with a
resistor greater than or equal to 10k, otherwise it my be left open. Any fault or
under voltage on the enable pins will cause the signal to be pulled low.

Input to the positive pin of the error amplifier. A resistor is connected from the
output of the DAC to this pin. Place a small capacitor from this pin to GND to
filter any noise.

This pin is the error amplifier inverting input. It is connected to the output voltage
via a voltage divider.

9,12

10,13

Rev.4.8
05/06/08

11

2

6

7

RT

CS+1,CS+2

CS-1,CS-2

CSCOMP

VCOMP

DROOP

This pin programs the internal oscillator frequency using a resistor from this pin to
ground. The frequency of each phase is 1/2 of this frequency.

Positive input of the differential current sense amplifiers. It is connected directly
to the RC junction of the respective phase’s output inductor.

Negative input of the differential current sense amplifiers. It is connected directly
to the negative side of the respective phase’s output inductor.

The output of the transconductance op amp for current balance circuit. An
external RC is connected from this pin to GND to stabilize the current loop.

This is the output pin of the error amplifier. The compensation network connec­tion.

A resistor from this pin to ground programs an internal current source that is fed
into the FB pin. This current source is proportional to the output current of the
regulator. The product of this current times the external resistor RFB provides a
droop voltage.

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5

NEXSEM

PIN # SYMBOL PIN DESCRIPTION

8

OCP

A resistor divider connected from this pin to Vref programs the current limit thresh­old. The outputs of the internal current sense differential amplifiers are summed
together to represent the output current. This voltage is then compared to this thresh­old.

NX2415

1

29

21,

20
32
14

3

VREF

ENBUS

PGND1,

PGND2

AGND

IOUT

PGSEN

A 1.6V buffered reference is brought out.
This pin is used to program the under voltage lockout of the bus supply. A resistor

divider from the bus voltage to this pin programs the under voltage lockout. When
the voltage of this pin is greater than 1.6V, the bus voltage is assumed in operation.
The pin has a 10% hysterisis.

This is the ground connection for the power stage of the controller.

Controller analog ground pin.
Input of OCP amplifier. Place a 10nF to 100nF capacitor from this pin to GND to

filter any noise.
Output over voltage and Pgood sensing pin. A resistor divider plus a small capacitor

should be connected to the this pin to set the OVP and Pgood.

Rev.4.8
05/06/08

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6

NEXSEM

BLOCK DIAGRAM

NX2415

VCC

Enbus

EN

Vp

VCOMP

Rt

FB

1.6/1.44

0.64
/0.53V

Bias
generator

Digital
start

Droop current

0.8V

1.6V

1.25V

SS_finish

Dis_EA

ramp1

0.8V

Two phase
OSC

UVLO

Hiccup

Set1

set2

UVLO

K=30

start

R
S

CS01

CS02

Q

V1.25

KR

KR

OVP

R

R

FET
driver

PVCC1

PVCC2

BST1

BST2

DrvH1

DrvH2

DrvL2
DrvL1

SW1
SW2

PGND1
PGND2

CS+1

CS-1

Vref

PGsen

Pgood

AGND

1.6V

0.8*120%

0.64/0.6

SS_finished

32 cycles
filter

ramp2

OVP

Hiccup

Hiccup
Logic

V1.25

Slave channel control

V1.25

Σ

6 Cycles
filter

Current Mirror

FB

÷

2

KR

PWM control
logic
and driver

KR

R

R

gm*Ri=0.6

Σ

CS+2

CS-2

CScomp

gm

IOUT

Ri

OCP

Droop

Rev.4.8
05/06/08

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7

NEXSEM

RIPPLEINS

1

IVF

12V400kHz

L=0.54uH

=3.97A

ESR=3.022m

==Ω

ERIPPLE

7m3.97A

12mV

SRIPPLE

NX2415

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Operation frequency for each channel
DIRIPPLE - Inductor current ripple

Design Example

The following is typical application for NX2415.
VIN = 12V
VOUT=1.2V
IOUT=50A
IOUT_max=60A
DVRIPPLE <=12mV
DVDROOP<=120mV @30A step
FS=400kHz
Phase number N=2

Output Inductor Selection

The selection of inductor value is based on induc­tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu­ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli­cation requirements. The inductor value can be calcu­lated by using the following equations:

V-VV

L=

∆×

where k is between 0.2 to 0.4.

Select k=0.2, then

L=

INOUT OUT

OUT

∆

I=k

RIPPLE

12V-1.2V1.2V1

OUT

0.2

××

I

OUTPUT

N

50A

×

2

××

...(1)

OUT

Choose inductor from Vishay IHLP_5050FD-01

with L=0.68uH DCR=1.4mΩ.

Current Ripple is recalculated as

V-VV

I=

∆××

RIPPLE

INOUT OUT

LVF

OUTINS

12V-1.2V1.2V1

0.68uH12V400kHz

××=

1

...(2)

Output Capacitor Selection

Output capacitor value is basically decided by the
output voltage ripple, capacitor RMS current rating and
load transient.

Based on Voltage Ripple

For electrolytic, POSCAP bulk capacitor, the ESR
(equivalent series resistance) and inductor current typi­cally determines the output voltage ripple.

V

∆

tiple capacitors in parallel are better than a big capaci­tor. For example, for 12mV output ripple, SANYO OS­CON capacitors 2R5SEPC1000MX(1000uF 7mΩ) are
chosen.

mined by the number of capacitor instead of ESR

that the output voltage droop during the transient can
not meet the spec although ripple is small.

desire

If low ESR is required, for most applications, mul-

N

=

Number of Capacitor is calculated as

N

=

N =2.3

For ceramic capacitor, the current ripple is deter-

C

OUT

Typically, the calculated capacitance is so small

RIPPLE

I3.97A

∆

RIPPLE

ESRI

∆

Ω×

=

8FV

××∆

V

∆

×∆

I

RIPPLE

12mV

RIPPLE

...(3)

...(4)

...(5)

Rev.4.8
05/06/08

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8

NEXSEM

DROOPTRAN

2

∆=×∆+×τ

OUTEFFcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEEFFcrit

ESRCifLL

0.28H

=µ

7m1000F1.5us

2

1.78×∆=+×τ

NX2415

Based On Transient Requirement

Typically, the output voltage droop during transient

is specified as:

V<V∆∆ @ step load DI

During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, overshoot caused by

DISTEP transient load which is from high load to low load,

can be estimated as the following equation,if assuming
the bandwidth of system is high enough.

VESRI

tance of each capacitor if multiple capacitors are used
in parallel.

put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca­pacitance is high and
transient spec is dependent on the ESR of capacitor.

capacitors in parallel. The number of capacitors can be
calculated by the following

overshootstep

where τ is the a function of capacitor, etc.

0ifLL




LI

τ=

L0.34uH

L

×∆



EFFstep



V

OUT



where

L

OUT

===

EFF

N2

ESRCVESRCV

==

crit

where ESRE and CE represents ESR and capaci-

The above equation shows that if the selected out-

In most cases, the output capacitors are multiple

ESRI

N

where

≤

EFFcrit

−×≥

0.68uH

××××

II

∆∆

stepstep

×∆

Estep

V2LCV

∆×××∆

tranEtran

2LC

≤ is true. In that case, the

V

OUT

V

OUT

××

STEP

OUT

...(6)

...(7)

...(8)

...(9)

0ifLL




LI



EFFstep




V

×∆

OUT

τ=

≤

EFFcrit

−×≥

...(10)

For example, assume voltage droop during transient

is 120mV for 30A load step.

If the OS-CON capacitors (1000uF, 7mΩ ) is used,

the critical inductance is given as

ESRCV

××

L

crit

7m1000F1.2V

Ω×µ×

The effective inductor value is 0.34uH which is big­ger than critical inductance. In that case, the output volt­age transient not only dependent on the ESR, but also
capacitance.

number of capacitors is

τ=−×

=−Ω×µ=

N

=+

20.34H1000F120mV

×µ×µ×

=

The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.

It should be considered that the proposed equa­tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more capaci­tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es­pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.

EEOUT

==

LI

0.34H30A

ESRI

7m30A

120mV

I

∆

step

30A

×∆

EFFstep

V

OUT

µ×

1.2V

Estep

V2LCV

∆×××∆

Ω×

ESRC

EE

V

OUT

tranEFFEtran

1.2V
(1.5us)

×

2

Rev.4.8
05/06/08

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9

NEXSEM

F ...(11)

F ...(12)

F ...(13)

F ...(14)

NX2415

Control Loop Compensator Design

NX2415 can control and drive two channel synchro­nous bucks with 180o phase shift between each other.
One of two channels is called master, the other is called
slave. They are connected together by sharing the same
output capacitors. Voltage loop is designed to regulate
output voltage. In order to achieve the current balance in
these two synchronous buck converters, current loop
compensation network is employed to to make sure the
currents in slave is following the master.

Voltage Loop Compensator Design

Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching fre­quency, phase margin greater than 50o and the gain cross­ing 0dB with -20dB/decade. Power stage output capaci­tors usually decide the compensator type. If electro­lytic capacitors are chosen as output capacitors, type II
compensator can be used to compensate the system,
because the zero caused by output capacitor ESR is
lower than crossover frequency. Otherwise type III com­pensator should be chosen.

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo OSCON and POSCAP, the frequency of ESR zero
caused by output capacitors is higher than the cross­over frequency. In this case, it is necessary to compen­sate the system with type III compensator.

In design example, six electrolytic capacitors are
used as output capacitors. The system is compensated
with type III compensator. The following figures and equa­tions show how to realize the this type III compensator
with electrolytic capacitors.

1

2RC

×π××

42

1

2(RR)C

×π×+×

233

1

2RC

×π××

33

1

CC

×

2R

×π××

4

CC

12

+

12

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

C2

Fb

Zf

C1

R4

Zin

Vout

R3

R2

C3

Ve

R1

Vref

Figure 2 - Type III compensator

power stage

LC

F

Z2

F

40dB/decade

F

ESR

P1

F

20dB/decade

F

O

F

P2

Gain(db)

loop gain

compensator

Z1

F

Rev.4.8
05/06/08

Figure 3 - Bode plot of Type III compensator

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10

NEXSEM

1V240kHz0.34uH10k3.92k

12V3.5m10k3.92k

×π××Ω×Ω

ΩΩ+Ω

20.756.1kHz5.62k

×π×××Ω

25.62k200kHz

Gain= ... (15)

F= ... (16)

F ... (17)

[

]

42233

(1sRC)1s(RR)C

20.34uH2000uF

23.5m2000uF

==Ω

R=20k

=(-)

210k6.1kHz22.7kHz

=1.9nF

222.7kHz1.8nF

NX2415

The transfer function of type III compensator

is given by:

V

e

=×

VsR(CC)

OUT 221

1

×+

+××++×

CC

×

(1sR)1sRC

+××+×

21

433

CC

21

+

( )

Use the same power stage requirement as demo
board. The crossover frequency has to be selected as
FLC<F

and ESR zero F

, and usually FO<=1/10~1/5FS.

ESR<FO

1.Calculate the location of LC double pole F
.

ESR

F

=

LC

2LC

=

1

×π××

EFFOUT

1

LC

×π××

6.1kHz

=

F

ESR

22.7kHz

=

2ESRC

=
=

1

×π××

OUT

1

×π×Ω×

2.Set R2 equal to10kΩ.

RV

2REF

1

V-V1.2V-0.8V

OUT REF

Ω×

10k0.8V

×

Choose R1= 20kΩ.

3. Calculate C3 by setting FZ2 = F

C=(-)

3

111

2RFF

×π×

×π×Ω

×

2z2p1

111

×

and Fp1 =F

LC

ESR

Choose C3=1.8nF.

5. Calculate R3 by equation (13).

6. Calculate R4 by choosing FO=40kHz.

V2FLRR

R=

4

VESRRR

=
=5.73k

×π×××

OSCOEFF23

××

in23

+

××

Ω

Choose R4=5.62kΩ.

7. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

1

2FR

×π××

Z14

1

C

=

2

=

6.2nF

=

Choose C2=6.8nF.

8. Calculate C1 by equation (14) with pole Fp2 at

half the switching frequency.

C

=

1

=

141pF

=

1

2RF

×π××

4P2

1

×π×Ω×

Choose C1=150pF.

B. Type II compensator design

.

If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa­tor can be used to compensate the system.

Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 4. R3 and C1
introduce a zero to cancel the double pole effect. C2
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero lo­cation and constant gain.

R

=

3

=

3.89k

=Ω

1

2FC

×π××

P13

1

×π××

Choose R3=3.92kΩ.

Rev.4.8
05/06/08

z

p

www.nexsem.com

R

3

R

2

1

2RC

×π××

31

≈

1

2RC

×π××

32

11

NEXSEM

20.75uH10800uF

213m1800uF

==Ω

R=20k

=10k

=27.3k

××Ω

227.4k0.751.768kHz

p

F

27.4k100kHz

NX2415

C2

Vout

R3

C1

R2

Fb

R1

Vref

Figure 4 - Type II compensator

power stage

40dB/decade

Gain(db)

loop gain

20dB/decade

Ve

1

×π××

EFFOUT

1

F

=

LC

2LC

=

×π××

1.768kHz

=

1

×π××

OUT

1

×π×Ω×

F

=

ESR

2ESRC

=

6.801kHz

=

2.Set R2 equal to10kΩ and calculate R1.

RV

2REF

1

V-V1.2V-0.8V

OUT REF

Ω×

10k0.8V

×

3. Set crossover frequency FO=15kHz.

4.Calculate R3 value by the following equation.

V2FL

R=R

OSCOEFF

32

VESR

in

1V215kHz0.75uH

12V2.16m

×π××

××

×π××

Ω

Ω

compensator

F

F

LC

Z

ESRFO

Gain

F

P

F

Figure 5 - Bode plot of Type II compensator

For this type of compensator, FO has to satisfy

FLC<F

<< FO and FO <=1/10~1/5F

ESR

s.

Here a type II compensator is designed for the case
which has six electrolytic capacitors(1800uF, 13mΩ) and
two 1.5uH inductors.

1.Calculate the location of LC double pole F

and ESR zero F

ESR

.

LC

Choose R3 =27.4kΩ.

5. Calculate C1 by setting compensator zero F

at 75% of the LC double pole.

C=

1

=
=4.4nF

1

2RF

×π××

3z

1

×π×Ω××

Choose C1=4.7nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

C=

2

=
=116pF

1

RF

π××

3s

1

π×Ω×

Choose C2=100pF.

Z

Rev.4.8
05/06/08

www.nexsem.com

12

NEXSEM

Current Loop Compensator Design

NX2415

Power stage

Master
channel

Ramp for
slave channel

Compensation

D(s)

Current Sensing
Amplifier Gain

1

Vosc

d

s*L+DCR

Rs*Cs*s+1

Inductor Current
sense

Figure 6 - Current loop control diagram

V

IN

Vbias

V

IN

PWM control
logic
and driver

Vbias

Vin

s*L+Req

master channel

L

Rs

Rs

Slave channel 1
L

Rs

Rs

iL

DCR

Cs

DCR

Cs

V

OUT

Rev.4.8
05/06/08

Icomp1

Slave channel control

Slave channel control

Rcc

Slave channel

Figure 7 - Function diagram of current loop

www.nexsem.com

C1

C2

13

NEXSEM

L

DCR

S_ILL

VDCRi

=×

1

CF

=µ

S

DCRC

486

==Ω

S

DCRC

01101

004

.(.)

NX2415

Inductor Current Sensing

V

IN

Control &
Driver

Current
Sensing

Rs

L

Rs

i

L

DCR

V

OUT

Cs

V

S_IL

Amplifier

Figure 8 - Inductor current sensing using RC network.

The inductor current can be sensed through a RC
network as shown above. The advantage of the RC net­work is the lossless comparing with a resistor in series
with output inductor.

The selection of the resistor sensing network is
chosen by the following equation:

RC

×=

SS

...(18)

racy during the transient if droop function is required.
The illustration is shown in the following figure.

Overshoot caused
by inductor

V

S_IL

----Voltage accross

nonlinearity

the sensing
capacitor Cs

iL--- inductor current

Output voltage
with droop function

Droop misbehavoir
caused by
overshoot of V

S_IL

Figure 9 - Droop accuracy affected by the nonlinearity
of inductor.

If the above equation is satisfied, the voltage across
the sensing capacitor Cs will be equal to the inductor
current times DCR of inductor for all frequency domain.

If the sensing capacitor is chosen

S

CS must be X7R or COG ceramic capacitor.

The sensing resistor is calculated as

R

S

L

=

×

For example, for 0.68uH inductor with 1.4mΩ
DCR, we have

068

.H

R

S

141

µ

.mF

Ω×µ

In most of cases, the selection of sensing resis­tor based on the above equation will be sufficient. How­ever, for some inductor such as toroid coiled inductor
with micrometal, even the product of sensing resistor
and capacitor is perfectly match with L/DCR, the voltage
across the capacitor still has overshoot due to the
nonlinearity of inductor. This will affect the droop accu-

In this case, the sensing resistor has to be chosen

R

S

L

≥

×

to compensate the overshoot. This selection only af­fects the small signal mode of current loop. For DC ac­curacy, there is no effect since the DC voltage across
the sensing capacitor will equal to the DCR times induc­tor current at DC load no matter what Rs is. In this ex­ample, Rs=620Ω.
RS value is preferred to be less than 400Ω in
NX2415's application, therefore we need to reiterate the
calculation, choose CS 2.2uF instead. RS value is finally
chosen as 301Ω .
Powe dissipation of Rs resistor is calculated as
followed:

(VV)V

−

P(R)D(D)

DS

=×+×−
=

INOUTOUT

=×+×−

121212

(V.V)(.V)

−

301301

.W

22

RR

SS

22

1

ΩΩ

The power rating of Rs should be over 0.04W.

Rev.4.8
05/06/08

www.nexsem.com

14

NEXSEM

F.kHz

12

RCC

oosc

gVKDCR

229

K.

442

==Ω

430

=Ω

214

CnF

×π×







dson_con

dson_syn

R.m

=Ω

Current Loop Compensation

NX2415

R

eq

===

1

P

22068

L.H

×π××π×µ

74

.m

Ω

17

Slave channel
power stage

Current loop
compensation

Loop gain
for slave
channel

Fp1

Fzc Fpc

-20 dB

-20dB
0 DB

-40dB

Fo

Figure 10 - Bode plot of current loop

The diagram and bode plot for current loop of
NX2415 is shown in above figures. The current signal
through inductor sensing is amplified by current sensing
differential amplifier. The amplified slave current signal
is compared with the amplified inductor current from
master channel (channel 1 for NX2415) through a
transconductance amplifier, the difference between chan­nel current will change the output of transconductance
amplifier, which will compare with a internal ramp signal
and changes the duty cycle of slave channel buck con­verter. If the inductor are perfectly matched and the PWM
controller has no offset, the DC current in slave channel
will equal to the DC current of master channel (channel

1) due to the gain of current loop.

From the bode plot, the power stage has one pole
located at

R

FL=

1

P

eq

2

where Req is the equivalent resistor and it is given by

VV

RDCRRR

≈+×+×−

eqdson_condson_syn

R

is the Rdson of control FET and

OUTOUT

VV

ININ

1

R

is

the Rdson of synchronous FET. For this example,

74

eq

The pole is located as

The current compensation transfer function is

given as

1

sRCg

D(s)

=×

m

sCC

×+

( )

12

1

+××

cc

s

+×

1

cc

××

CC

+

12

It has one zero and one pole. The ideal is to
choose resistor Rcc to achieve desired loop gain such
as 50kHz. Rcc can be calculated as

2

FLV

R

×π×××

=

cc

mINC

×××

...(19)

where

60

k

⋅Ω

≈=

C

2

kR

Ω+

S

60kΩ and 2kΩ is the internal resistance for the current
sensing amplifier.

For fast response, we can set the current loop
cross-over frequency one and half times of voltage loop
cross-over frequency. Since the voltage loop cross-over
frequency is typically selected as 1/10 of switching fre­quency, we choose FO=50kHz.

R

2500681

cc

161222914

.mA/VV..m

kHz.HV

×π××µ×

×××Ω

Select

R

cc

.

The selection of capacitor C1 is such that the zero
of compensation will cancel the pole of power stage,
therefore,

L.H

===

1

RR.m

×Ω×Ω

eqcc

068

µ

74430

Typically, the capacitor C1 is so big that the cur­rent loop may start slowly during the start up. There­fore, smaller capacitor can be selected. However, the
selected capacitor can not reduce too much to cause
phase droop.
Select C1=220nF.

The capacitor C2 is an option and it is used to
filter out the switching noise. C2 can be calculated as

Rev.4.8
05/06/08

www.nexsem.com

15

NEXSEM

185

C.nF

18600000

OCPOCP

V0.6I

Ω

=×Ω

OUTDROOPINLOADLL

VIRIR

R3m

==Ω

LOAD

NX2415

RFkHz

π××π×Ω×

ccS

430400

11

===

2

Select C2=2.2nF.

Frequency Selection

The frequency can be set by external Rt resistor.
The relationship between frequency per phase and RT
pin is shown as follows.

RF≈

T

800

700

600

500

400

300

frequency(kHz)

200

100

0

0 50 100 150 200

...(20)

S

FREQUENCY(kHz) vs RT(kohm)

Rt(kohm)

VREF

100k

OCP

R

OCP

Figure 12 - Over current protection

Output Voltage Droop Operation

The effective output impedance of the controller must
be adjusted to maximize the output voltage fluctuation
range. A program resistor attached to the Droop pin
R

will program this value. The function works by an

DROOP

internal current source connected to the FB pin. This
current flows output of the FB pin and through the Rin
resistance from the FB pin to the output.

This current source is a function of the sensed
output current. As the output current increases, the droop
current will increase and causes the output voltage
todroop proportionately. The droop current is programmed
by a resistor attached to the Droop pin. The value of the
resistor is chosen as follows.

Figure 11 - Frequency vs Rt chart

Over Current/Short Circuit Protection

The converter will go into hiccup mode if the

output current reaches a programmed limit V
determined by the voltage at pin OCP.

=

R100k

OCP

Where I
level,100kΩ is the resistor connecting V
I

pin. RS is the current sensing matching resistor

OCP

when using DCR sensing method.

Rev.4.8
05/06/08

60kDCR

2kR2

Ω+

S

V

OCP

VV

−

REFOCP

is the desired over current protection

ocp

...(21)

pin and

REF

www.nexsem.com

VOUT

OCP

IN

R

FB

I

V

P

Figure 13 - Output voltage droop funciton

∆=×=∆× ...(22)

Where RLL is desired load impedance. For example,

if we want Vout droops 60mV @ 20A,

60mV

LL

20A

V(IOUT)

=

R

DROOP

60kDCR

0.6I

×××

Ω

2kR2

Ω+

S

R

DROOP

I

DROOP

=

DROOP

Error Amplifer

...(23)

COMP

16

NEXSEM

75

I.A

0

D

(

)

Iout

LOADIN

DCRIR

0.660k1.4m20A10k

ΩΩ××Ω

NX2415

Combine equation 22 and 23,

R

DROOP

Where DCR is the sense resistor or the DCR of
the output inductor. RS is the current sensing matching
resistor when using DCR sensing method. I
load current. RIN is the input DC resistor of the master
phase compensator which connect FB pin and PGSEN
pin. For example, to have the DV
load current is 20A, DCR is 1.4mΩ, RIN is 10kΩ, RS is
620Ω.

R

DROOP

32k

=Ω

Choose R

0.660k

=

22kRV

=××

22k0.62k60mV

DROOP

Ω

Ω+∆

SOUT

Ω+Ω

= 32kΩ.

...(24)

LOAD

=60mV when the

OUT

is the

Over Voltage Protection

Over voltage protection is achieved by sensing the
output voltage through resistor divider. The sensed volt­age on PGSEN pin is compared with 120%*0.8V to gen­erate the OVP signal. A small value capacitor is re­quired to connect to PGSEN pin also.

be calculated. From this figure, it is obvious that a multi­phase converter can have a much smaller input RMS
current, which results in a lower amount of input capaci­tors that are required.

For example, Vin=12V, Vout=1.2V. The duty cycle
is D=Vout/Vin=1.2/12=10%. From the figure, for two
phase, the normlized RMS current is

0.2*Iout=0.2*50A=10A.

A combination of ceramic and electrolytic(SANYO
WG or WF series) or OSCON type capacitors can
achieve both ripple current capability together with hav­ing enough capacitance such that input voltage will not
sag too much. In this application, one OSCON
SVPC180M(180uF, 16V, 2.8A) and three 10uF(4A rms
current, X5R) ceramic capacitors are selected.

A 1uH input inductor is recommended to slow down
the input current transient. Suppose power stage effi­ciency is 0.8, then input current can estimated by

IV

INPUT

In this application, Coilcraft DO3316P_102HC with
RMS rating 10A is chosen.

V.V

η××

IN

×

OUTOUT

===

6012

A.V

×

0812

VOUT 1.2V

10k

20k

PGSEN

Figure 14 - Over voltage protection

0.8V*120%
OVP

1nF

Input Filter Selection

The selection criteria of input capacitor are voltage
rating and the RMS current rating. For conservative con­sideration, the capacitor voltage rating should be 1.5
times higher than the maximum input voltage. The RMS
current rating of the input capacitor for multi-phase con­verter can be estimated from the above Figure 15.

First, determine the duty cycle of the converter (VO/
VIN). The ratio of input RMS current over output current
can be obtained. Then the total input RMS current can

0.5

0.4

0.3

INI

RMS

0.2

0.1

0

Figure 15 - Normalized input RMS current vs.

Three
phase

0.1 0.2 0.3

duty cycle.

Single­phase

Two
phase

0.4 0.5

Rev.4.8
05/06/08

www.nexsem.com

17

NEXSEM

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

P=I(1D)RK

×−××

SWINOUTSWS

PVITF

=××××

SW

T

S

dt4082F

×

4082

F

NX2415

Power MOSFETs Selection

The NX2415 requires two N-Channel power
MOSFETs for each channels. The selection of
MOSFETs is based on maximum drain source voltage,
gate source voltage, maximum current rating, MOSFET
on resistance and power dissipation. The main consid­eration is the power loss contribution of MOSFETs to
the overall converter efficiency. In this design example,
eight NTD60N02 are used. They have the following pa­rameters: VDS=25V, ID =62A,R

=12mΩ,Q

DSON

GATE

=9nC.

There are three factors causing the MOSFET power
loss:conduction loss, switching loss and gate driver loss.

Gate driver loss is the loss generated by discharg­ing the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:

...(24)

where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V

LGS

is

the low side gate source voltage. This power dissipation

should not exceed maximum power dissipation of the
driver device.

Conduction loss is simply defined as:

P=IDR

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

Where the RDS(ON) will increases as MOSFET jun­ction temperature increases, K is RDS(ON) temperature
dependency and should be selected for the worst case.
Conduction loss should not exceed package rating or
overall system thermal budget.

Switching loss is mainly caused by crossover con­duction at the switching transition. The total switching
loss can be approximated.

mosfet datasheet, IOUT is output current, and FS is switch­ing frequency. Swithing loss PSW is frequency depen-
dent.

2

×××

2

K

...(25)

+

1
2

...(26)

is the sum of TR and TF which can be found in

Soft Start and Enable Signal Operation

The NX2415 will start operation only after Vcc and
PVcc have reached their threshold voltages and EN and
ENBUS have been enabled. The ENBUS pin can be pro­grammed to turn on the converter at any input voltage.
The ENBUS pin has a threshold voltage of 1.6V.

Once the converter starts, there is a soft start se­quence of 4082 steps between 0 and Vp. The ramp rate
is determined by the switching frequency.

dVV

OO

=

...(27)

The softstart time is calculated as followed:

T

=

startup

...(28)

S

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

There are two sets of components considered in
the layout which are power components and small sig­nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch­ing power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in­cludes power plane, ground plane and signal plane is
recommended .

Layout guidelines:

1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.

2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touching
the drain pin of the upper MOSFET, a plane connection
is a must.

3. The output capacitors should be placed as close

Rev.4.8
05/06/08

www.nexsem.com

18

NEXSEM

as to the load as possible and plane connection is re­quired.

4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.

5. Source of the lower MOSFET needs to be con­nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by­passing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.

8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.

9. All GNDs need to go directly thru via to GND
plane.

10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.

11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana­log control function.

12. Inductor current sense line should be con­nected directly to the inductor solder pad.

NX2415

Rev.4.8
05/06/08

www.nexsem.com

19

NEXSEM

MLPQ 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS

NX2415

Rev.4.8
05/06/08

NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.

www.nexsem.com

20

NEXSEM

MLPQ 32 PIN 5 x 5 TAPE AND REEL INFORMATION

NX2415

Rev.4.8
05/06/08

NOTE:

1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.

2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.

www.nexsem.com

21

NEXSEM

Customer Service

NEXSEM Inc.

NX2415

500 Wald

Irvine, CA 92618

U.S.A.

Tel: [phone]

Fax: [phone]

WWW.NEXSEM.COM

Rev.4.8
05/06/08

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22