Page 1
Evaluation board available.
NX2309
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER
WITH NMOS LDO CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2309 controller IC is a combination synchronous
Buck and LDO controller IC designed to convert single
12V supply to low cost dual on board supply applications. The synchronous controller is used for high current high efficiency step down DC to DC converter applications while the LDO controller in conjunction with an
external low cost N ch MOSFET can be used as a very
low drop out regulator in applications such as converting
3.3V to 2.5V output. Internal UVLO keeps both regulators off until the supply voltage exceeds 9V where independent internal digital soft starts get initiated to ramp
up both outputs.The switching section has fixed hiccup
current limit by sensing the Rdson of synchronous
MOSFET. The LDO controller has Feedback Under
Voltage Lock Out as a short circuit protection.Other features includes: 12V gate drive capability , Adaptive dead
band control.
R14
C12
LDO OUT
LDO FB
COMP
FB
1uF
VCC
N X 2 3 0 9
GND
VOUT1
+1.8V
VOUT2
+1.2V/2A
C9
47uF
C8
150uF
25mohm
M3
IRFR3706
R8
5k
C13
200pF
150pFC10
R9
10k
R5
5.36k
C5
6.8nF
FEATURES
n 12V PWM controller plus LDO controller
n Fixed hiccup current limit by sensing Rdson of
MOSFET
n 12V high side and low side driver
n Fixed internal 300kHz for switching controller
n Dual Independent Digital Soft Start Function
n Adaptive Deadband Control
n Shut Down switching via pulling down COMP pin
n Pb-free and RoHS compliant
APPLICATIONS
n PCI Graphic Card on board converters
n Mother board On board DC to DC applications
n On board Single Supply 12V DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Set Top Box and LCD Display
TYPICAL APPLICATION
10
BST
HDRV
SW
LDRV
D1 MBR0530T1
C4
0.1uF
L1 1uH
C2
180uF
M1
IRFR3709Z
L2 1.5uH
M2
IRFR3709Z
R2
1.43k
C6
2.7nF
C3
47uF
R3
10k
C7
4SEPC560M
560uF,7mohm
VIN1
+12V
VOUT1
+1.8V/10A
R4
8k
Figure1 - Typical application of NX2309
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2309CUTR 0 to 70oC MSOP - 10L 300kHz Yes
NX2309CMTR 0 to 70oC MLPD - 10L 300kHz Yes
Rev. 2.0
12/19/05
1
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NX2309
θ≈200/
CW
θ≈52/
CW
Supply Current
ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP 10-LEAD PLASTIC MLPD
Gnd
(PAD)
o
10
SW
COMP
9
FB
8
LDO_FB
7
LDO_OUT
6
BST
HDrv
Gnd
LDrv
Vcc
JA
1
2
3
4
5
o
10
SW
9
COMP
8
FB
7
LDO_FB
6
LDO_OUT
BST
HDrv
NC
LDrv
VCC
JA
1
2
3
4
5
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, V
BST-VSW
values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
REF
Ref Voltage line regulation 10V<=VCC<=14V 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
V
CC
CC
ICC (Static) mAOutputs not switching 5
(Static)
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Voltage Range V
BST
V
Supply Current V
BST
BST)
I
CC
(Dynamic)
to V
BST
SW
BST
CL=3300PF 17 mA
CL=3300PF 12 mA
(Dynamic)
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.3 V
=12V, and TA = 0 to 70oC. Typical
0.8
7 14
7 14
6.6
V
V
V
V
Rev. 2.0
12/19/05
2
Page 3
NX2309
High Side Driver, Hdrv, BST,
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
Oscillator
Frequency F
Ramp-Amplitude Voltage V
Max Duty Cycle
S
RAMP
Min Duty Cycle
Error Amplifiers
Open Loop Gain 50 65 dB
Transconductance gm 2000 umho
Input Bias Current Ib 100 nA
EN & SS
Soft Start time Tss 6.8 mS
Comp SD threshold 0.2 V
SW (CL=3300pF)
Output Impedance , Sourcing
R
(Hdrv) I=200mA
source
Current
R
(Hdrv) I=200mA
sink
Current
Rise Time THdrv(Rise) 10% to 90% 30 ns
Fall Time THdrv(Fall) 90% to 10% 20 ns
Deadband Time
Tdead(L to
H)
High, 10% to 10%
300 KHz
1.1 V
95 %
0
%
ohm3.6
1 ohmOutput Impedance , Sinking
ns50
Low Side Driver , Ldrv,
PVcc, Pgnd(CL=3300pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 2.2 ohm
source
Current
Output Impedance, Sinking
Current
N
R
(Ldrv) I=200mA 1 ohm
sink
Rise Time TLdrv(Rise) 10% to 90% 30 ns
Fall Time TLdrv(Fall) 90% to 10% 20 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
50
ns
High, 10% to 10%
LDO Controller
FB Pin- Bias Current
High Output Voltage
Low Output Voltage 0.2
High Output Source Current
Low Output Sink Current
Open Loop Gain GBNT(NOTE 2)
50
100
nA
11.1 V
1.9 mA
0.9 mA
db
V
FB Under Voltage trip point 50 %
Fixed OCP
OCP Voltage Threshold 240 mV
Rev. 2.0
12/19/05
3
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NX2309
NOTE1: In actual circuit application, the ENSW pin is used to program converter start up and hysteresis threshold
voltage.
NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as
5
1
VCC
BST
possible to and connected to this pin and ground pin. The maximum rating of this
pin is 16V.
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic
capacitor is placed as close as possible to and connected to this pin and SW
pin.
10
3
8
9
2
4
6
GND
FB
COMP
SW
HDRV
LDRV
LDO_FB
Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor
divider to the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut down
pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft
start is reset.
This pin is connected to source of high side FETs and provide return path for the
high side driver. It is also used to hold the low side driver low until this pin is
brought low by the action of high side turning off. LDRV can only go high if SW is
below 1V threshold .
High side gate driver output.
Low side gate driver output.
LDO controller feedback input. This pin is connected via resistor divider to the out-
put of the switching regulator to set the output DC voltage.If the LDOFB pin is pulled
below 0.4V, an internal comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the startup this latch is not activated, allowing
the LDOFB pin to come up and follow the soft started Vref voltage.
Rev. 2.0
12/19/05
7
LDO_OUT
LDO controller output. This pin is controlling the gate of an external NCH MOSFET.
The maximum rating of this pin is 16V.
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Page 5
BLOCK DIAGRAM
NX2309
VCC
FB
COMP
GND
Bias
Regulator
Bias
Generator
COMP
0.2V
START
0.8V
Digital
start Up
ramp
START
1.25V
0.8V
7.2/6.8V
OSC
0.6V
CLAMP
UVLO
1.3V
CLAMP
POR
START
OC
Control
Logic
PWM
S
Q
R
Hiccup Logic
OC
0.4
OCP
comparator
VCC
240mV
BST
HDRV
SW
LDRV
LDOFB
Rev. 2.0
12/19/05
POR
LDO digital
start up
Figure 2 - Simplified block diagram of the NX2309
LDOOUT
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NX2309
RIPPLEINS
1
IVF
0.410A12V300kHz
=3.4A
SOUT
==Ω
ESR=7.3m
ERIPPLE
7m3.4A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VIN=12V
VOUT=1.8V
IOUT =10A
DVRIPPLE <=25mV
DVTRAN<=100mV @ 5A step
FS=300kHz
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
OUT
INOUT OUT
××
×
12V-1.8V1.8V1
×
××
...(1)
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.4, then
L=
OUT
L=1.3uH
OUT
Choose LOUT=1.5uH, then coilcraft inductor
DO5010P-152HC is a good choice.
Current Ripple is calculated as
V-VV
I=
RIPPLE
INOUT OUT
LVF
12V-1.8V1.8V1
1.5uH12V300kHz
××
OUTINS
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
is the value of output capacitors.
OUT
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, OSCON are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
desire
V
RIPPLE
∆
I3.4A
RIPPLE
25mV
∆
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 25mV output ripple, OSCON
4SEPC560M with 7mΩ are chosen.
ESRI
N
=
∆
×∆
V
RIPPLE
Number of Capacitor is calculated as
25mV
Ω×
=
N
N =0.95
The number of capacitor has to be round up to a
integer. Choose N =1.
RIPPLE
××
8FC
...(3)
...(4)
...(5)
Rev. 2.0
12/19/05
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NX2309
8300kHz100uF
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
1.42H
=µ
7m560F0.25us
2
(0.25us)
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m3.4A
RIPPLE
6.8mV14.1mV20.9mV
=+=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V
droop
∆V
<
@step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the overshoot when load from high load to light load with a
DI
transient load, if assuming the bandwidth of
STEP
system is high enough, the overshoot can be estimated as the following equation.
VESRI
overshootstep
2LC
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected out-
3.4A
××
STEP
V
OUT
××
OUT
...(6)
...(7)
...(8)
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤ is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 5A load step.
If the OSCON 4SEPC560M (560uF, 7mohm
ESR) is used, the crticial inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
L
crit
7m560F1.8V
Ω×µ×
5A
The selected inductor is 1.5uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitor is
LI
×∆
step
τ=−×
V
OUT
1.5H5A
µ×
=−Ω×µ=
1.8V
ESRI
×∆
N
7m5A1.8V
=+×
0.35
=
Estep
=+×τ
V2LCV
∆×××∆
Ω×
100mV21.5H560F100mV
ESRC
EE
V
OUT
tranEtran
×µ×µ×
2
Rev. 2.0
12/19/05
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NX2309
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we choose N=1.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should
be chosen.
1
×π××
2RC
42
1
×π×+×
2(RR)C
233
1
×π××
2RC
33
1
×
CC
4
CC
12
+
12
×π××
2R
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time,
C2
Zf
C1
R4
Zin
Vout
R3
R2
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev. 2.0
12/19/05
C3
Fb
gm
Ve
R1
Vref
Figure 3 - Type III compensator using
transconductance amplifier
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NX2309
21.5uH560uF
27m560uF
==Ω
R=8k
=(-)
210k5.5kHz40.6kHz
=2.5nF
=560uF
×π×××Ω
20.755.5kHz5.36k
25.36k150kHz
Case 1: FLC<FO<F
(for most ceramic or low
ESR
ESR POSCAP, OSCON)
power stage
LC
F
Gain(db)
40dB/decade
loop gain
ESR
F
20dB/decade
compensator
F
Z1 Z2
F
F
O
F
F
P1
P2
Figure 4 - Bode plot of Type III compensator
(FLC<FO<F
ESR
)
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<F
and FO<=1/10~1/5Fs is shown as the
ESR
following steps.
1. Calculate the location of LC double pole F
and ESR zero F
ESR
.
LC
2. Set R2 equal to 10kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
10k0.8V
×
Choose R1=8.06kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
111
C=(-)
3
×π×
2RFF
×π×Ω
×
2z2p1
111
×
, calculate C
ESR
Choose C3=2.7nF.
4. Calculate R4 with the crossover frequency at 1/
10~ 1/5 of the switching frequency. Set FO=30kHz.
V2FL
OSCO
R=C
4out
VC
1.1V230kHz1.5uH
12V2.7nF
=5.38k
×π××
××
in3
×π××
××
Ω
Choose R4=5.36kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
×π××
2FR
Z14
1
=
C
2
=
=
7.1nF
Choose C2=6.8nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
3.
1
OUTOUT
1
=
F
LC
×π××
2LC
=
×π××
=
5.5kHz
=
F
ESR
40.6kHz
Rev. 2.0
12/19/05
×π××
2ESRC
=
×π×Ω×
=
1
OUT
1
=
C
1
=
=
197pF
1
×π××
2RF
4P2
1
×π×Ω×
Choose C1=200pF.
7. Calculate R3 by equation (13) with Fp1 =F
ESR
.
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NX2309
240.6kHz2.5nF
22.2uH2000uF
215m2000uF
==Ω
R=12k
=(-)
215k1.8kHz5.3kHz
=2.4nF
25.3kHz2.7F
×π××Ω×Ω
ΩΩ+Ω
1.1V230kHz2.2uH15k11k
12V15m15k11k
×π×××Ω
20.751.8kHz16k
1
×π××
2FC
P13
1
×π××
=
R
3
=
=Ω
1.45k
Choose R3 =1.43kΩ.
Case 2: FLC<F
(for electrolytic capacitors)
ESR<FO
power stage
LC
F
F
ESR
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
F
Z1 Z2
F
P1
F
F
F
O
P2
Figure 5 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here two SANYO MV-WG1000
with 30 mΩ is chosen as output capacitor, output inductor
is 2.2uH. See figure 18.
1. Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
1.8kHz
=
F
ESR
2ESRC
=
=
5.3kHz
1
×π××
OUT
1
×π×Ω×
2. Set R2 equal to 15kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
15k0.8V
×
Choose R1=12kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
ESR
4. Calculate C3 .
111
C=(-)
3
×π×
2RFF
×π×Ω
×
2z2p1
111
×
Choose C3=2.7nF.
5. Calculate R3 .
1
×π××
2FC
P13
1
×π××
=
R
3
=
=Ω
11.1k
Choose R3 =11kΩ.
6. Calculate R4 with FO=30kHz.
V2FLRR
OSCO23
R=
4
VESRRR
=
=16k
×π×××
××
in23
+
××
Ω
Choose R4=16kΩ.
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
×π××
Z14
1
=
C
2
2FR
=
=
4.2nF
Choose C2=4.7nF.
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
.
Rev. 2.0
12/19/05
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NX2309
Gain= ... (15)
F= ... (16)
F ... (17)
216k150kHz
=
C
1
2RF
=
=
66pF
1
×π××
4P2
1
×π×Ω×
Choose C1=68pF.
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<F
Case 1:
RC circuit as shown in figure 14. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise.
the compensator of transconductance amplifier must
satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The
following equations show the compensator pole zero location and constant gain.
<<FO<=1/10~1/5F
ESR
s.
Type II compensator can be realized by simple
To achieve the same effect as voltage amplifier,
R
3
R
2
1
z
2RC
×π××
31
≈
p
1
2RC
×π××
32
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
Z
LC
F
ESR
P
F
F
O
Figure 6 - Bode plot of Type II compensator
C2
Vout
R3
C1
R2
Fb
Ve
R1
Vref
Figure 7 - Type II compensator with
transconductance amplifier(case 1)
Rev. 2.0
12/19/05
The following parameters are used as an example for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure
19. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.
1.Calculate the location of LC double pole F
and ESR zero F
ESR
.
LC
11
Page 12
NX2309
21.5uH4500uF
26.33m4500uF
××Ω
=10k
=37.2k
237.4k0.751.94kHz
p
F
37.4k150kHz
Gain=gR ... (18)
F= ... (19)
F ... (20)
22.2uH1360uF
=
F
LC
×π××
2LC
=
1
OUTOUT
1
×π××
=
1.94kHz
=
F
ESR
2ESRC
=
=
5.6kHz
2.Set crossover frequency FO=30kHz>>F
1
×π××
OUT
1
×π×Ω×
ESR
.
3. Set R2 equal to10kΩ. Based on output voltage,
using equation 21, the final selection of R1 is 20kΩ.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCO
32
VESR
in
1.1V230kHz1.5uH
12V6.33m
×π××
××
×π××
Ω
Ω
Choose R3 =37.4kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
Case 2:
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 15. R
and C1 introduce a zero to cancel the double pole effect.
C2 introduces a pole to suppress the switching noise.
The following equations show the compensator pole zero
location and constant gain.
R
1
××
m3
R+R
12
1
z
2RC
×π××
≈
p
2RC
31
1
×π××
32
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C2
C1
3
C=
1
=
1
×π××
2RF
3z
1
×π×Ω××
=2.9nF
Choose C1=2.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
π××
RF
3s
1
π×Ω×
=57pF
Choose C2=56pF.
Figure 8 - Type II compensator with
transconductance amplifier(case 2)
The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V,
output inductor is 2.2uH, output capacitors are two 680uF
with 41mΩ electrolytic capacitors. See figure 20.
1.Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
2.9kHz
Rev. 2.0
12/19/05
12
Page 13
NX2309
220.5m1360uF
1220.5m2mA/V
22.87k0.752.9kHz
p
F
2.87k150kHz
OUT
REF
2REF
OUT REF
IID1-D
1
×π××
OUT
1
×π×Ω×
=
F
ESR
2ESRC
=
=
5.7kHz
2.Set R2 equal to10kΩ. Using equation 18, the fi-
nal selection of R1 is 4.7kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1.1V230kHz2.2uH1
=
=2.9k
Choose R
5. Calculate C1 by setting compensator zero F
×π××
×××
inESRmREF
×π××
××
2.5V
×
0.8V
1
Ω
Ω
=2.87kΩ.
3
Z
at 75% of the LC double pole.
C=
1
=
1
×π××
2RF
3z
1
×π×Ω××
=25nF
Choose C1=27nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
=369pF
1
π××
RF
3s
1
π×Ω×
Choose C2=390pF.
Output Voltage Calculation
Output voltage is set by reference voltage and ex-
ternal voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation applies to figure 9, which shows the relationship between
V ,
V and voltage divider..
Vout
R2
Fb
R1
Vref
Figure 9 - Voltage divider
RV
R=
1
×
V-V
...(21)
where R2 is part of the compensator, and the
value of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
=××
RMSOUT
V
OUT
D
=
V
IN
VIN = 12V, VOUT=1.8V, IOUT=10A, using equation
(19), the result of input RMS current is 3.6A.
For higher efficiency, low ESR capacitors are
recommended.
One Sanyo OS-CON 16SVP180M 16V 180uF
20mΩ with 3.64A RMS rating are chosen as input bulk
capacitors.
...(22)
Rev. 2.0
12/19/05
13
Page 14
NX2309
×−××
P=I(1D)RK
SWINOUTSWS
PVITF
=××××
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
I240mV/R
I17A
RDSONLDOINLDOOUTLOAD
=−=Ω
(1.8V1.2V)2A1.2W
Power MOSFETs Selection
The NX2309 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used.
They have the following parameters: VDS=30V, I
=75A,R
loss:conduction loss, switching loss.
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3706 datasheet. Conduction
loss should not exceed package rating or overall system thermal budget.
conduction at the switching transition. The total
switching loss can be approximated.
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Swithing loss PSW is frequency
dependent.
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
DSON
=9mΩ,Q
GATE
=23nC.
There are two factors causing the MOSFET power
Conduction loss is simply defined as:
2
P=IDRK
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
×××
2
...(23)
+
Switching loss is mainly caused by crossover
1
2
...(24)
Also MOSFET gate driver loss should be consid-
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2309, the current limit is decided by
the R
FET is on, and the voltage on SW pin is below 240mV,
D
of the low side mosfet. When synchronous
DSON
the over current occurs. The over current limit can be
calculated by the following equation.
=
SETDSON
The MOSFET R
is calculated in the worst case
DSON
situation, then the current limit for MOSFET IRFR3706
is
240mV240mV
===
SET
R1.49m
DSON
×Ω
LDO Selection Guide
NX2309 offers a LDO controller. The selection of
MOSFET to meet LDO is more straight forward. The
selection is that the Rdson of MOSFET should meet the
dropout requirement. For example.
V
=1.8V
LDOIN
V
I
The maximum Rdson of MOSFET should be
R(VV)I
Most of MOSFETs can meet the requirement. More
important is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as
P(VV)I
LOSSLDOINLDOOUTLOAD
Select IR MOSFET IRFR3706 with 9mΩ R
sufficient.
=1.2V
LDOOUT
=2A
Load
=−×
(1.8V1.2V)/2A0.3
=−×
=−×=
DSON
is
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
side gate source voltage.
Rev. 2.0
12/19/05
...(25)
is the low
LGS
LDO Compensation
The diagram of LDO controller including VCC regu-
lator is shown in above figure 9. For low frequency ca-
14
Page 15
NX2309
C=
2FR1+gESR
C= =155pF
×Ω
5k0.8V/(1.2V0.8)10k
=Ω×−=Ω
pacitor such as electrolytic, POSCAP, OSCON, etc, The
compensation parameter can be calculated as follows.
gESR
C
1
×π×××
Of1m
×
m
×
where FO is the desired loop gain.
LDO input
+
Vref
R
f1
ESR
Co
Rload
R
f2
Rc Cc
Figure 10 - NX2309 LDO controller.
Typically, FO has to be higher than zero caused by
ESR. FO is typically around several tens kHz to a few
hundred kHz. For this example, we select Fo=100kHz.
gm is the forward trans-conductance of MOSFET.
For IRFR3706, gm=53.
Select Rf1=5kohm.
Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.
C
15318m
2100kHz5k1+5318m
×π××Ω×Ω
×
Choose CC=150pF.
For electrolytic or POSCAP, RC is typically selected
to be zero.
Rf2 is determined by the desired output voltage
RRV/(VV)
=×−
f2f1REFLDOOUTREF
Choose Rf2=10kΩ.
Current Limit for LDO
Current limit of LDO is achieved by sensing the
LDO feedback voltage. When LDO_FB pin is below 0.4V,
the IC goes into hiccup mode. The IC will turn off all the
channel for 2048 cycles and start to restart system again.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
Rev. 2.0
12/19/05
15
Page 16
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2309
Rev. 2.0
12/19/05
16
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