Datasheet nx2308ds Datasheets

NEXSEM

SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER

NX2308

ADVANCE DATA SHEET

Pb Free Product

DESCRIPTION

The NX2308 controller IC is a compact synchronous Buck controller IC designed for step down DC to DC converter applications. The NX2308 controller is optimized to convert single supply 12V bus voltage to as low as

0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 9V where internal digital soft starts get initiated to ramp up output. The NX2308 employs loss-less current limiting followed by HICCUP feature. Other features includes: 12V gate drive capability , Converter Shutdown by pulling COMP pin to Gnd, Adaptive dead band control.

Vin

+12V

C4 100uF

R7

10

D1 1N4148

FEATURES

n 12V Gate Driver n Bus voltage operation from 9V to 15V n Hiccup current limit by sensing Rdson of

Synchronous MOSFET

n Internal 300kHz n Internal Digital Soft Start Function n Adaptive deadband Control n Shut Down via pulling COMP pin n Pb-free and RoHS compliant

APPLICATIONS

n Graphic Card on board converters n Vddq Supply in mother board applications n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n Set Top Box and LCD Display

TYPICAL APPLICATION

L2 1uH

C5

1uF

Cin

180uF

HI=SD

M3

C7

100pF

C7 1uF

5.6nF

C3 1uF

R4

10.2k

C2

6

5VREG

8

COMP

7

FB

5

BSTVcc

NX2308

Gnd

1

3

Hdrv

SW

OCP

Ldrv

C6

0.1uF

2

10

9

4

4k

M1

L1 2.2uH

R5

M2

R1

1.1k

C1

3.9nF

R3

8k

Co

2 x 470uF

R2

10k

Vout +1.8V 10A

Figure1 - Typical application of NX2308

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free NX2308CUTR 0 to 70oC MSOP - 10L 300kHz Yes NX2308CMTR 0 to 70oC MLPD - 10L 300kHz Yes

Rev. 2.0 12/19/05

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1

NEXSEM

θ≈200/

CW

θ≈52/

CW

REF

CC

Supply Current

NX2308

ABSOLUTE MAXIMUM RATINGS

Vcc to PGND & BST to SW voltage .................... -0.3V to 16V

BST to PGND Voltage ...................................... -0.3V to 35V

SW to PGND .................................................... -2V to 35V

All other pins .................................................... -0.3V to 6.5V

Storage Temperature Range ............................... -65oC to 150oC

Operating Junction Temperature Range ............... -40oC to 125oC

ESD Susceptibility ........................................... 2kV

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

10-LEAD PLASTIC MSOP 10-LEAD PLASTIC MLPD

JA

o

JA

BST

HDrv

Gnd

LDrv

Vcc

1 2 3 4 5

10

9 8

7 6

SW OCP Comp FB 5VReg

BST

HDrv

NC

LDrv VCC

1

2 3

4 5

Gnd (PAD)

10

9 8 7

6

SW OCP

COMP

FB 5VReg

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =12V, V values refer to TA = 25oC.

PARAMETER SYM Test Condition Min TYP MAX Units

Reference Voltage

Ref Voltage V Ref Voltage line regulation 10V<=VCC<=14V 0.2 %

Supply Voltage(Vcc)

VCC Voltage Range V V

CC

(Static) VCC Supply Current

(Dynamic)

Supply Voltage(V

V

Voltage Range V

BST

V

Supply Current V

BST

Under Voltage Lockout

VCC-Threshold VCC_UVLO VCC Rising VCC-Hysteresis VCC_Hyst VCC Falling 0.3 V

BST)

ICC (Static) mAOutputs not switching 5

I

CC

(Dynamic)

to V

BST

(Dynamic)

CL=3300PF 17 mA

SW

CL=3300PF 12 mA

BST-VSW

=12V, and TA = 0 to 70oC. Typical

7 14

0.8

6.6

V

Rev. 2.0 12/19/05

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2

NEXSEM

S

RAMP

Comp SD Threshold

0.2

V

sink

OCP current

40

uA

Ldrv going Low to Hdrv going

NX2308

PARAMETER SYM Test Condition Min TYP MAX Units

Oscillator

Frequency F Ramp-Amplitude Voltage V Max Duty Cycle Min Duty Cycle

Error Amplifiers

Transconductance 2000 umho

Input Bias Current Ib 100 nA

Soft Start

Soft Start time Tss 6.8 mS

High Side Driver (CL=3300pF)

R

Output Impedance , Sinking

Current

Output Impedance , Sinking

Current

Rise Time THdrv(Rise) 10% to 90% 30 ns Fall Time THdrv(Fall) 90% to 10% 20 ns Deadband Time

Low Side Driver (CL=3300pF)

Output Impedance, Sourcing Current

Rise Time TLdrv(Rise) 10% to 90% 30 ns

N

Fall Time TLdrv(Fall) 90% to 10% 20 ns Deadband Time Tdead(H to L)SW going Low to Ldrv going

(Hdrv) I= 200mA 3.6 ohm

source

R

(Hdrv) I=200mA 1 ohm

Tdead(L to

H)

R

(Ldrv) I=200mA 2.2 ohm

source

R

(Ldrv) I=200mA 1 ohm

sink

High, 10% to 10%

300 KHz

1.1 V 94 %

0

50

%

ns50

ns

OCP Adjust

Rev. 2.0 12/19/05

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NEXSEM

PIN DESCRIPTIONS

PIN # PIN SYMBOL PIN DESCRIPTION

Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as

5

1

VCC

BST

possible to and connected to this pin and ground pin. The maximum rating of this pin is 16V.

This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and respected SW pins.

NX2308

10

3

7

8

2 4

9

GND

FB

COMP

SW

HDRV

LDRV

OCP

Power ground. This pin is the error amplifiers inverting input. This pin is connected via resistor

divider to the output of the switching regulator to set the output DC voltage.

This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft start is reset.

This pin is connected to source of high side FET and provide return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold .

High side gate driver output. Low side gate driver output. This pin is connected to the drain of the external low side MOSFET and is the input

of the over current protection(OCP) comparator. An internal current source 40uA is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles.

Rev. 2.0 12/19/05

6

5VREG

Output of internal 5V regulator. An external 0.1uF capacitor is required for stability.

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4

NEXSEM

BLOCK DIAGRAM

NX2308

VCC

5VREG

FB

COMP

Bias Regulator

Bias Generator

START

Digital start Up

0.8V

COMP

0.2V

START

1.25V

0.8V

7.2/6.8V

OSC

ramp

0.6V CLAMP

UVLO

set1

1.3V CLAMP

POR

START

OC

Control Logic

PWM

S

Q

R

Hiccup Logic

OC

OCP comparator

VCC

I

BST

HDRV

SW

LDRV

OCP

Rev. 2.0 12/19/05

GND

Figure 2 - Simplified block diagram of the NX2308

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5

NEXSEM

RIPPLEINS

1

IVF

0.310A12V300kHz

=2.3A

SOUT

==Ω

ESR=8.7m

ERIPPLE

9m2.3A

NX2308

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage VOUT - Output voltage IOUT - Output current DVRIPPLE - Output voltage ripple FS - Switching frequency DIRIPPLE - Inductor current ripple

Design Example

Power stage design requirements: VIN=12V VOUT=1.8V IOUT =10A DVRIPPLE <=20mV DVTRAN<=100mV @ 10A step FS=300kHz

Output Inductor Selection

The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:

V-VV

L=

I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.3, then

L=

OUT

L=1.7uH

OUT

Choose LOUT=2.2uH, then coilcraft inductor DO5010P-222HC is a good choice.

Current Ripple is calculated as

INOUT OUT

OUT

12V-1.8V1.8V1

××

×

××

×

...(1)

V-VV 1

I=

RIPPLE

INOUT OUT

LVF

12V-1.8V1.8V1

2.2uH12V300kHz

××

OUTINS

...(2)

××=

Output Capacitor Selection

Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent series resistance,C

Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected.

For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.

∆

tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP 2R5TPE470M9 with 9mΩ are chosen.

integer. Choose N =2.

desire

If low ESR is required, for most applications, mul-

ESRI

N

=

Number of Capacitor is calculated as

Ω×

=

N

N =1.03

The number of capacitor has to be round up to a

20mV

is the value of output capacitors.

OUT

V 20mV

RIPPLE

∆

I2.3A

RIPPLE

×∆

V

∆

RIPPLE

××

8FC

...(5)

...(3)

...(4)

Rev. 2.0 12/19/05

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6

NEXSEM

8300kHz100uF

tran

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.76H

=µ

9m470F7.97us

2

(7.97us)

NX2308

If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.

For example, one 100uF, X5R ceramic capacitor

with 2mΩ ESR is used. The amount of output ripple is

∆=Ω×+

V2m2.3A

RIPPLE

4.6mV9.6mV14.2mV

Although this meets DC ripple spec, however it needs to be studied for transient requirement.

Based On Transient Requirement

Typically, the output voltage droop during transient is specified as

∆V

During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a DI

transient load, if assuming the bandwidth of

STEP

system is high enough, the overshoot can be estimated as the following equation.

VESRI

where τ is the a function of capacitor,etc.

where

=+=

∆V

<

droop

overshootstep

0ifLL

 

LI

×∆τ=



step



V

OUT



@step load DI

≤

crit

−×≥

2LC

2.3A

××

STEP

V

OUT

××

OUT

...(6)

...(7)

put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and ca-

pacitance is high and transient spec is mostly like to dependent on the ESR

of capacitor.

Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following

ESRI

×∆

N

where

 

sient is 100mV for 10A load step.

ESR) is used, the crticial inductance is given as

 



For example, assume voltage droop during tran-

If the POSCAP 2R5TPE470M9 (470uF, 9mohm

Estep

V2LCV

∆×××∆

tranEtran

0ifLL

LI

×∆τ=

step

V

OUT

ESRCV

L

==

crit

9m470F1.8V

Ω×µ×

≤ is true. In that case, the

V

OUT

≤

crit

−×≥

××

EEOUT

I

∆

step

...(9)

...(10)

10A

The selected inductor is 2.2uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.

number of capacitor is

LI

×∆

step

τ=−×

V

OUT

2.2H10A

µ×

=−Ω×µ=

ESRC

EE

1.8V

ESRCVESRCV

L

crit

where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel.

The above equation shows that if the selected out-

Rev. 2.0 12/19/05

××××

==

II

∆∆

stepstep

...(8)

ESRI

N

=+×τ

9m10A1.8V

Ω×

=+×

100mV22.2H470F100mV

1.44

=

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×∆

Estep

V2LCV

∆×××∆

tranEtran

×µ×µ×

V

2OUT

7

NEXSEM

F ...(11)

F ...(12)

F ...(13)

F ...(14)

OUT minin1

V1gZZ/R

f

OUT in

Z

VZ

−

NX2308

The number of capacitors has to satisfied both ripple and transient requirement. Overall, we choose N=2.

It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters.

Compensator Design

Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen.

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator for

transconductance amplifier is given by:

V 1gZ

e mf

For the voltage amplifier, the transfer function of compensator is

the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time,

=

V

e

=

To achieve the same effect as voltage amplifier,

Zin

R3

1

2RC

×π××

42

1

2(RR)C

×π×+×

2RC

×π××

2R

×π××

+×+

Vout

233

1

33

1

CC

12

4

CC

12

−×

× +

Zf

C1

C2

R4

R2

A. Type III compensator design

For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.

Rev. 2.0 12/19/05

C3

Figure 3 - Type III compensator using

transconductance amplifier

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R1

Fb

Vref

gm

Ve

8

NEXSEM

22.2uH940uF

24.5m940uF

=940uF

20.753.5kHz10.2k

×π×××Ω

210.2k150kHz

237.6kHz3.9nF

==Ω

R=8k

=(-)

210k3.5kHz37.6kHz

Case 1: FLC<FO<F

power stage

Gain(db)

ESR

LC

F

40dB/decade

NX2308

× Ω×

RV 10k0.8V

2REF

1

frequency at 1/10~ 1/5 of the switching frequency. Set FO=25kHz.

V-V1.8V-0.8V

OUT REF

Choose R1=8kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

4. Calculate R4 and C3 with the crossover

ESR

.

loop gain

ESR

F

20dB/decade

compensator

F

Z1

F

Z2

Figure 4 - Bode plot of Type III compensator

(FLC<FO<F

Typical design example of type III compensator in which t he crossover frequency is selected as FLC<FO<F following steps.

1. Calculate the location of LC double pole F

and ESR zero F

and FO<=1/10~1/5Fs is shown as the

ESR

.

ESR

F

=

LC

2LC

×π××

=

O

F

ESR

1

OUTOUT

1

F

P1

F

)

P2

LC

×π××

3.5kHz

=

C=(-)

111

3

2RFF

×π×

×

2z2p1

111

×

×π×Ω

=4.1nF

V2FL

R=C

4out

VC

1.5V225kHz2.2uH

×π××

OSCO

××

in3

×π××

××

12V3.9nF

=10.4k

Choose C3=3.9nF, R4=10.2k.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

C

2

=

5.95nF

Choose C2=5.6nF.

6. Calculate C1 by equation (14) with pole Fp2 at

half the switching frequency.

C

1

104pF

Choose C1=100pF.

7. Calculate R3 by equation (13).

Ω

=

1

2FR

×π××

Z14

=

1

2RF

×π××

4P2

×π×Ω×

=

1

F

ESR

=

2ESRC

=

1

×π××

OUT

1

×π×Ω×

37.6kHz

=

2. Set R2 equal to10k Ω.

Rev. 2.0 12/19/05

R

=

3

=

1.1k

=Ω

Choose R3 =1.1kΩ.

www.nexsem.com

1

2FC

×π××

P13

1

×π××

9

NEXSEM

22.2uH1500uF

213m1500uF

==Ω

R=12k

=(-)

215k2.77kHz8.16kHz

28.16kHz2.7nF

1.5V230kHz2.2uH15k7.32k

12V13m15k7.32k

×π××Ω×Ω

ΩΩ+Ω

20.752.77kHz19.6k

×π×××Ω

219.6k150kHz

NX2308

Case 2: FLC<F

power stage

Gain(db)

loop gain

compensator

F

Z1

ESR<FO

LC

F

ESR

F

Z2

40dB/decade

O

F

P1

F

20dB/decade

F

P2

2. Set R2 equal to 15k Ω.

× Ω×

RV 15k0.8V

2REF

1

V-V1.8V-0.8V

OUT REF

Choose R1=12kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

4. Calculate C3 .

C=(-)

111

3

2RFF

×π×

×

2z2p1

111

×

×π×Ω

=2.5nF

Choose C3=2.7nF.

5. Calculate R3 .

1

2FC

×π××

P13

1

R

=

3

=

×π××

7.22k

=Ω

Choose R3 =7.32kΩ.

6. Calculate R4 with FO=30kHz.

ESR

.

Figure 5 - Bode plot of Type III compensator

(FLC<F

If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which t he crossover frequency is selected as FLC<F as the following steps. Here one SANYO MV-WG1500 with 13 mΩ is chosen as output capacitor.

1. Calculate the location of LC double pole F

and ESR zero F

F

=

LC

=

ESR<FO

.

ESR

1

2LC

×π××

OUTOUT

)

ESR<FO

and FO<=1/10~1/5Fs is shown

1

LC

×π××

2.77kHz

=

F

=

ESR

2ESRC

=

1

×π××

OUT

1

×π×Ω×

8.16kHz

=

V2FLRR

OSCO23

R=

4

VESRRR = =19.6k

Choose R4=19.6kΩ.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

C

2

2.9nF

Choose C2=2.7nF.

6. Calculate C1 by equation (14) with pole Fp2 at

half the switching frequency.

C

1

54pF

Choose C1=56pF.

×π×××

××

in23

+

××

Ω

=

1

2FR

×π××

Z14

1

=

1

2RF

×π××

4P2

1

×π×Ω×

=

Rev. 2.0 12/19/05

www.nexsem.com

10

NEXSEM

Gain= ... (15)

F= ... (16)

F ... (17)

21.5uH4500uF

26.33m4500uF

××Ω

=10k

B. Type II compensator design

If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system.

For this type of compensator, FO has to satisfy FLC<F

<<FO<=1/10~1/5F

ESR

s.

R2

R1

Vout

Fb

R3

NX2308

C2

C1

Ve

Case 1:

Type II compensator can be realized by simple RC circuit as shown in figure 7. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise.

To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must

satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The following equations show the compensator pole zero location and constant gain.

R

3

R

2

1

z

2RC

×π××

31

≈

p

1

2RC

×π××

32

power stage

Vref

Figure 7 - Type II compensator with transconductance amplifier(case 1)

The following parameters are used as an example for type II compensator design, three 1500uF with 19mohm Sanyo electrolytic CAP 6MV1500WGL are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure

19. The power stage information is that: VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.

1.Calculate the location of LC double pole F

and ESR zero F

=

F

LC

2LC

=

.

ESR

1

×π××

OUTOUT

1

LC

×π××

=

1.94kHz

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

F

Z LCFESR

F

Figure 6 - Bode plot of Type II compensator

Rev. 2.0 12/19/05

P

O

F

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F

ESR

=

×π××

2ESRC

=

1

OUT

1

×π×Ω×

=

5.6kHz

2.Set crossover frequency FO=30kHz>>F

3. Set R2 equal to10k Ω. Based on output voltage,

using equation 21, the final selection of R1 is 20k Ω.

4.Calculate R3 value by the following equation.

V2FL

R=R

OSCO

32

VESR

in

1.1V230kHz1.5uH 12V6.33m

=37.2k

Choose R3 =37.4k Ω.

×π××

××

×π××

Ω

ESR

.

11

NEXSEM

Gain=gR ... (18)

F= ... (19)

F ... (20)

237.4k0.751.94kHz

p

F

37.4k150kHz

NX2308

5. Calculate C1 by setting compensator zero F

at 75% of the LC double pole.

C=

1

= =2.9nF

Choose C1=2.7nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

C=

2

= =57pF

Choose C2=56pF.

Case 2:

Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 9. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.

1

×π××

2RF

3z

1

×π×Ω××

1

π××

RF

3s

1

π×Ω×

R

1

××

m3

R+R

12

Z

1

z

2RC

×π××

≈

p

31

1

2RC

×π××

32

power stage

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

F

Z LCFESR

F

Figure 8 - Bode plot of Type II compensator

P

O

F

Vout

R2

Fb

gm

R1

Vref

Ve

R3

C2

C1

Rev. 2.0 12/19/05

Figure 9 - Type II compensator with transconductance amplifier

For this type of compensator, FO has to satisfy

FLC<F

tor design. Input voltage is 12V, output voltage is 3.3V, output inductor is 1.5uH, output capacitors are two 680uF with 41mΩ electrolytic capacitors.

and ESR zero F

<<FO<=1/10~1/5F

ESR

The following is parameters for type II compensa-

1.Calculate the location of LC double pole F

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ESR

s.

LC

.

12

NEXSEM

21.5uH1360uF

220.5m1360uF

1220.52mA/V

23.57k0.753.5kHz

p

F

3.57k300kHz

OUT

REF

V

2REF

OUT REF

IID1-D

NX2308

1

OUTOUT

1

F

=

LC

2LC

×π××

=

×π××

3.5kHz

=

1

×π××

OUT

1

F

ESR

=

2ESRC

=

×π×Ω×

5.7kHz

=

2.Set R2 equal to10.2k Ω. Using equation 21, the

final selection of R1 is 3.24k Ω.

3. Set crossover frequency at 1/10~ 1/5 of the

swithing frequency, here FO=30kHz.

4.Calculate R3 value by the following equation.

V2FL R+R

OSCO 12

R=

3

VRgR

1.5V230kHz1.5uH1

=

=3.55k

Choose R3 =3.57k Ω.

5. Calculate C1 by setting compensator zero F

at 75% of the LC double pole.

C=

= =16.9nF

Choose C1=15nF.

6. Calculate C2 by setting compensator pole

at half the swithing frequency.

×π××

×××

inESRm1

×π××

××

10.2k+3.24k

×

ΩΩ

3.24k

Ω

1

Ω

1

2RF

×π××

3z

1

×π×Ω××

Output Voltage Calculation

Output voltage is set by reference voltage and ex-

ternal voltage divider. The reference voltage is fixed at

0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation and picture show the relationship between

V ,

where R2 is part of the compensator, and the

value of R1 value can be set by voltage divider.

Choose R2=15kΩ, to set the output voltage at

1.8V, the result of R1 is 12kΩ.

Z

Input Capacitor Selection

Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated

as:

and voltage divider..

Vout

R2

Fb

R1

Vref

Figure 10 - Voltage divider

RV

R=

1

×

V-V

...(21)

C=

2

= =297pF

Choose C1=330pF.

Rev. 2.0 12/19/05

1

RF

π××

3s

π×Ω×

=××

RMSOUT

V

OUT

D

1

VIN = 12V, VOUT=1.8V, IOUT=10A, using equation (19), the result of input RMS current is 3.6A.

recommended.

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=

V

IN

For higher efficiency, low ESR capacitors are

...(22)

13

NEXSEM

P=I(1D)RK

×−××

SWINOUTSWS

PVITF

=××××

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

SWLDSON

IR+V

IIR/R

===Ω

R3.375k

NX2308

One Sanyo OS-CON 16SVP180M 16V 180uF 20mΩ with 3.64A RMS rating are chosen as input bulk capacitors.

Power MOSFETs Selection

The NX2305 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter

efficiency. In this design example, two IRFR3709Z are used. They have the following parameters: VDS=30V,R

=6.5mΩ,Q

GATE

=17nC.

There are two factors causing the MOSFET power loss:conduction loss, switching loss.

Conduction loss is simply defined as:

P=IDR

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

2

×××

2

K

+

...(23)

where the R DS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to IRFR3709Z datasheet . Conduc- tion loss should not exceed package rating or overall system thermal budget.

Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.

1 2

...(24)

where IOUT is output current, TSW is the sum of T and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent.

Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as:

DSON

...(25)

where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and V

is the low

LGS

side gate source voltage.

This power dissipation should not exceed maximum power dissipation of the driver device.

Over Current Limit Protection

Over current protection for NX2308 is achieved by sensing current through the low side MOSFET. An internal current source of 40uA flows through an external resistor connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as

V=-IR×

The voltage at pin OCP is given as

×

OCPOCPSW

When the voltage is below zero, the over current occurs as shown in figure.

vbus

OCP

I

40uA

OCP comparator

OCP

SW

OCP

R

Figure 11 - Over current protection

The over current limit can be set by the following equation

=×

SETOCPOCPDSON

If the MOSFET R

=9mΩ, and the current limit

DSON

is set at 15A, then

× ×Ω

R

IR 15A9m

SETDSON

OCP

Choose R

I40uA

OCP

=4kΩ

Layout Considerations

The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results.

There are two sets of components considered in

Rev. 2.0 12/19/05

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14

NEXSEM

NX2308

the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended .

Layout guidelines:

1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them.

2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must.

3. The output capacitors should be placed as close as to the load as possible and plane connection is required.

4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible.

5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider.

8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals.

9. All GNDs need to go directly thru via to GND

plane.

10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC.

11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.

Rev. 2.0 12/19/05

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15

Datasheet nx2308ds Datasheets

Specifications and Main Features

Frequently Asked Questions

User Manual