Page 1
NX2307
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER
ADVANCE DATA SHEET
Pb Free Product
DESCRIPTION
The NX2307 controller IC is a compact synchronous Buck
controller IC with 8 lead SOIC8 package designed for
step down DC to DC converter applications. The NX2307
controller is optimized to convert single supply 12V bus
voltage to as low as 0.8V output voltage. Internal UVLO
keeps the regulator off until the supply voltage exceeds
7V where internal digital soft starts get initiated to ramp
up output. The NX2307 employs fixed current limiting
followed by HICCUP feature. Other features includes:
12V gate drive capability , Converter Shutdown by pulling COMP pin to Gnd, Adaptive dead band control.
Vin
HI=SD
+12V
200pF
M3
C7
5.36k
C2
6.8nF
C4
100uF
R4
7
6
C3
1uF
5
Vcc
COMP
FB
R6
10
NX2307
Gnd
D1 MBR0530T1
1
BST
Hdrv
SW
Ldrv
3
FEATURES
n 12V Gate Driver
n Bus voltage operation from 7V to 15V
n Fixed hiccup current limit by sensing Rdson of
Synchronous MOSFET
n Internal 300kHz
n Internal Digital Soft Start Function
n Adaptive deadband Control
n Shut Down via pulling COMP pin
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic Card on board converters
n Vddq Supply in mother board applications
n On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Set Top Box and LCD Display
TYPICAL APPLICATION
L2 1uH
C5
1uF
C6
0.1uF
2
8
4
M1
IRFR3706
L1 1.5uH
M2
IRFR3706
C1
2.7nF
R1
1.43k
Cin
16SVP180M
16V,180uF
R2
10k
Vout
Co
4SEPC560M
560uF,7mohm
+1.8V 10A
Rev. 3.2
06/22/06
R3
8k
Figure1 - Typical application of NX2307
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2307CSTR 0 to 70oC SOIC - 8L 300kHz Yes
1
Page 2
NX2307
θ≈130/
CW
Supply Current
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
8-LEAD PLASTIC SOIC
o
8
SW
7
COMP
6
Fb
5
Vcc
BST
HDrv
Gnd
LDrv
JA
1
2
3
4
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, V
values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
Ref Voltage line regulation 10V<=VCC<=14V 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
V
CC
(Static)
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Voltage Range V
BST
V
Supply Current V
BST
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.3 V
BST)
REF
CC
ICC (Static) mAOutputs not switching 5
I
CC
(Dynamic)
to V
BST
BST
(Dynamic)
CL=3300PF 17 mA
SW
CL=3300PF 12 mA
BST-VSW
=12V, and TA = 0 to 70oC. Typical
7 14
7 14
0.8
6.6
V
V
V
V
Rev. 3.2
06/22/06
2
Page 3
NX2307
Driver(CL=3300pF)
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
Oscillator (Rt)
Frequency F
Ramp-Amplitude Voltage V
Max Duty Cycle
S
RAMP
Min Duty Cycle
Error Amplifiers
Transconductance 2000 umho
Input Bias Current Ib 100 nA
Comp SD threshold 0.2 V
Soft Start
Soft Start time Tss 6.8 mS
High Side
300 KHz
1.1 V
94 %
0
%
R
(Hdrv) I=200mA
source
3.6 ohmOutput Impedance , Sourcing
Current
Output Impedance , Sinking
R
(Hdrv) I=200mA
sink
ohm1
Current
Rise Time THdrv(Rise) 10% to 90% 30 ns
Fall Time THdrv(Fall) 90% to 10% 20 ns
Deadband Time
Tdead(L to
H)
High, 10% to 10%
ns50
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 2.2 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 1 ohm
sink
Current
Rise Time TLdrv(Rise) 10% to 90% 30 ns
N
Fall Time TLdrv(Fall) 90% to 10% 20 ns
50
nsDeadband Time Tdead(H to L)SW going Low to Ldrv going
High, 10% to 10%
Fixed OCP
OCP voltage threshold 240 mV
Rev. 3.2
06/22/06
3
Page 4
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as
5
1
VCC
BST
possible to and connected to this pin and ground pin. The maximum rating of this
pin is 16V.
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF
ceramic capacitor is placed as close as possible to and connected to this pin
and SW pin.
NX2307
3
6
7
8
2
4
GND
FB
COMP
SW
HDRV
LDRV
Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor
divider to the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut down
pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft
start is reset.
This pin is connected to source of high side FETs and provide return path for the
high side driver. It is also used to hold the low side driver low until this pin is
brought low by the action of high side turning off. LDRV can only go high if SW is
below 1V threshold .
High side gate driver output.
Low side gate driver output.
Rev. 3.2
06/22/06
4
Page 5
BLOCK DIAGRAM
NX2307
VCC
FB
COMP
Bias
Regulator
Bias
Generator
START
Digital
start Up
0.8V
COMP
0.2V
START
1.25V
0.8V
6.6/6.3V
ramp
OSC
0.6V
CLAMP
UVLO
1.3V
CLAMP
POR
START
OC
Control
Logic
PWM
S
Q
R
Hiccup Logic
OC
OCP
comparator
VCC
240mV
BST
HDRV
SW
LDRV
Rev. 3.2
06/22/06
GND
Figure 2 - Simplified block diagram of the NX2307
5
Page 6
NX2307
R2
10
C2
1u
U1
5
VCC
HDRV
NX2307-SOIC8
LDRV
GND
BST
SW
1
2
3
4
5
6
7
8
9
10
234
J12V
4
12V
J1
3.3V
3.3V
GND
5V
GND
5V
GND
PWR_OK
5VSB
12V
C8
GND
GND12V
GND
PS_ON
GND
GND
GND
C9
OP
3.3V
-12V
-5V
5V
5V
1
23
OUT
11
12
13
14
15
16
17
18
19
20
1
C12
.1u
VOUT
1
2
JVOUT
5
R24
1k
234
BUS
1
2
R15
2k
AK
PWR
C6
100u/16V
12V
L1
DO1608C-102
C5B
D1
MBR0530T1
1
C4
0.1u
2
8
4
3
R11
OP
R3
0
R12
OP
R4
0
VD
1u
C5A
16SVP180M
M1
IRF3706
SW
M2
IRF3706
OP
567
8
JSW
M3
123
OP
OP
D3
4
M4
1
5
(1.5uH, 4m)
DO5010P-152HC
L2
R20
4SEPC560M
10
C19
470pF
Rev. 3.2
06/22/06
*
FB
COMP
SW
R7
1.43k
R8
10k
C13
2700p
R10
OP
OP
R5
6
OP
C20
C7
6800p
R9
8.06k
R13
OP
C11
OP
R6
5.49k
7
C10
200p
Figure 3- Demo board schematic based on ORCAD
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Bill of Materials
Item Quantity Reference Value Manufacture
1 2 VOUT,BUS CON2
2 2 C5B,C2 1u
3 1 C4 0.1u
4 1 C5A 16SVPA180M SANYO
5 1 C6 100u/16V
6 1 C7 6800p
7 1 C8 4SEPC560M SANYO
8 11 M3,D3,M4,R5,C9,R10,C10, OP
R11,C11,R12,R13
9 1 C12 .1u
10 1 C13 2700p
11 1 C19 470pF
12 1 C10 200p
13 1 D1 MBR0530T1
14 2 JVOUT,JSW SCOPE TP Tektronics
15 1 J1 ATX con
16 1 J12V ATX-12V
17 1 L1 DO3316P-102 Coilcraft
18 1 L2 DO5010P-152HC Coilcraft
19 2 M1,M2 IRF3706 International Rectifier
20 1 PWR LED
21 2 R2,R20 10
22 2 R3,R4 0
23 1 R6 5.49k
24 1 R7 1.43k
25 1 R8 10k
26 1 R9 8.06k
27 1 R15 2k
28 1 R24 1k
29 1 U1 NX2307-SOIC8 NEXSEM INC.
NX2307
Rev. 3.2
06/22/06
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Page 8
Demoboard waveforms
NX2307
Figure 4 - Output ripple for power output
Figure 6 - Start up time
Figure 5 - Output voltage transient response for
load current 0A-5A
Figure 7 - Prebias startup
Figure 8 - Shutdown via pulling comp pin down
Rev. 3.2
06/22/06
Figure 9 - Short circuit protection
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Page 9
NX2307
RIPPLEINS
1
IVF
0.410A12V300kHz
=3.4A
SOUT
==Ω
ESR=7.3m
ERIPPLE
7m3.4A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VIN=12V
VOUT=1.8V
IOUT =10A
DVRIPPLE <=25mV
DVTRAN<=100mV @ 5A step
FS=300kHz
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.4, then
L=
OUT
L=1.3uH
OUT
Choose LOUT=1.5uH, then coilcraft inductor
DO5010P-152HC is a good choice.
Current Ripple is calculated as
INOUT OUT
OUT
××
×
12V-1.8V1.8V1
×
××
...(1)
V-VV
I=
RIPPLE
INOUT OUT
LVF
12V-1.8V1.8V1
1.5uH12V300kHz
××
OUTINS
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the amount
of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent series resistance,C
is the value of output capacitors.
OUT
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, OSCON are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
desire
V
RIPPLE
∆
I3.4A
RIPPLE
25mV
∆
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 25mV output ripple, OSCON
4SEPC560M with 7mΩ are chosen.
ESRI
N
=
∆
×∆
V
RIPPLE
Number of Capacitor is calculated as
25mV
Ω×
=
N
N =0.95
The number of capacitor has to be round up to a
integer. Choose N =1.
RIPPLE
××
8FC
...(3)
...(4)
...(5)
Rev. 3.2
06/22/06
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Page 10
NX2307
8300kHz100uF
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
1.42H
=µ
7m560F0.25us
2
(0.25us)
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m3.4A
RIPPLE
6.8mV14.1mV20.9mV
=+=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V
droop
∆V
<
@step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the overshoot when load from high load to light load with a
DI
transient load, if assuming the bandwidth of
STEP
system is high enough, the overshoot can be estimated as the following equation.
VESRI
overshootstep
2LC
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected out-
3.4A
××
STEP
V
OUT
××
OUT
...(6)
...(7)
...(8)
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤ is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 5A load step.
If the OSCON 4SEPC560M (560uF, 7mohm
ESR) is used, the crticial inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
L
crit
7m560F1.8V
Ω×µ×
5A
The selected inductor is 1.5uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitor is
LI
×∆
step
τ=−×
V
OUT
1.5H5A
µ×
=−Ω×µ=
1.8V
ESRI
×∆
N
=+×
0.35
=
Estep
=+×τ
7m5A1.8V
V2LCV
∆×××∆
Ω×
100mV21.5H560F100mV
ESRC
EE
V
OUT
tranEtran
×µ×µ×
2
Rev. 3.2
06/22/06
10
Page 11
NX2307
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we choose N=1.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should
be chosen.
1
×π××
2RC
42
1
×π×+×
2(RR)C
233
1
×π××
2RC
33
1
×
CC
4
CC
12
+
12
×π××
2R
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier, the
compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.
C2
Zf
C1
R4
Zin
Vout
R3
R2
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev. 3.2
06/22/06
C3
Fb
gm
R1
Vref
Figure 10 - Type III compensator using
transconductance amplifier(C1 can also be
connected from comp pin to ground)
Ve
11
Page 12
NX2307
21.5uH560uF
27m560uF
==Ω
R=8k
=(-)
210k5.5kHz40.6kHz
=2.5nF
=560uF
×π×××Ω
20.755.5kHz5.36k
25.36k150kHz
Case 1: FLC<FO<F
(for most ceramic or low
ESR
ESR POSCAP, OSCON)
power stage
LC
F
Gain(db)
40dB/decade
loop gain
ESR
F
20dB/decade
compensator
F
Z1 Z2
F
F
O
F
F
P1
P2
Figure 11 - Bode plot of Type III compensator
(FLC<FO<F
ESR
)
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<F
and FO<=1/10~1/5Fs is shown as the
ESR
following steps.
1. Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
5.5kHz
2. Set R2 equal to 10kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
10k0.8V
×
Choose R1=8.06kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
111
C=(-)
3
×π×
2RFF
×π×Ω
×
2z2p1
111
×
, calculate C
ESR
Choose C3=2.7nF.
4. Calculate R4 with the crossover frequency at 1/
10~ 1/5 of the switching frequency. Set FO=30kHz.
V2FL
OSCO
R=C
4out
VC
1.1V230kHz1.5uH
12V2.7nF
=5.38k
×π××
××
in3
×π××
××
Ω
Choose R4=5.36kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
×π××
2FR
Z14
1
=
C
2
=
=
7.1nF
Choose C2=6.8nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
=
C
1
=
=
197pF
1
×π××
2RF
4P2
1
×π×Ω×
3.
=
F
ESR
40.6kHz
Rev. 3.2
06/22/06
×π××
2ESRC
=
×π×Ω×
=
1
OUT
1
Choose C1=200pF.
7. Calculate R3 by equation (13) with Fp1 =F
ESR
.
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Page 13
NX2307
240.6kHz2.5nF
22.2uH2000uF
215m2000uF
==Ω
R=12k
=(-)
215k1.8kHz5.3kHz
=2.4nF
25.3kHz2.7F
×π××Ω×Ω
ΩΩ+Ω
1.1V230kHz2.2uH15k11k
12V15m15k11k
×π×××Ω
20.751.8kHz16k
1
×π××
2FC
P13
1
×π××
=
R
3
=
=Ω
1.45k
Choose R3 =1.43kΩ.
Case 2: FLC<F
(for electrolytic capacitors)
ESR<FO
power stage
LC
F
ESR
F
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
F
Z1 Z2
F
P1
F
F
F
O
P2
Figure 12 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is selected
as FLC<F
and FO<=1/10~1/5Fs is shown as the
ESR<FO
following steps. Here two SANYO MV-WG1000 with
30 mΩ is chosen as output capacitor, output inductor is
2.2uH. See figure 18.
1. Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
1.8kHz
=
F
ESR
2ESRC
=
=
5.3kHz
1
×π××
OUT
1
×π×Ω×
2. Set R2 equal to 15kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
15k0.8V
×
Choose R1=12kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
ESR
4. Calculate C3 .
111
C=(-)
3
×π×
2RFF
×π×Ω
×
2z2p1
111
×
Choose C3=2.7nF.
5. Calculate R3 .
1
×π××
2FC
P13
1
×π××
=
R
3
=
=Ω
11.1k
Choose R3 =11kΩ.
6. Calculate R4 with FO=30kHz.
V2FLRR
OSCO23
R=
4
VESRRR
=
=16k
×π×××
××
in23
+
××
Ω
Choose R4=16kΩ.
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
×π××
2FR
Z14
1
=
C
2
=
=
4.2nF
Choose C2=4.7nF.
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
.
Rev. 3.2
06/22/06
13
Page 14
NX2307
Gain= ... (15)
F= ... (16)
F ... (17)
216k150kHz
=
C
1
2RF
=
=
66pF
1
×π××
4P2
1
×π×Ω×
Choose C1=68pF.
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<F
Case 1:
RC circuit as shown in figure 14. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise.
compensator of transconductance amplifier must satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The
following equations show the compensator pole zero location and constant gain.
<<FO<=1/10~1/5F
ESR
s.
Type II compensator can be realized by simple
To achieve the same effect as voltage amplifier, the
R
3
R
2
1
z
2RC
×π××
31
≈
p
1
2RC
×π××
32
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
F
LC
Z
ESR
P
F
F
O
Figure 13 - Bode plot of Type II compensator
C2
Vout
R3
C1
R2
Fb
Ve
R1
Vref
Figure 14 - Type II compensator with
transconductance amplifier(case 1)
Rev. 3.2
06/22/06
The following parameters are used as an example for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure
19. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.
1.Calculate the location of LC double pole F
and ESR zero F
ESR
.
LC
14
Page 15
NX2307
21.5uH4500uF
26.33m4500uF
××Ω
=10k
=37.2k
237.4k0.751.94kHz
p
F
37.4k150kHz
Gain=gR ... (18)
F= ... (19)
F ... (20)
22.2uH1360uF
=
F
LC
×π××
2LC
=
1
OUTOUT
1
×π××
=
1.94kHz
=
F
ESR
5.6kHz
×π××
2ESRC
=
×π×Ω×
=
2.Set crossover frequency FO=30kHz>>F
1
OUT
1
.
ESR
3. Set R2 equal to10kΩ. Based on output
voltage, using equation 21, the final selection of R1 is
20kΩ.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCO
32
VESR
in
1.1V230kHz1.5uH
12V6.33m
×π××
××
×π××
Ω
Ω
Choose R3 =37.4kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
Case 2:
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 15. R
and C1 introduce a zero to cancel the double pole effect.
C2 introduces a pole to suppress the switching noise.
The following equations show the compensator pole zero
location and constant gain.
R
1
××
m3
R+R
12
1
z
2RC
×π××
≈
p
2RC
31
1
×π××
32
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C2
C1
3
C=
1
=
1
×π××
2RF
3z
1
×π×Ω××
=2.9nF
Choose C1=2.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
π××
RF
3s
1
π×Ω×
=57pF
Choose C2=56pF.
Rev. 3.2
06/22/06
Figure 15 - Type II compensator with
transconductance amplifier(case 2)
The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V,
output inductor is 2.2uH, output capacitors are two 680uF
with 41mΩ electrolytic capacitors. See figure 20.
1.Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
2.9kHz
15
Page 16
NX2307
OUT
REF
2REF
OUT REF
IID1-D
220.5m1360uF
1220.5m2mA/V
22.87k0.752.9kHz
p
F
2.87k150kHz
1
OUT
1
=
F
ESR
5.7kHz
×π××
2ESRC
=
×π×Ω×
=
2.Set R2 equal to10kΩ. Using equation 18, the fi-
nal selection of R1 is 4.7kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1.1V230kHz2.2uH1
=
=2.9k
Choose R
×π××
×××
inESRmREF
×π××
××
2.5V
×
0.8V
1
Ω
Ω
=2.87kΩ.
3
5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.
C=
1
=
1
×π××
2RF
3z
1
×π×Ω××
=25nF
Choose C1=27nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
π××
RF
3s
1
π×Ω×
=369pF
Choose C2=390pF.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation applies to figure 17, which shows the relationship between
V ,
V and voltage divider..
Vout
R2
Fb
R1
Vref
Figure 16 - Voltage divider
RV
R=
1
Z
where R
of R1 value can be set by voltage divider.
×
V-V
is part of the compensator, and the value
2
...(21)
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated
as:
=××
RMSOUT
V
OUT
D
=
V
IN
VIN = 12V, VOUT=1.8V, IOUT=10A, the result of input
RMS current is 3.6A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OS-CON 16SVP180M 16V
180uF 20mΩ with 3.64A RMS rating are chosen as
input bulk capacitors.
...(22)
Rev. 3.2
06/22/06
16
Page 17
NX2307
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
I240mV/R
I17A
×−××
P=I(1D)RK
SWINOUTSWS
PVITF
=××××
Power MOSFETs Selection
The NX2307 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, I
=75A,R
loss:conduction loss, switching loss.
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3706 datasheet. Conduction
loss should not exceed package rating or overall system thermal budget.
conduction at the switching transition. The total
switching loss can be approximated.
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Swithing loss PSW is frequency
dependent.
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
side gate source voltage.
DSON
=9mΩ,Q
GATE
=23nC.
There are two factors causing the MOSFET power
Conduction loss is simply defined as:
2
P=IDRK
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
×××
2
...(23)
+
Switching loss is mainly caused by crossover
1
2
...(24)
Also MOSFET gate driver loss should be consid-
...(25)
where QHGATE is the high side MOSFETs gate
is the low
LGS
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2307, the current limit is decided by
the R
FET is on, and the voltage on SW pin is below 240mV,
D
of the low side mosfet. When synchronous
DSON
the over current occurs. The over current limit can be
calculated by the following equation.
=
SETDSON
The MOSFET R
is calculated in the worst case
DSON
situation, then the current limit for MOSFET IRFR3706
is
240mV240mV
===
SET
R1.49m
DSON
×Ω
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
R
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch-
Rev. 3.2
06/22/06
17
Page 18
ing the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be kept
away from the inductor and other noise sources, and be
placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2307
Rev. 3.2
06/22/06
18
Page 19
TYPICAL APPLICATIONS
NX2307
HI=SD
Vin
+12V
68pF
C4
100uF
C3
1uF
M3
C7
4.7nF
7
R4
16k
C2
6
5
Vcc
COMP
FB
R6
10
1
BST
NX2307
Gnd
3
L2 1uH
D1 MBR0530T1
2
Hdrv
8
SW
4
Ldrv
C6
0.1uF
C5
1uF
M1
half FDS6912A
L1 2.2uH
R1
11k
M2
half FDS6912A
C1
2.7nF
Cin
16MV1000WGL
16V,1000uF
Co
2 x MV1000WG
R2
15k
R3
12k
1000uF,30mohm
Figure 17 - NX2307 application with electrolytic capacitor and type III compensator
Vout
+1.8V 5A
HI=SD
Vin
+12V
L2 1uH
M3
C7
62pF
37.4k
C2
2.7nF
C4
100uF
R4
7
6
C3
1uF
5
Vcc
COMP
FB
R6
10
NX2307
D1 MBR0530T1
1
BST
Hdrv
SW
Ldrv
C6
0.1uF
2
8
4
C5
1uF
M1
IRFR3709
L1 1.5uH
M2
IRFR3709
Gnd
3
Figure 18 - NX2307 application with type II compensator(case 1)
Cin
16SVP180M
16V,180uF
R2
10k
R3
20k
Vout
Co
3 x 6MV1500WGL
1500uF,13mohm
+1.2V 12A
Rev. 3.2
06/22/06
19
Page 20
NX2307
HI=SD
Vin
+12V
390pF
L2 1uH
C4
100uF
C3
1uF
M3
C7
R4
2.87k
C2
27nF
7
6
5
Vcc
COMP
FB
R6
10
NX2307
D1 MBR0530T1
1
BST
Hdrv
SW
Ldrv
C6
0.1uF
2
8
4
C5
1uF
M1
IRFR3706
L1 2.2uH
M2
IRFR3706
Cin
16SVP180M
16V,180uF
R2
10k
Vout
Co
2 x (680uF,41mohm)
+2.5V 9A
Gnd
3
R3
4.7k
Figure 19 - NX2307 application with type II compensator(case 2)
Rev. 3.2
06/22/06
20
Page 21
SOIC8 PACKAGE OUTLINE DIMENSIONS
NX2307
Rev. 3.2
06/22/06
21
Page 22
NX2307
Rev. 3.2
06/22/06
22
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