Page 1
Evaluation board available.
NX2305
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER
WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2305 controller IC is a combination synchronous
Buck and LDO controller IC designed to convert single
12V supply to low cost dual on board supply applications. The synchronous controller is used for high current high efficiency step down DC to DC converter applications while the LDO controller in conjunction with an
external low cost N ch MOSFET can be used as a very
low drop out regulator in applications such as converting
3.3V to 2.5V output. Internal UVLO keeps both regulators off until the supply voltage exceeds 9V where independent internal digital soft starts get initiated to ramp
up both outputs.The switching section has hiccup current limit by sensing the Rdson of synchronous MOSFET.
The LDO controller has Feedback Under Voltage Lock
Out as a short circuit protection.Other features includes:
12V gate drive capability , Adaptive dead band control,
Power good flag for the switcher controller and separate
Enable pins for independent power sequencing.
R14
VIN2
+3.3V
VOUT2
+1.6V/2A
VIN2
+3.3V
HI=SD
VIN1
+12V
HI=SD
C9
47uF
C8
150uF
25mohm
R10
0.75k
R12
6.8k
M5
R11
1.4k
R13
1.4k
C11
open
R6
10k
150pFC10
R8
R9
5k
5k
M3
M4
5V REG
PGOOD
LDO OUT
LDO FB
ENLDO
ENSW
C12
1uF
VCC
N X 2 3 0 5
AGND
FEATURES
n 12V PWM controller plus LDO controller
n Hiccup current limit by sensing Rdson of MOSFET
n 12V high side and low side driver
n Fixed internal 300kHz for switching controller
n Dual Independent Digital Soft Start Function
n Adaptive Deadband Control
n Enable pin available to program the Vbus UVLO
n Shut Down switching and LDO via pulling down
EnSW or ENLDO pins
n Pb-free and RoHS compliant
APPLICATIONS
n PCI Graphic Card on board converters
n Mother board On board DC to DC applications
n On board Single Supply 12V DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Set Top Box and LCD Display
TYPICAL APPLICATION
10
0.1uF
C1
PVCC
BST
HDRV
SW
OCP
LDRV
PGND
FB
COMP
R1
4k
R5
10k
C13
1N4148
C4
0.1uF
C5
5.6nF
100pF
L1 1uH
C2
180uF
M1
IRFR3709Z
L2 2.2uH
M2
IRFR3709Z
R2
1.1k
C6
3.9nF
C3
100uF
R4
8k
R3
10k
C7
2 x 470uF
VIN1
+12V
VOUT1
+1.8V/10A
Rev.5.0
08/19/08
Figure1 - Typical application of NX2305
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2305CMTR 0 to 70oC MLPQ-16L 300kHz Yes
NX2305CSTR 0 to 70oC SOIC -16L 300kHz Yes
1
Page 2
NX2305
θ≈46/
CW
θ≈83/
CW
Supply Current
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
16-LEAD PLASTIC MLPQ 16-LEAD PLASTIC SOIC
o
JA
HDRV
PGND
LDRV
PVCC
o
BST
HDRV
GND
LDRV
PVCC
VCC
LDO-OUT
LDO-FB
1
2
3
4
5
6
7
8 9
16
15
14
13
12
11
10
SW
OCP
COMP
FB
PGOOD
EN-SW
EN-LDO
5V REG
12
11
JA
FB
PGOOD
BST
SW
OCP
COMP
16
15 14
13
1
2
17
AGND
EN-SW
3
4
5
7
6
10
EN-LDO
9
8
VCC
LDO-FB
LDO-OUT
5V REG
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, V
BST-VSW
= 0 to 70oC. Typical values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
REF
Ref Voltage line regulation 10V<=Vcc<=14V 0.2 %
Supply Voltage(Vcc&V
VCC Voltage Range V
V
CC
(Static)
PVCC Supply Current
(Dynamic)
V
Voltage Range V
BST
V
Supply Current(Static) V
BST
BST
)
CC
ICC (Static) mAENSW=LOW
ENLDO=LOW
I
CC
CL=3300pF 8.5 mA
(Dynamic)
to V
BST
BST
SW
(Static) ENSW=LOW
ENLDO=LOW
=12V, ENSW=ENLDO=3V, and T
0.8
8.2 14
8
8.2 14
0.2 mA
A
V
V
V
Rev.5.0
08/19/08
2
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NX2305
High Side Driver, Hdrv, BST,
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
V
Supply Current
BST
(Dynamic)
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising (NOTE1)
VCC hysterises VCC Falling (NOTE1)
Oscillator (Rt)
Frequency F
Ramp-Amplitude Voltage V
Max Duty Cycle
Min duty Cycle
Error Amplifiers
Open Loop Gain 50 65 dB
Transconductance gm 2000 umho
Comp SD threshold 0.2 V
Input Bias Current Ib 100 nA
EN & SS
Soft Start time Tss 6.8 mS
Enable HI Threshold V
Enable Hysterises V
V
BST
(dynamic)
S
RAMP
ENTHH
ENTHL
CL=3300PF 9.2 mA
6.8
300
V
mV
300 KHz
1.1 V
94 %
0
%
1.24 V
30 mV
SW (CL=3300pF)
Output Impedance , Sourcing
R
(Hdrv) I=200mA
source
ohm3.6
Current
R
(Hdrv) I=200mA
sink
1 ohmOutput Impedance , Sinking
Current
Rise Time THdrv(Rise) 10% to 90% 30 ns
Fall Time THdrv(Fall) 90% to 10% 20 ns
Deadband Time
N
Tdead(L to
H)
ns50
High, 10% to 10%
Low Side Driver , Ldrv,
PVcc, Pgnd(CL=3300pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 2.2 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 1 ohm
sink
Current
Rise Time TLdrv(Rise) 10% to 90% 30 ns
Fall Time TLdrv(Fall) 90% to 10% 20 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
50
ns
High, 10% to 10%
LDO Controller
FB Pin- Bias Current
High Output Voltage
Low Output Voltage 0.2
High Output Source Current
1
uA
11.1 V
1.9 mA
V
Rev.5.0
08/19/08
3
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NX2305
PARAMETER SYM Test Condition Min TYP MAX Units
Open Loop Gain GBNT(Note 2)
FB Under Voltage trip point 50 %
Power Good(Pgood)
Threshold Voltage as % of
Vref
Hysteresis 5 %
OCP Adjust
OCP Current Setting 40 uA
NOTE1: VCC is connected to ENSW pin via a resistor divider. In VCC UVLO test, ENSW pin is open.
NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).
FB ramping up 90 %
50
dB
Rev.5.0
08/19/08
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PIN DESCRIPTIONS
PIN SYMBOL PIN DESCRIPTION
VCC
IC’s supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor
is placed as close as possible to and connected to this pin and ground pin. The maximum rating
of this pin is 16V.
NX2305
BST
ENLDO
ENSW
FB
COMP
OCP
SW
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as
close as possible to and connected to these pins and SW pin.
A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start
until this threshold is reached. An external low cost MOSFET can be connected to this pin for
external enable control.
A resistor divider is connected from the respective switcher BUS voltage to this pin that holds off
the controller's soft start until this threshold is reached. An external low cost MOSFET can be
connected to this pin for external enable control.
This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output
of the switching regulator to set the output DC voltage.
This pin is the output of error amplifier and is used to compensate the voltage control feedback
loop.
This pin is connected to the drain of the external low side MOSFET and is the input of the over
current protection(OCP) comparator. An internal current source 40uA is flown to the external
resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit
point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins
are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048
switching cycles.
This pin is connected to source of high side FET and provides return path for the high side driver.
It is also used to hold the low side driver low until this pin is brought low by the action of high side
turning off. LDRV can only go high if SW is below 1V threshold .
HDRV
LDRV
PVCC
LDO_FB
LDO_OUT
5V REG
Rev.5.0
08/19/08
High side gate driver output.
Low side gate driver output.
Supply voltage for the low side fet driver. A high frequency 1uF ceramic cap must be connected
from this pin to the PGND pin as close as possible.
LDO controller feedback input. This pin is connected via resistor divider to the output of the
switching regulator to set the output DC voltage.If the LDOFB pin is pulled below 0.4V, an internal
comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the
startup this latch is not activated, allowing the LDOFB pin to come up and follow the soft started
Vref voltage.
LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum
rating of this pin is 16V.
Output of an internal 5V regulator.
5
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PIN SYMBOL PIN DESCRIPTION
PGOOD
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When
FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state.
NX2305
PGND
AGND
A((
Power ground pin for low side driver. In SOIC16 package, PGND and AGND are combined
together called GND.
Analog ground. In MLPD16 package, pad is AGND.
Rev.5.0
08/19/08
6
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BLOCK DIAGRAM
NX2305
5VREG
VCC
ENSW
FB
COMP
GND
Bias
Generator
Bias
Regulator
90k
20k
START
Digital
start Up
V
ENTHH
V
ENTHL
COMP
0.2V
0.8V
ramp
START
1.25V
0.8V
OSC
UVLO
ENSW_HI
0.6V
CLAMP
1.3V
CLAMP
FB
0.9Vref
/0.85Vref
POR
START
OC
Control
Logic
PWM
S
Q
R
Hiccup Logic
OC
0.4
I
40uA
OCP
comparator
PGOOD
BST
HDRV
SW
PVCC
LDRV
PGND
OCP
OCP
FBLDO
ENLDO
Rev.5.0
08/19/08
1.25/1.15
POR
ENSW_HI
LDO digital
start up
Figure 2 - Simplified block diagram of the NX2305
LDOOUT
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NX2305
RIPPLEINS
1
IVF
0.310A12V300kHz
=2.3A
SOUT
==Ω
ESR=8.7m
ERIPPLE
9m2.3A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VIN=12V
VOUT=1.8V
IOUT =10A
DVRIPPLE <=20mV
DVTRAN<=100mV @ 10A step
FS=300kHz
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
OUT
INOUT OUT
××
×
12V-1.8V1.8V1
×
××
...(1)
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
OUT
L=1.7uH
OUT
Choose LOUT=2.2uH, then coilcraft inductor
DO5010P-222HC is a good choice.
Current Ripple is calculated as
V-VV
I=
RIPPLE
INOUT OUT
LVF
12V-1.8V1.8V1
2.2uH12V300kHz
××
OUTINS
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
is the value of output capacitors.
OUT
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
desire
V
RIPPLE
∆
I2.3A
RIPPLE
20mV
∆
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP
2R5TPE470M9 with 9mΩ are chosen.
ESRI
N
=
∆
×∆
V
RIPPLE
Number of Capacitor is calculated as
20mV
Ω×
=
N
N =1.03
The number of capacitor has to be round up to a
integer. Choose N =2.
RIPPLE
××
8FC
...(3)
...(4)
...(5)
Rev.5.0
08/19/08
8
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NX2305
8300kHz100uF
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.76H
=µ
9m470F7.97us
2
(7.97us)
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.3A
RIPPLE
4.6mV9.6mV14.2mV
=+=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
∆V
droop
∆V
<
@step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the overshoot when load from high load to light load with a
DI
transient load, if assuming the bandwidth of
STEP
system is high enough, the overshoot can be estimated as the following equation.
VESRI
overshootstep
2LC
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected out-
2.3A
××
STEP
V
OUT
××
OUT
...(6)
...(7)
...(8)
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤ is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 10A load step.
If the POSCAP 2R5TPE470M9 (470uF, 9mohm
ESR) is used, the crticial inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
L
crit
9m470F1.8V
Ω×µ×
10A
The selected inductor is 2.2uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitor is
LI
×∆
step
τ=−×
V
OUT
2.2H10A
µ×
=−Ω×µ=
1.8V
ESRI
×∆
N
=+×
1.44
=
Estep
=+×τ
9m10A1.8V
V2LCV
∆×××∆
Ω×
100mV22.2H470F100mV
ESRC
EE
V
OUT
tranEtran
×µ×µ×
2
Rev.5.0
08/19/08
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Page 10
NX2305
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we choose N=2.
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should
be chosen.
1
2RC
×π××
42
1
2(RR)C
×π×+×
233
1
2RC
×π××
33
1
CC
×
2R
×π××
4
CC
12
+
12
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.
C2
Zf
C1
R4
Zin
Vout
R3
R2
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev.5.0
08/19/08
C3
Fb
gm
Ve
R1
Vref
Figure 3 - Type III compensator using
transconductance amplifier
10
Page 11
Case 1: FLC<FO<F
22.2uH940uF
24.5m940uF
=940uF
20.753.5kHz10.2k
×π×××Ω
210.2k150kHz
237.6kHz3.9nF
==Ω
R=8k
=(-)
210k3.5kHz37.6kHz
=4.1nF
power stage
F
Gain(db)
ESR
LC
40dB/decade
NX2305
×
V-V1.8V-0.8V
OUT REF
RV
2REF
1
Choose R1=8kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate R4 and C3 with the crossover
frequency at 1/10~ 1/5 of the switching frequency. Set
FO=25kHz.
Ω×
10k0.8V
ESR
.
loop gain
ESR
F
20dB/decade
compensator
F
Z1 Z2
F
F
O
F
P1
F
P2
Figure 4 - Bode plot of Type III compensator
(FLC<FO<F
ESR
)
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<F
and FO<=1/10~1/5Fs is shown as the
ESR
following steps.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
3.5kHz
=
F
=
ESR
2ESRC
=
37.6kHz
=
1
×π××
OUT
1
×π×Ω×
2. Set R2 equal to 10kΩ.
C=(-)
R=C
=10.4k
111
3
2RFF
×π×
×π×Ω
V2FL
OSCO
4out
VC
in3
1.1V225kHz2.2uH
12V3.9nF
×
2z2p1
111
××
××
×
×π××
×π××
Ω
Choose C3=3.9nF, R4=10.2k.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
5.95nF
=
Choose C2=5.6nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
104pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=100pF.
7. Calculate R3 by equation (13).
1
2FC
×π××
P13
1
×π××
R
=
3
=
1.1k
=Ω
Choose R3 =1.1kΩ.
Rev.5.0
08/19/08
11
Page 12
NX2305
22.2uH1500uF
213m1500uF
==Ω
R=12k
=(-)
215k2.77kHz8.16kHz
=2.5nF
28.16kHz2.7nF
1.1V230kHz2.2uH15k7.32k
12V13m15k7.32k
×π××Ω×Ω
ΩΩ+Ω
20.752.77kHz14.3k
×π×××Ω
214.3k150kHz
Case 2: FLC<F
power stage
Gain(db)
loop gain
compensator
F
Z1 Z2
ESR<FO
LC
F
ESR
F
F
40dB/decade
F
P1
F
O
20dB/decade
F
P2
2. Set R2 equal to 15kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
15k0.8V
×
Choose R1=12kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate C3 .
C=(-)
111
3
2RFF
×π×
×π×Ω
×
2z2p1
111
×
Choose C3=2.7nF.
5. Calculate R3 .
1
2FC
×π××
P13
1
×π××
R
=
3
=
7.22k
=Ω
Choose R3 =7.32kΩ.
6. Calculate R4 with FO=30kHz.
Ω×
ESR
.
Figure 5 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here one SANYO MV-WG1500
with 13 mΩ is chosen as output capacitor.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
2.77kHz
=
F
=
ESR
2ESRC
=
8.16kHz
=
1
×π××
OUT
1
×π×Ω×
V2FLRR
OSCO23
R=
4
VESRRR
=
=14.3k
×π×××
××
in23
+
××
Ω
Choose R4=14.3kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
3.9nF
=
Choose C2=3.9nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
74pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=82pF.
Rev.5.0
08/19/08
12
Page 13
B. Type II compensator design
Gain= ... (15)
F= ... (16)
F ... (17)
21.5uH4500uF
26.33m4500uF
××Ω
=10k
=37.2k
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<F
Case 1:
RC circuit as shown in figure 7. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise.
the compensator of transconductance amplifier must
satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The
following equations show the compensator pole zero location and constant gain.
<<FO<=1/10~1/5F
ESR
s.
Type II compensator can be realized by simple
To achieve the same effect as voltage amplifier,
R
3
R
2
1
z
2RC
×π××
31
≈
p
1
2RC
×π××
32
power stage
NX2305
C2
Vout
R3
R2
Fb
R1
Vref
Figure 7 - Type II compensator with
transconductance amplifier(case 1)
The following parameters are used as an example for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P152HC 1.5uH is used as output inductor. See figure
19. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.
1.Calculate the location of LC double pole F
and ESR zero F
=
F
LC
2LC
=
.
ESR
1
×π××
OUTOUT
×π××
=
1.94kHz
C1
gm
Ve
LC
1
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
F
LC
Z
ESR
P
F
F
O
Figure 6 - Bode plot of Type II compensator
Rev.5.0
08/19/08
=
F
ESR
2ESRC
=
=
5.6kHz
2.Set crossover frequency FO=30kHz>>F
1
×π××
OUT
1
×π×Ω×
ESR
.
3. Set R2 equal to10kΩ. Based on output voltage,
using equation 21, the final selection of R1 is 20kΩ.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCO
32
VESR
in
1.1V230kHz1.5uH
12V6.33m
×π××
××
×π××
Ω
Ω
Choose R3 =37.4kΩ.
13
Page 14
NX2305
Gain=gR ... (18)
F= ... (19)
F ... (20)
237.4k0.751.94kHz
p
F
37.4k150kHz
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
C=
1
=
1
×π××
2RF
3z
1
×π×Ω××
=2.9nF
Choose C1=2.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
π××
RF
3s
1
π×Ω×
=57pF
Choose C2=56pF.
Case 2:
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 9. R3 and
C1 introduce a zero to cancel the double pole effect. C2
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero location and constant gain.
R
1
××
m3
R+R
12
1
z
2RC
×π××
≈
p
2RC
31
1
×π××
32
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
F
LC
Z
ESR
P
F
F
O
Figure 8 - Bode plot of Type II compensator
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C2
C1
Rev.5.0
08/19/08
Figure 9 - Type II compensator with
transconductance amplifier
For this type of compensator, FO has to satisfy
FLC<F
<<FO<=1/10~1/5F
ESR
s.
The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 3.3V,
output inductor is 1.5uH, output capacitors are two 680uF
with 41mΩ electrolytic capacitors.
1.Calculate the location of LC double pole F
and ESR zero F
ESR
.
LC
14
Page 15
NX2305
21.5uH1360uF
220.5m1360uF
1220.52mA/V
22.61k0.753.5kHz
p
F
2.61k300kHz
OUT
REF
2REF
OUT REF
IID1-D
1
OUTOUT
1
F
=
LC
2LC
×π××
=
×π××
3.5kHz
=
1
×π××
OUT
1
×π×Ω×
F
=
ESR
2ESRC
=
5.7kHz
=
2.Set R2 equal to10.2kΩ. Using equation 21, the
final selection of R1 is 3.24kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.
V2FL
OSCO 12
R=
3
VRgR
1.1V230kHz1.5uH1
=
=2.6k
×π××
×××
inESRm1
×π××
××
10.2k+3.24k
×
ΩΩ
3.24k
Ω
Ω
R+R
1
Ω
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation and picture show the relationship between
V ,
V and voltage divider..
Vout
R2
Fb
R1
Vref
Figure 10 - Voltage divider
RV
R=
1
where R2 is part of the compensator, and the
value of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
×
V-V
...(21)
Choose R3 =2.61kΩ.
5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=23nF
Choose C1=22nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
=406pF
1
RF
π××
3s
1
π×Ω×
Choose C1=390pF.
Input Capacitor Selection
Z
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF
ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by
voltage rating and RMS current rating. The RMS current
in the input capacitors can be calculated
as:
=××
RMSOUT
V
OUT
D
=
V
IN
...(22)
VIN = 12V, VOUT=1.8V, IOUT=10A, using equation
(22), the result of input RMS current is 3.6A.
For higher efficiency, low ESR capacitors are
recommended.
Rev.5.0
08/19/08
15
Page 16
NX2305
ENTHH2
(8VV)R
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
One Sanyo OS-CON 16SVP180M 16V 180uF
20mΩ with 3.64A RMS rating are chosen as input bulk
capacitors.
Power MOSFETs Selection
The NX2305 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3709Z are
used. They have the following parameters: VDS=30V,R
=6.5mΩ,Q
GATE
=17nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
2
×××
2
K
+
...(23)
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3709Z datasheet. Conduc-
tion loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
1
2
...(24)
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Switching loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
DSON
...(25)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
is the low
LGS
side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
Soft Start and Enable
NX2305 has digital soft start for switching controller and has one enable pin for this start up. When the
Power Ready (POR) signal is high and the voltage at
enable pin is above V
starts to operate and the voltage at positive input of Error
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the desired voltage decided by the feedback resistor divider.
Vbus
+
OFF
ON
10k
R1
R2
Figure 11 - Enable and Shut down the NX2305
with Enable pin.
The start up of NX2305 can be programmed through
resistor divider at Enable pin. For example, if the input
bus voltage is 12V and we want NX2305 starts when
Vbus is above 8V. We can select
R
−×
=
R
1
V
ENTHH
The NX2305 can be turned off by pulling down the
Enable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin is below V
tal soft start is reset to zero. In addition, all the high side
and low side driver is off and no negative spike will be
generated during the turn off.
the internal digital counter
ENTHH,
ENSW or
ENLDO
POR
ENTHH
V
ENTHL
V
Digital
start
up
ENTHL,
the digi-
Rev.5.0
08/19/08
16
Page 17
NX2305
SWLDSON
IR+V
IIR/R
===Ω
R3.375k
RDSONLDOINLDOOUTLOAD
(3.3V2.5V)/2A0.4
=−=Ω
(3.3V2.5V)2A1.6W
gESR
C=
4FR1+gESR
Over Current Protection
Over current protection for NX2305 is achieved by
sensing current through the low side MOSFET. An internal current source of 40uA flows through an external resistor connected from OCP pin to SW node sets the
over current protection threshold. When synchronous FET
is on, the voltage at node SW is given as
V=-IR×
The voltage at pin OCP is given as
×
OCPOCPSW
When the voltage is below zero, the over current
occurss as shown in figure 12.
vbus
OCP
I
40uA
OCP
comparator
Figure 12 - Over current protection
The over current limit can be set by the following
equation
=×
SETOCPOCPDSON
If the MOSFET R
DSON
is set at 15A, then
×
IR
SETDSON
OCP
Choose R
I40uA
OCP
=4kΩ
OCP
OCP
R
OCP
SW
=9mΩ, and the current limit
×Ω
15A9m
R(VV)I
=−×
Most of MOSFETs can meet the requirement. More
important is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as
P(VV)I
=−×
LOSSLDOINLDOOUTLOAD
=−×=
Select IR MOSFET IRFR3706 with 9mΩ R
DSON
is
sufficient.
LDO Compensation
The diagram of LDO controller including VCC regulator is shown in figure 13.
LDO input
+
Vref
R
f1
R
f2
Rc Cc
Figure 13 - NX2305 LDO controller.
For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows.
ESR
Co
Rload
LDO Selection Guide
NX2305 offers a LDO controller. The selection of
MOSFET to meet LDO is more straight forward. The
selection is that the Rdson of MOSFET should meet
the dropout requirement. For example.
V
=3.3V
LDOIN
V
I
Load
The maximum Rdson of MOSFET should be
Rev.5.0
08/19/08
LDOOUT
=2A
=2.5V
C
1
×π×××
Of1m
×
m
×
where FO is the desired crossover frequency.
Typically, in this LDO compensation, crossover
frequency FO has to be higher than zero caused by ESR.
FO is typically around several tens kHz to a few hundred
kHz. For this example, we select Fo=100kHz. gm is the
forward trans-conductance of MOSFET.
For IRFR3706, gm=53.
Select Rf1=5kohm.
Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.
17
Page 18
NX2305
C= =77pF
×Ω
LDOOUTREF
5k0.8V
1.6V0.8V
2100kHz10uF
1010uF
12.7k5S
C
15318m
4100kHz5k1+5318m
×π××Ω×Ω
×
Choose CC=82pF. For electrolytic or POSCAP, R
is typically selected to be zero.
Rf2 is determined by the desired output voltage.
RV
×
R=
f2
=
Ω
f1REF
VV
−
Ω×
−
=5k
Choose Rf2=5kΩ.
When ceramic capacitors or some low ESR bulk
capacitors are chosen as LDO output capacitors, the
zero caused by output capacitor ESR is so high that
crossover frequency FO has to be chosen much higher
than zero caused by RC and CC and much lower than
zero caused by ESR . For example, 10uF ceramic is
used as output capacitor. We select Fo=100kHz,
Rf1=5kohm and select MOSFET MTD3055(gm=5). R
and C
can be calculated as follows.
C
2FC
×π××
R=R
=5k
Ω
Cf1
=12.56k
×
Ω×
OO
0.5g
×
m
×π××
0.55S
×
Choose RC=12.7kΩ.
10C
×
C=
C
=
=1.6nF
Choose C
O
Rg
×
Cm
×
Ω×
=1.5nF.
C
Current Limit for LDO
Current limit of LDO is achieved by sensing the
LDO feedback voltage. When LDO_FB pin is below 0.4V,
the IC goes into hiccup mode. The IC will turn off all the
channel for 2048 cycles and start to restart system again.
Layout Considerations
C
C
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch-
ing the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
Rev.5.0
08/19/08
18
Page 19
wide and short. A place for gate drive resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2305
VOUT1
+1.8V
VOUT2
+1.2V/2A
VOUT1
+1.8V
HI=SD
VIN1
+12V
HI=SD
10
R14
C11
C12
open
1uF
C9
47uF
C8
150uF
25mohm
R10
0.75k
R12
6.8k
M5
R11
1.4k
R13
1.4k
VCC
M3
M4
C10
5V REG
PGOOD
LDO OUT
LDO FB
ENLDO
ENSW
R6
10k
R7
0
150pF
R8
R9
5k
5k
PVCC
HDRV
LDRV
N X 2 3 0 5
PGND
COMP
AGND
BST
SW
OCP
FB
C1
1uF
R1
5k
R5
40.2k
C13
1N4148
C4
0.1uF
C5
1.8nF
27pF
M1
IR3709
L2 2.2uH
M2
IR3711
L1 1uH
C2
180uF
22.1k
820pF
R2
C6
Figure 14 - Typical application of NX2305 with single power supply
C3
100uF
49.9k
R4
40.2k
VIN1
+12V
VOUT1
C7
1500uF
13mohm
R3
+1.8V/10A
Rev.5.0
08/19/08
19
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