Page 1
NX2142/2142A
SINGLE CHANNEL PWM CONTROLLER WITH FEEDFORWARD
AND 5V BIAS REGULATOR
ADVANCE DATA SHEET
Pb Free Product
DESCRIPTION
The NX2142/2142A controller IC is a compact synchronous Buck controller IC with 10 lead MSOP package
designed for step down DC to DC converter applications with voltage feedforward functionality. Voltage
feedforward provides fast response, good line regulation and nearly constant power stage gain under wide
voltage input range. The NX2142/2142A controller is
optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. NX2142/2142A
can function as a single supply controller with its 5V
bias regulator. Internal UVLO keeps the regulator off
until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The
NX2142/2142A employs fixed current limiting and FB
UVLO followed by hiccup feature. Other features includes: 5V gate drive capability , Converter Shutdown
by pulling COMP pin to Gnd, Adaptive dead band control.
Vin
+8 to 20V
MMBT3904
1uF
FEATURES
n Bus voltage operation from 7V to 24V
n 5V bias regulator available
n Excellent dynamic response with input voltage
feed-forward and voltage mode control
n Fixed 600kHz, 1MHz switching frequency
n Internal Digital Soft Start Function
n Fixed internal hiccup current limit
n FB UVLO followed by hiccup feature
n Shutdown by pulling COMP pin low
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic Card on board converters
n Vddq Supply in mother board applications
n On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n Set Top Box and LCD Display
TYPICAL APPLICATION
1uF47uF
BAT54A
25TQC33M
1
BST
Hdrv
SW
NX2142
Ldrv
0.1uF
2
10
4
AO4800(half)
DO3316P-682
1000uF,30mohm
AO4800(half)
1k
324
27pF
0.1uF
20k
5.2nF
6
REGOUT
5
VIN
9
COMP
8
FB
7
VCC
Gnd
3
Figure1 - Typical application of NX2142
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2142CUTR 0 to 70oC MSOP-10L 600kHz Yes
NX2142ACUTR 0 to 70oC MSOP-10L 1MHz Yes
Vout
+3.3V /3A
Rev. 1.1
10/28/07
1
Page 2
NX2142/2142A
CW
θ≈200/
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V
VIN to GND ........................................................ -0.3V to 30V
BST to GND Voltage .......................................... -0.3V to 35V
SW to GND ....................................................... -2V to 35V
REGOUT to GND ................................................ 0.2 to 16V
All other pins ..................................................... -0.3V to 6.5V
Storage Temperature Range ................................ -65oC to 150oC
Operating Junction Temperature Range ................ -40oC to 125oC
ESD Susceptibility ............................................ 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
o
10
SW
BST
JA
1
HDrv
GND
LDrv
VIN
2
3
4
5
COMP
9
8
FB
7
VCC
REGOUT
6
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical
values refer to TA = 25oC.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
REF
Ref Voltage line regulation 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
Operating quiescent current I
CC
Q
EN=HIGH 3
Vcc UVLO
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V
Supply Voltage(Vin)
Vin Voltage Range V
in
7 25
Input Voltage Current Vin=24V 9
Vin UVLO
Vin-Threshold Vin_UVLO Vin Rising
0.8
5
4.4
6
V
V
mA
V
V
mA
V
Rev. 1.1
10/28/07
2
Page 3
NX2142/2142A
(CL=3300pF)
(CL=3300pF)
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
Vin-Hysteresis Vin_Hyst Vin Falling 0.5 V
Oscillator (Rt)
Frequency F
S
Frequency Over Vin
Ramp Peak to Peak Voltage V
RAMP
Ramp Valley Voltage 0.8 V
Ramp Peak to Peak/Vin Gain 0.1 V/V
Max Duty Cycle FS=600kHz
Min Duty Cycle
Min Controllable on time
Error Amplifiers
Transconductance 2500 umho
Input Bias Current Ib 100 nA
Comp SD threshold 0.3 V
Soft Start
Soft Start time Tss NX2142 3.4 mS
High Side Driver
NX2142 600 KHz
NX2142A 1000 KHz
1
%
Vin=20V 2 V
77 %
0 %
150
nS
NX2142A 2 mS
R
(Hdrv) I=200mA
source
1
ohmOutput Impedance , Sourcing
Current
Output Impedance , Sinking
R
(Hdrv) I=200mA
sink
ohm0.8
Current
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time
N
Low Side Driver
Output Impedance, Sourcing
Tdead(L to
H)
R
(Ldrv) I=200mA 1 ohm
source
High, 10% to 10%
ns30
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 0.5 ohm
sink
Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
30
ns
High, 10% to 10%
Fixed OCP
OCP voltage threshold 320 mV
FBUVLO
Feedback UVLO threshold percent of nominal
70
%
Over temperature
Threshold
150
°C
Hysteresis 20 °C
Rev. 1.1
10/28/07
3
Page 4
PIN DESCRIPTIONS
PIN SYMBOL PIN DESCRIPTION
This pin supplies the internal 5V bias circuit. A 1uF high frequency ceramic X5R
VCC
BST
capacitor must be placed as close as possible to this pin and ground pin to provide
high frequency bypass and to make the 5V regulator stable.
This pin supplies voltage to high side FET driver. A minimum 0.1uF ceramic high
frequency capacitor is placed as close as possible to and connected to this pin and
SW pin.
NX2142/2142A
GND
FB
COMP
SW
HDRV
LDRV
REGOUT
Power ground.
This pin is the error amplifiers inverting input. It is connected via resistor divider to
the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to compen-
sate the voltage control feedback loop. You can shutdown the switching regulator by
pulling this pin below 0.3V.
This pin is connected to source of high side FETs and provides return path for the
high side driver. This pin also provides input for the OCP comparator by sensing the
RDSON of the lower MOSFET. When this pin is below ground by 320mV, both drivers
are shutdown and enter hiccup mode.
High side gate driver output.
Low side gate driver output.
The output of the 5V regulator controller that drives a low current low cost external
bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived
from bus voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. This regulator request a 1uF ceramic X5R type output
capacitor in order to be stable.
Rev. 1.1
10/28/07
VIN
This pin provides the input voltage to the 5V regulator controller as well as the
oscillator for the PWM feed forward to work. When VIN exceeds 6V, the converter
starts to operate.
4
Page 5
BLOCK DIAGRAM
VIN
4.4/4.2V
6V/
5.5V
Bias
Generator
COMP
START
Digital
start Up
0.3V
0.8V
VCC
FB
1.25V
ramp
0.8V
VIN
OSC
Ref
UVLO
NX2142/2142A
Regout
POR
START
OC
Control
Logic
PWM
S
Q
R
OC
VCC
BST
HDRV
SW
LDRV
COMP
GND
POR
Hiccup Logic
START
0.6V
CLAMP
1.3V
CLAMP
Figure 2 - Simplified block diagram of the NX2142
320mV
OCP
comparator
SS_half_done
70%*Vp
FB
Rev. 1.1
10/28/07
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Page 6
TYPICAL APPLICATION CIRCUIT
NX2142/2142A
BUS
GNDBUS
C10
47u
BUS(8-20V)
Q1
2N3904
EN_REGOUT
U1
6
EN/REG_OUT
C6
0.1u
U_VIN
5
VIN
U_VCC
7
BST
VCC
HDRV
SW
LDRV
NX2142CUTR
C2
1u
D1
BAT54A
BST
1
C1
0.1u
2
10
4
U_SW SW
VDD
Ci1
25TQC33M
C14
1u
7
8
M5A
HDRVU_HDRV
LDRVU_LDRV
STM6912
2
1
5
6
M6B
STM6912
4
3
Lo
1 2
DO3316P-682
R15
10
C9
470p
OUT(5V)
Co1
1000uF, 6.3v,30mohm
VOUT
GNDOUT
Rev. 1.1
10/28/07
C5
25n
R8
1.2k
R9
4.99k
GND
3
FB
COMP
FB
8
R7
10k
C3
3.3n
COMP
9
C4
52p
R10
953
Figure 3- Demo board schematic(VIN=8-20V,VOUT=5V,IOUT=3A)
6
Page 7
NX2142/2142A
Bill of Materials
Item Quantity Reference Value Manufacture
1 1 Ci1 25TQC33M SANYO
2 1 Co1 6MV1000WG SANYO
3 2 C1,C6 0.1u
4 3 C2,C14 1u
5 1 C3 3.3n
6 1 C4 52p
7 1 C5 25n
8 1 C9 470p
9 1 C10 47u
10 1 D1 BAT54A Fairchild
11 1 Lo DO3316P-682 Coilcraft
12 2 M5,M6 AO4800 AOS
13 1 Q1 MMBT3904 Fairchild
14 1 R7 10k
15 1 R8 1.2k
16 1 R9 4.99k 1%
17 1 R10 953 1%
18 1 R15 10
19 1 U1 NX2142CUTR NEXSEM INC.
Rev. 1.1
10/28/07
7
Page 8
Demoboard waveforms
Eff(%)
NX2142/2142A
Figure 4 - Output ripple (VIN=12V)
Figure 6 - Over current protection
100.00%
95.00%
90.00%
85.00%
80.00%
75.00%
70.00%
65.00%
60.00%
55.00%
50.00%
0 500 1000 1500 2000 2500 3000 3500
Iout(mA)
Figure 5 - Output voltage transient response
(VIN=12V, IOUT=3A)
Figure 7 - Startup
Figure 8 - Output Efficiency(VIN=12V, VOUT=5V)
Rev. 1.1
10/28/07
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Page 9
APPLICATION INFORMATION
RIPPLEINMAXS
1
IVF
0.33A20V600kHz
=0.919A
SOUT
ESR=54m
==Ω
ERIPPLE
30m0.919A
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple
Design Example
Power stage design requirements:
VINMIN=8V
VINMAX=20V
VOUT=5V
IOUT =3A
DVRIPPLE <=50mV
DVTRAN<=150mV @ 1.5A step
FS=600kHz
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:
V-VV
INMAXOUT OUT
L=
OUT
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
L=6.9uH
Choose LOUT=6.8uH, then coilcraft inductor
DO3316P-682HC is a good choice.
×
20V-5V5V1
OUT
OUT
×
××
...(1)
××
NX2142/2142A
Current Ripple is calculated as
V-VV
INOUT OUT
LVF
20V-5V5V1
6.8uH20V600kHz
××
OUTINS
××=
I=
RIPPLE
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specification for the load transient. The optimum design may
require a couple of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
tors.
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, Aluminum Electrolytic is chosen as output capacitor, the ESR and inductor current
typically determines the output voltage ripple.
∆
desire
∆
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 50mV output ripple, Electrolytic
6ME1000WG with 30mΩ are chosen.
ESRI
N
=
Number of Capacitor is calculated as
N
Ω×
=
50mV
N =0.55
The number of capacitor has to be round up to a
integer. Choose N =1.
is the value of output capaci-
OUT
V
RIPPLE
I0.919A
RIPPLE
×∆
V
∆
RIPPLE
1
∆
I
RIPPLE
××
8FC
50mV
...(5)
...(2)
...(3)
...(4)
Rev. 1.1
10/28/07
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Page 10
NX2142/2142A
8600kHz100uF
tran
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
100H
=µ
Estep
ESRI
0.225
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.
For example, one 100uF, X5R ceramic capacitor with 2m Ω ESR is used. The amount of output ripple
is
V2m0.919A
∆=Ω×+
RIPPLE
1.838mV1.9mV3.738mV
=+=
0.919A
××
One ceramic capacitors are needed. Although
this can meet DC ripple spec, however it needs to be
studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient is specified as
∆V
droop
∆V
<
@step load DI
STEP
During the transient, the voltage droop during
the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other
section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the
overshoot when load from high load to light load
with a DI
transient load, if assuming the band-
STEP
width of system is high enough, the overshoot can
be estimated as the following equation.
V
VESRI
overshootstep
OUT
2LC
××
OUT
...(6)
where τ is the a function of capacitor,etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(7)
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
...(8)
L
crit
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected
output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of
ESR and capacitance is high and
≤ is true. In
that case, the transient spec is mostly like to dependent on the ESR of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 150mV for 1.5A load step.
If the Electrolytic 6ME1000WG(1000uF, 30mohm
ESR) is used, the crticial inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
30m1000F5V
1.5A
The selected inductor is 6.8uH which is much
smaller than critical inductance. In that case, the output voltage transient not only dependent on the ESR,
but also capacitance.
number of capacitor is
V
∆
Ω×
200mV
×∆
tran
N
=
30m1.5A
=
=
The number of capacitors has to satisfy both ripple
and transient requirement. Overall, we choose N=1.
Rev. 1.1
10/28/07
10
Page 11
NX2142/2142A
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for
high frequency capacitor such as high quality POSCAP
especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the
ESR of capacitors is so low that the PCB parasitic can
affect the results tremendously. More capacitors have
to be selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of
the power stage, the power system has 180o phase
shift , and therefore, is unstable by itself. In order to
achieve accurate output voltage and fast transient response, compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain
crossing 0dB with -20dB/decade. Power stage output
capacitors usually decide the compensator type. If
electrolytic capacitors are chosen as output capacitors,
type II compensator can be used to compensate the
system, because the zero caused by output capacitor
ESR is lower than crossover frequency. Otherwise type
III compensator should be chosen.
Voltage feedforward compensation is used in
NX2142 to compensate the output voltage variation
caused by input voltage changing. The feedforward
funtion is realized by using VIN pin voltage to program
the oscillator ramp voltage V
at about 1/10 of V
OSC
voltage, which provides nearly constant power stage
gain under wide voltage input range.
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The
following figures and equations show how to realize
the type III compensator by transconductance amplifier.
1
×π××
2RC
42
1
×π×+×
2(RR)C
233
1
×π××
2RC
33
1
×
CC
4
CC
12
+
12
×π××
2R
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same
time,
C2
Fb
C1
Zf
gm
R4
Ve
Zin
Vout
IN
R3
R2
C3
R1
Vref
Figure 9 - Type III compensator using
transconductance amplifier
Rev. 1.1
10/28/07
11
Page 12
NX2142/2142A
26.8uH44uF
21.5m44uF
20.59.2kHz10k
×π×××Ω
210k300kHz
=44uF
=(-)
21.2nF0.75*9.2kHz300kHz
=18k
2600kHz1.2nF
Case 1: FLC<FO<F
ESR
ESR POSCAP, OSCON)
power stage
LC
F
Gain(db)
loop gain
compensator
F
F
Z1 Z2
(for most ceramic or low
40dB/decade
ESR
F
20dB/decade
F
O
F
F
P1
P2
2. Set R4 equal to 10kΩ.
3. Calculate C2 with zero Fz1 at 50% of the LC
double pole by equation (11).
C
=
2
2FR
=
3.5nF
=
Choose C2=3.9nF.
4. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
2RF
=
53pF
=
Choose C1=52pF.
5. Calculate C3 with the crossover frequency at
1/10~ 1/5 of the switching frequency. Set FO=60kHz.
1
×π××
Z14
1
1
×π××
4P2
1
×π×Ω×
Figure 10 - Bode plot of Type III compensator
(FLC<FO<F
ESR
)
Typical design example of type III compensator
in which the crossover frequency is selected as
FLC<FO<F
and FO<=1/10~1/5Fs is shown as the
ESR
following steps. Here two X5R 22uF ceramic capacitor
with 3m
Ω is chosen as output capacitor, output inductor
is 6.8uH.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
9.2kHz
=
F
=
ESR
2ESRC
×π××
=
×π×Ω×
241kHz
=
1
OUT
1
V2FL
OSCO
C=C
3out
VR
1260kHz6.8uH
1010k
×π××
××
in4
×π××
××
Ω
=1.1nF
Choose C3=1.2nF.
6. Set zero FZ2 = 0.75FLC and Fp1 =0.5Fs, calcu-
late R
2.
R=(-)
111
2
2CFF
×π×
×π×
×
3z2p1
111
×
Ω
Choose R2=20kΩ.
7. Calculate R3 by equation (13) with Fp1 =Fs.
1
2FC
×π××
P13
1
×π××
R
=
3
=
221
=Ω
Choose R3 =300Ω.
Rev. 1.1
10/28/07
12
Page 13
NX2142/2142A
26.8uH1000uF
230m1000uF
20.751.93kHz10k
×π×××Ω
210k300kHz
1030m10k5.3kHz
=(-)
225nF1.93kHz5.3kHz
=2k
R=5.7k
==Ω
8. Calculate R1.
RV
×
2REF
1
V-V5V-0.8V
OUT REF
Choose R1=5.7kΩ.
Case 2: FLC<F
ESR<FO
power stage
F
Gain(db)
F
loop gain
compensator
20k0.8V
Ω×
(for electrolytic capacitors)
LC
40dB/decade
ESR
20dB/decade
F
=
ESR
2ESRC
=
5.3kHz
=
1
×π××
OUT
1
×π×Ω×
2. Set R4 equal to 10kΩ.
3. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
C
=
2
=
10nF
=
Choose C2=10nF.
4. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
53pF
=
1
2FR
×π××
Z14
1
1
2RF
×π××
4P2
1
×π×Ω×
F
Z1 Z2
F
F
F
P1
F
O
P2
Figure 11 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here one SANYO 6ME-WG1000
with 30 mΩ is chosen as output capacitor, output
inductor is 6.8uH.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
2LC
=
.
ESR
1
×π××
OUTOUT
1
LC
×π××
1.93kHz
=
Choose C1=52pF.
5. Calculate C3 with the crossover frequency at
1/10~ 1/5 of the switching frequency. Set FO=60kHz.
VFL
C=
=
OSCO
3
×
VESRRF
in4P1
160kHz6.8uH
×
×
××
×
Ω×Ω×
=25nF
Choose C3=25nF.
6. Set zero FZ2 = FLC and Fp1 =F
R=(-)
111
2
2CFF
×π×
×π×
×
3z2p1
111
×
, calculate R
ESR
Ω
Choose R2=20kΩ.
7. Calculate R3 by equation (13) with Fp1 =F
ESR
2.
.
Rev. 1.1
10/28/07
13
Page 14
NX2142/2142A
Gain= ... (15)
F= ... (16)
F ... (17)
25.3kHz25nF
R=381
==Ω
1
2FC
×π××
P13
1
×π××
R
=
3
=
1.2k
=Ω
Choose R3 =1.2kΩ.
8. Calculate R1.
×
2REF
1
V-V5V-0.8V
OUT REF
1.2k0.8V
Ω×
RV
Choose R1=381Ω.
B. Type II compensator design
If the electrolytic capacitors are chosen as
power stage output capacitors, usually the Type II
compensator can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<F
Case 1:
RC circuit as shown in figure 13. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise.
the compensator of transconductance amplifier must
satisfy this condition: R3>>1/gm and R1||R2>>1/gm.
The following equations show the compensator pole
zero location and constant gain.
<<FO<=1/10~1/5F
ESR
s.
Type II compensator can be realized by simple
To achieve the same effect as voltage amplifier,
power stage
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
F
LC
Z
ESR
P
F
F
O
Figure 12 - Bode plot of Type II compensator
C2
Vout
R3
C1
R2
Fb
R1
gm
Ve
Vref
R
3
R
2
1
z
2RC
×π××
31
≈
p
Rev. 1.1
10/28/07
1
2RC
×π××
32
Figure 13 - Type II compensator with
transconductance amplifier(case 1)
The following parameters are used as an
example for type II compensator design, three
1500uF with 19mohm Sanyo electrolytic CAP
6MV1500WGL are used as output capacitors.
Coilcraft DO5010P-152HC 1.5uH is used as output
inductor. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=600kHz.
1.Calculate the location of LC double pole F
and ESR zero F
ESR
.
LC
14
Page 15
NX2142/2142A
21.5uH4500uF
26.33m4500uF
=4k
=36k
××Ω
237.4k0.751.94kHz
p
F
37.4k600kHz
Gain=gR ... (18)
F= ... (19)
F ... (20)
22.2uH1360uF
=
F
LC
×π××
2LC
=
1
OUTOUT
1
×π××
=
1.94kHz
=
F
ESR
2ESRC
=
=
5.6kHz
1
×π××
OUT
1
×π×Ω×
2.Set crossover frequency FO=60kHz>>F
ESR
.
Case 2:
simple RC circuit without feedback as shown in figure
15. R3 and C1 introduce a zero to cancel the double
pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
3. Set R2 equal to 4kΩ. Based on output
voltage, using equation 21, the final selection of R1 is
8kΩ.
4.Calculate R3 value by the following equation.
V2FL
R=R
OSCO
32
VESR
in
1260kHz1.5uH
106.33m
Ω
×π××
××
×π××
Ω
Choose R3 =37.4kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
Type II compensator can also be realized by
R
1
××
m3
R+R
12
1
z
2RC
×π××
≈
p
2RC
31
1
×π××
32
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C2
C1
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=2.7nF
Choose C1=2.7nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
RF
π××
3s
1
π×Ω×
=14pF
Choose C2=15pF.
Rev. 1.1
10/28/07
Figure 14 - Type II compensator with
transconductance amplifier(case 2)
The following is parameters for type II compen-
sator design. Input voltage is 12V, output voltage is
2.5V, output inductor is 2.2uH, output capacitors are
two 680uF with 41mΩ electrolytic capacitors.
1.Calculate the location of LC double pole F
and ESR zero F
=
F
LC
=
.
ESR
1
×π××
2LC
OUTOUT
1
LC
×π××
=
2.9kHz
15
Page 16
NX2142/2142A
OUT
REF
2REF
OUT REF
IID1-D
220.5m1360uF
1020.5m2.5mA/V
25k0.752.9kHz
p
F
5k600kHz
1
×π××
OUT
1
×π×Ω×
=
F
ESR
2ESRC
=
=
5.7kHz
2.Set R2 equal to10kΩ. Using equation 18, the
final selection of R1 is 4.7kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=60kHz.
4.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1260kHz2.2uH1
=
=5k
Ω
Choose R
×π××
×××
inESRmREF
×π××
××
2.5V
×
0.8V
=5kΩ.
3
1
Ω
5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=14nF
Choose C1=15nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
RF
π××
3s
1
π×Ω×
=54pF
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation applies to figure 15, which shows
the relationship between
V ,
V and voltage di-
vider.
Vout
R2
Fb
R1
Vref
Figure 15 - Voltage divider
RV
Z
R=
1
where R
of R1 value can be set by voltage divider.
×
V-V
is part of the compensator, and the value
2
...(21)
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors
can be calculated
as:
Choose C2=52pF.
Rev. 1.1
10/28/07
=××
RMSOUT
V
OUT
D
=
V
INMIN
...(22)
VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of
input RMS current is 3.4A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON CAP 25SVP56M
16
Page 17
NX2142/2142A
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
I320mV/R
I4.6A
×−××
P=I(1D)RK
SWINOUTSWS
PVITF
=××××
25V 56uF 28mΩ with 3.8A RMS rating are chosen
as input bulk capacitors.
Power MOSFETs Selection
The NX2142 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two STM6912 are
used. They have the following parameters: VDS=30V, I
=6A,R
power loss:conduction loss, switching loss.
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to
1.4 at 125oC according to datasheet. Conduction loss
should not exceed package rating or overall system
thermal budget.
duction at the switching transition. The total switching
loss can be approximated.
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charg
circuits.It is proportional to frequency and is defined
as:
=57mΩ,Q
DSON
=6.3nC.
GATE
There are two factors causing the MOSFET
Conduction loss is simply defined as:
2
P=IDRK
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
×××
2
...(23)
+
Switching loss is mainly caused by crossover con-
1
2
...(24)
Also MOSFET gate driver loss should be consid-
ing the gate capacitor and is dissipated in driver
...(25)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS
is the high side gate source voltage, and V
LGS
low side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2142, the current limit is decided by
D
the R
of the low side mosfet. When synchronous
DSON
FET is on, and the voltage on SW pin is below 320mV,
the over current occurs. The over current limit can be
calculated by the following equation.
=
SETDSON
The MOSFET R
is calculated in the worst
DSON
case situation, then the current limit for MOSFET
STM6912 is
320mV320mV
===
SET
R1.257m
DSON
×Ω
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en-
R
vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
is the
Rev. 1.1
10/28/07
17
Page 18
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-
cally touching the drain pin of the upper MOSFET, a
plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane ans as close as possible. A snubber nedds to be
placed as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2142/2142A
Rev. 1.1
10/28/07
18
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