Datasheet nx2141ds, nx2141 Datasheet

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Page 1

NX2141

SINGLE CHANNEL MOBILE PWM CONTROLLER WITH

FEEDFORWARD AND ENABLE

ADVANCE DATA SHEET

Pb Free Product

DESCRIPTION

The NX2141 controller IC is a compact synchronous Buck controller IC designed for step down DC to DC converter applications with voltage feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2141 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the regulator off until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The NX2141 employs fixed current limiting and FB UVLO followed by hiccup feature. Other features includes: 5V gate drive capability , Adaptive dead band control, available in 16 lead MLPQ and 10 lead MSOP package.

Vin1

+8 to 20V

100uF

Vin2

+5V

1nF

OFF

2.3k

15nF

1uF

10k

PVCC

VCC

PGOOD

COMP

Pgnd

VIN

NX2141

Gnd

BST

Hdrv

Ldrv

FEATURES

n Bus voltage operation from 7V to 24V n Less than 1uA shutdown current with Enable low n Excellent dynamic response with input voltage feed-

forward and voltage mode control

n Internal Digital Soft Start Function n Fixed internal hiccup current limit n FB UVLO followed by hiccup feature n Power Good indicator available n Start into precharged output n Pb-free and RoHS compliant

APPLICATIONS

n Notebook PC n Graphic Card on board converters n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n Set Top Box and LCD Display

1uH

MBR0530T1

0.1uF

TYPICAL APPLICATION

1uF

1uH

1.5k

2.2nF

25TQC33M 25V,33uF

10k

Vout

Co 2*2R5TPE220MC (220uF,12mohm)

+1.05V 10A

32k

Figure1 - Typical application of NX2141(MLPQ)

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free NX2141CMTR -40oC to 85oC MLPQ-16L 200kHz Yes NX2141CUTR -40oC to 85oC MSOP-10L 200kHz Yes

Rev. 1.6 05/15/07

Page 2

NX2141

θ≈46/

θ≈200/

ABSOLUTE MAXIMUM RATINGS

VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V

VIN to GND ........................................................ -0.3V to 30V

BST to GND Voltage .......................................... -0.3V to 35V

SW to GND ....................................................... -2V to 35V

All other pins ..................................................... -0.3V to 6.5V

Storage Temperature Range ................................ -65oC to 150oC

Operating Junction Temperature Range ................ -40oC to 125oC

ESD Susceptibility ............................................ 2kV

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

16-LEAD PLASTIC MLPQ 10-LEAD PLASTIC MSOP

COMP

VCC EN

HDRV PGND

LDRV

BST

VCC

PVCC

COMP

VIN

BST

HDRV

GND

LDRV

VIN

15 14

1 2

PGOOD

AGND

3 4

1 2 3 4 5

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =5V, VIN=12V and TA = -40oC to 85oC. Typical values refer to TA = 25oC.

PARAMETER SYM Test Condition Min TYP MAX Units

Reference Voltage

Ref Voltage V

REF

Ref Voltage line regulation 0.2 %

Supply Voltage(Vcc)

VCC Voltage Range V Operating quiescent current I Shut down current I

CC Q

EN=HIGH 1.5 EN=LOW

4.75 5.25

Vcc UVLO

VCC-Threshold VCC_UVLO VCC Rising VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V

Supply Voltage(Vin)

Vin Voltage Range V

7 25

Input Voltage Current Vin=24V 24 Shut Down Current EN=LOW

0.8

4.4

V 5 1

Rev. 1.6 05/15/07

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NX2141

(CL=3300pF)

Ldrv going Low to Hdrv going

PARAMETER SYM Test Condition Min TYP MAX Units

Vin UVLO

Vin-Threshold Vin_UVLO VCC Rising Vin-Hysteresis Vin_Hyst VCC Falling 0.5 V

Oscillator (Rt)

Frequency F Frequency Over Vin Ramp-Amplitude Voltage V

RAMP

200 KHz

-5

Vin=20V 2 V Ramp Offset 0.8 V Ramp/Vin Gain 0.1 V/V Max Duty Cycle Min on time

Error Amplifiers

Transconductance 2500 umho Input Bias Current Ib 100 nA Comp SD threshold 0.3 V

Vref and Soft Start

Soft Start time Tss FS=200kHz 10 mS

High Side Driver

88 %

150

(Hdrv) I=200mA

source

1 ohmOutput Impedance , Sourcing

Current Output Impedance , Sinking

(Hdrv) I=200mA

sink

ohm0.8

Current Rise Time THdrv(Rise) 10% to 90% 50 ns

Fall Time THdrv(Fall) 90% to 10% 50 ns Deadband Time

Low Side Driver

Tdead(L to

High, 10% to 10%

ns30

(CL=3300pF)

Output Impedance, Sourcing

(Ldrv) I=200mA 1 ohm

source

Current Output Impedance, Sinking

(Ldrv) I=200mA 0.5 ohm

sink

Current Rise Time TLdrv(Rise) 10% to 90% 50 ns

Fall Time TLdrv(Fall) 90% to 10% 50 ns

nsDeadband Time Tdead(H to L)SW going Low to Ldrv going

High, 10% to 10%

Fixed OCP

OCP voltage Threshold 320 mV

Enable

Enable HI Threshold

1.4

Enable LOW Threshold

0.4

Rev. 1.6 05/15/07

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NX2141

Vref

PARAMETER SYM Test Condition Min TYP MAX Units

Power Good(MLPQ only)

Threshold Voltage as % of Hysteresis 5 %

FBUVLO

Feedback UVLO threshold percent of nominal

Over temperature

Threshold Hysteresis 20 °C

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

This pin supplies the internal 5V bias circuit. A 1uF ceramic capacitor is placed as

VCC

BST

close as possible to this pin and ground pin. This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic

capacitor is placed as close as possible to and connected to this pin and SW pin.

FB ramping up 90 %

150

°C

GND

COMP

HDRV

LDRV

VIN

Power ground. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to

the output of the switching regulator to set the output DC voltage.

This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop.

This pin is connected to source of high side FETs and provide return path for the high side driver.

High side gate driver output. Low side gate driver output.

Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down the controller and resets the soft start.

Bus voltage input provides power supply to oscillator and VIN UVLO signal.

Rev. 1.6 05/15/07

PGOOD

(MLPQ only)

PVCC

An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage, PGOOD changes from LO to HI state.

Supply voltage for the low side fet drivers. A high frequency 1uF ceramic cap must be connected from this pin to the PGND pin as close as possible.

Page 5

BLOCK DIAGRAM

NX2141

VCC

VIN

COMP

6V/

5.5V

Bias Generator

COMP

0.3V

START

Digital start Up

0.8V

ramp

START

1.25V

0.8V

VIN

OSC

0.6V CLAMP

UVLO

1.3V CLAMP

0.85Vref /0.90Vref

POR

START

Control Logic

PWM

DISABLE

POR

320mV

Hiccup Logic

OCP comparator

PGOOD

BST

HDRV

PVCC

LDRV

PGND

Rev. 1.6 05/15/07

AGND

DISABLE

SS_half_done

Figure 2 - Simplified block diagram of the NX2141(MLPQ)

70%*Vp

Page 6

NX2141

Vin1

+8 to 20V

100uF

Vin2

+5V

1nF

2.3k

15nF

1uF

10k

PVCC

VCC

PGOOD

0.1uF

COMP

Pgnd

VIN

NX2141

Gnd

BST

Hdrv

Ldrv

1uH

MBR0530T1

0.1uF

1uF

1uH

1.5k

2.2nF

25TQC33M 25V,33uF

10k

32k

Vout

Co 2*2R5TPE220MC (220uF,12mohm)

+1.05V 10A

Rev. 1.6 05/15/07

Figure 3 - Simplified Demo board schematic(MLPQ)

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NX2141

Rev. 1.6 05/15/07

Figure 4 - Demo board schematic based on ORCAD

Page 8

Bill of Materials

Item number Quantity Reference Part Manufacturer

1 4 C1,C5,C6,C18 0.1u 2 4 C2,C4,C7,C9 1u 3 1 C3 25TQC33M SANYO 4 2 C19,C8 47u 5 1 C10 15nF 6 1 C13 1000pF 7 1 C14 2.2n 8 1 C15 470p

9 2 C17,C16 2R5TPE220MC SANYO 10 1 D1 MBR0530T1 11 1 L2 MLC1550-102ML Coilcraft 12 1 M1 FDS6294 Fairchildsemi 13 1 M2 FDS6676AS Fairchildsemi 14 4 R1,R2,R3,R11 0 15 3 R4,R6,R14 10 16 1 R5 100k 17 1 R8 2.3k 18 1 R10 32k 19 1 R12 10k 20 1 R13 1.5k 21 1 R15 1k 22 1 U1 NX2141CMTR NEXSEM INC. 23 1 U2 L78L05AB/sot89

NX2141

Rev. 1.6 05/15/07

Page 9

Demoboard waveforms

NX2141

Figure 5 - Output ripple(CH1 Vout ripple(50mV/ div),CH2 output current(5A/div), CH3 SW(5V/div))

Figure 7 - Enlarged transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div))

Figure 6 - Transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div))

Figure 8 - Enlarged transient response(CH1 Vout AC(50mV/div), CH2 output current(5A/div))

Figure 9 - Over Current Protection(CH2 output current(10A/ div), CH4 VOUT(500mV/div))

Rev. 1.6 05/15/07

Figure 10 - Power Good(CH4 Vout(500mV/div), CH3 PGOOD(5V/div))

Page 10

Demoboard waveforms(cont'd)

NX2141

Figure 11 - Step VIN response(CH1 Vout AC(50mV/ div), CH3 VIN(5V/div), CH4 SW(5V/div))

Figure 13 - Step into precharged output (CH1 EN (2V/ div), CH3 OUTPUT CURRENT(10A/div), CH4 VOUT(500mV/div))

Efficiency(%)

89.00%

88.00%

87.00%

86.00%

85.00%

84.00%

83.00%

82.00%

81.00%

80.00%

79.00%

efficinecy vs Iout(VIn=12V)

0 2 4 6 8 10 12

Iout(A)

Figure 12 - Enlarged Figure 11 (CH1 Vout AC(50mV/ div), CH3 VIN(5V/div), CH4 SW(5V/div))

Figure 14 - Soft start(CH1 EN(2V/div),CH2 output current(10A/div), CH3 VOUT(500mV/div))

86.00%

84.00%

82.00%

80.00%

78.00%

Efficiency(%)

76.00%

74.00%

efficinecy vs Iout(VIn=19V)

0 2 4 6 8 10 12

Iout(A)

Figure 15 - Efficiency(VIN=12V, VOUT=1V)

Rev. 1.6 05/15/07

Figure 16 - Efficiency(VIN=19V, VOUT=1V)

Page 11

APPLICATION INFORMATION

RIPPLEINMAXS

IVF

0.410A20V200kHz

=4.97A

SOUT

ESR=6m

==Ω

ERIPPLE

12m4.97A

NX2141

Current Ripple @ maximum input voltage is

calculated as

Symbol Used In Application Information:

VIN - Input voltage VOUT - Output voltage IOUT - Output current DVRIPPLE - Output voltage ripple FS - Switching frequency DIRIPPLE - Inductor current ripple

Design Example

Power stage design requirements: VINMIN=8V VINMAX=20V VOUT=1.05V IOUT_max =10A DVRIPPLE <=30mV DVTRAN<=50mV @ 5A step FS=200kHz

Output Inductor Selection

The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:

V-VV

INMAXOUT OUT

OUT

I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.4, then

L= L=1.2uH

In this application we choose LOUT=1uH, then coilcraft inductor MLC1550-102MLC is a good choice.

20V-1.05V1.05V1

OUT

××

...(1)

××

V-VV

RIPPLE

INOUT OUT

20V-1.05V1.05V1

××

LVF

OUTINS

1uH20V200kHz

××=

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load condition is determined by equation(3).

∆

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent series resistance,C

is the value of output capacitors.

OUT

Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected.

For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.

desire

∆

RIPPLE

I4.97A

∆

RIPPLE

30mV

If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 30mV output ripple, POSCAP 2R5TPE220MC with 12mΩ are chosen.

ESRI

∆

×∆

RIPPLE

Number of Capacitor is calculated as

Ω×

30mV

N =2

The number of capacitor has to be round up to a integer. Choose N =2.

RIPPLE

××

8FC

...(3)

...(4)

...(5)

Rev. 1.6 05/15/07

Page 12

NX2141

8200kHz200uF

tran

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

=+×τ

EEcrit

ESRCifLL

0.55H

=µ

12m220F2.12us

(2.12us)

If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors.

For example, two 100uF, X5R ceramic capacitor

with 2mΩ ESR is used. The amount of output ripple is

V1m4.97A

∆=Ω×+

RIPPLE

5mV15mV20mV

=+=

Two ceramic capacitors are needed. Although this can meet DC ripple spec, however it needs to be stud-

ied for transient requirement.

Based On Transient Requirement

Typically, the output voltage droop during transient is specified as

∆V

droop

∆V

@step load DI

During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a DI

transient load, if assuming the bandwidth of

STEP

system is high enough, the overshoot can be estimated as the following equation.

VESRI

overshootstep

2LC

where τ is the a function of capacitor,etc.

0ifLL

 

×∆

τ=

 

OUT



≤

crit

step

−×≥

where

ESRCVESRCV

××××

∆∆

stepstep

crit

where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel.

4.97A

××

STEP

OUT

××

OUT

...(6)

...(7)

...(8)

The above equation shows that if the selected output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and ca-

pacitance is high and

≤ is true. In that case, the

transient spec is mostly like to dependent on the ESR of capacitor.

Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following

ESRI

×∆

Estep

V2LCV

∆×××∆

tranEtran

OUT

...(9)

where

0ifLL

 

×∆

τ=

 

OUT



≤

crit

step

−×≥

...(10)

For example, assume voltage droop during transient is 50mV for 5A load step.

If the POSCAP 2R5TPE220MC(220uF, 12mohm ESR) is used, the crticial inductance is given as

ESRCV

××

EEOUT

∆

step

Ω×µ×

crit

12m220F1.05V

The selected inductor is 1uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.

number of capacitor is

×∆

step

τ=−×

OUT

1H5A

µ×

=−Ω×µ=

1.05V

ESRI

×∆

=+×τ

12m5A1.05V

=+×

1.35

Estep

V2LCV

∆×××∆

Ω×

53mV21H220F53mV

ESRC

OUT

tranEtran

×µ×µ×

Rev. 1.6 05/15/07

Page 13

NX2141

F ...(11)

F ...(12)

F ...(13)

F ...(14)

OUT minin1

V1gZZ/R

OUT in

−

The number of capacitors has to satisfy both ripple

and transient requirement. Overall, we choose N=2.

It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters.

Compensator Design

Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen.

Voltage feedforward compensation is used in NX2141 to compensate the output voltage variation caused by input voltage changing. The feedforward funtion is realized by using VIN pin voltage to program the oscillator ramp voltage V

=0.1VIN, which provides nearly

OSC

constant power stage gain under wide voltage input range.

A. Type III compensator design

For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen-

sate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.

×π××

2RC

×π×+×

2(RR)C

233

×π××

2RC

×π××

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator for

transconductance amplifier is given by:

V 1gZ

e mf

−×

+×+

For the voltage amplifier, the transfer function of compensator is

To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.

Zin

Vout

Vref

Figure 17 - Type III compensator using

transconductance amplifier

Rev. 1.6 05/15/07

Page 14

NX2141

21uH440uF

26m440uF

20.757.59kHz2.5k

×π×××Ω

22.5k66.7kHz

1215kHz1uH440uF

=1.7nF

260.3kHz2.2nF

()

22.2nF7.59kHz60.3kHz

Case 1: FLC<FO<F ESR POSCAP, OSCON)

power stage

Gain(db)

loop gain

compensator

Z1 Z2

(for most ceramic or low

ESR

40dB/decade

ESR

20dB/decade

2. Set R4 equal to 2.5kΩ.

3. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

2FR

×π××

Z14

11nF

Choose C2=15nF.

4. Calculate C1 by equation (14) with pole Fp2 at

one third of the switching frequency.

≈

959pF

≈

2RF

×π××

4P2

×π×Ω×

Choose C1=1nF.

5. Calculate C

with the crossover frequency FO at

15kHz.

Figure 18 - Bode plot of Type III compensator

(FLC<FO<F

ESR

)

Typical design example of type III compensator in which the crossover frequency is selected as FLC<FO<F

and FO<1/10 is shown as the following

ESR

steps.

1. Calculate the location of LC double pole F

and ESR zero F

ESR

2LC

×π××

OUTOUT

×π××

7.59kHz

ESR

2ESRC

×π××

×π×Ω×

60.3kHz

OUT

V2FLC

OSCOOUT

102.5k

×π×××

IN4

×π×××

Ω

Choose C3=2.2nF.

6. Calculate R3 by equation (13) with Fp1 =F

2FC

×π××

P13

×π××

1.2k

=Ω

Choose R3 =1.5kΩ.

7. Calculate R2 by setting compensator zero F

at the LC double pole.

R()

8.35k

111

=×−

2CFF

×π×

3Z2P1

=×−

111

×π×

=Ω

ESR

Rev. 1.6 05/15/07

Choose R2 =10kΩ.

Page 15

NX2141

22.2uH2000uF

29m2000uF

20.752.4kHz2.5k

×π×××Ω

22.5k66.7kHz

215kHz1uH

×Ω

28.8kHz1.2k

×π××Ω

R=32k

==Ω

8. Calculate R1 .

2REF

V-V1.05V-0.8V

OUT REF

Choose R1=32kΩ.

Case 2: FLC<F

power stage

Gain(db)

loop gain

compensator

10k0.8V

Ω×

(for electrolytic capacitors)

ESR<FO

40dB/decade

ESR

20dB/decade

ESR

2ESRC

8.8kHz

×π××

OUT

×π×Ω×

2. Set R4 equal to 2.5kΩ.

3. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

2FR

×π××

Z14

35nF

Choose C2=33nF.

4. Calculate C1 by equation (14) with pole Fp2 at

one third of the switching frequency.

≈

959pF

≈

2RF

×π××

4P2

×π×Ω×

Z1 Z2

Figure 19- Bode plot of Type III compensator

(FLC<F

ESR<FO

)

If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<F

and FO<1/10Fs is shown as

ESR<FO

the following steps. Here two SANYO MV-WF1000 with 18 mΩ is chosen as output capacitor, output inductor is

2.2uH, output voltage is 1.05V, switching frequency is 200kHz.

1. Calculate the location of LC double pole F

and ESR zero F

ESR

2LC

×π××

OUTOUT

×π××

2.4kHz

Choose C1=1nF.

5. Calculate R

with the crossover frequency FO at

15kHz.

VESRR

IN4

=10 =1.08k

V2FL

OSCO

9mohm2.5k

×π××

Ω

×π××

Choose R3=1.2kΩ.

6. Calculate C3 by equation (13) with Fp1 =F

2FR

×π××

P13

14nF

Choose C3 =15nF.

7. Calculate R2 by setting compensator zero F

at the LC double pole.

ESR

Rev. 1.6 05/15/07

Page 16

NX2141

Gain=gR ...(15)

F= ... (16)

F ... (17)

22.2uH1360uF

220.5m1360uF

()

215nF2.4kHz8.8kHz

R=12.8k

==Ω

R()

=×−

3.2k

=Ω

111

=×−

2CFF

×π×

3Z2P1

111

×π×

Choose R2 =4kΩ.

8. Calculate R1 .

2REF

V-V1.05V-0.8V

OUT REF

4k0.8V

Ω×

Choose R1=12.7kΩ.

B. Type II compensator design

If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system.

For this type of compensator, FO has to satisfy FLC<F

<<FO<1/10F

ESR

The following equations show the compensator pole zero location and constant gain.

××

R+R

2RC

×π××

≈

2RC

×π××

Vout

Vref

power stage

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

ESR

Figure 20 - Bode plot of Type II compensator

Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 15. R and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise.

Figure 21 - Type II compensator with transconductance amplifier

The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are two 680uF with 41mΩ electrolytic capacitors.

1.Calculate the location of LC double pole F

and ESR zero F

ESR

×π××

2LC

OUTOUT

×π××

2.9kHz

OUT

×π×Ω×

ESR

5.7kHz

×π××

2ESRC

= =

Rev. 1.6 05/15/07

Page 17

NX2141

1020.5m2.5mA/V

21k0.752.9kHz

1k300kHz

OUT

REF

2REF

OUT REF

IID1-D

1.Set R2 equal to10kΩ. Using equation 18, the fi-

nal selection of R1 is 4.7kΩ.

2. Set crossover frequency at 1/20 of the

swithing frequency, here FO=10kHz.

3.Calculate R3 value by the following equation.

V2FLV

OSCOOUT

VRgV

1210kHz2.2uH1

=0.8k

Choose R

4. Calculate C1 by setting compensator zero F

×π××

×××

inESRmREF

×π××

××

2.5V

0.8V

Ω

=1kΩ.

at 75% of the LC double pole.

2RF

×π××

×π×Ω××

=70nF

Choose C1=68nF.

5. Calculate C2 by setting compensator pole

at half the swithing frequency.

π××

π×Ω×

=530pF

Choose C2=560pF.

Output Voltage Calculation

Output voltage is set by reference voltage and ex-

ternal voltage divider. The reference voltage is fixed at

0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 22, which shows the relationship between

V ,

V and voltage divider..

Vout

Vref

Figure 22 - Voltage divider

where R

V-V

is part of the compensator, and the value

...(18)

of R1 value can be set by voltage divider.

Input Capacitor Selection

Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated

as:

=××

RMSOUT

VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of input RMS current is 3.4A.

For higher efficiency, low ESR capacitors are recommended. One Sanyo OSCON CAP 25SVP56M 25V 56uF 28mΩ with 3.8A RMS rating are chosen as input bulk capacitors.

OUT

INMIN

...(19)

Rev. 1.6 05/15/07

Page 18

NX2141

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

I320mV/R

I35A

×−××

P=I(1D)RK

SWINOUTSWS

PVITF

=××××

Power MOSFETs Selection

The NX2141 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter

efficiency. For example, two IRF7822 are used in application. They have the following parameters: VDS=30V, I

=18A,R

loss:conduction loss, switching loss.

where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to datasheet. Conduction loss should not exceed package rating or overall system thermal budget.

conduction at the switching transition. The total switching loss can be approximated.

where IOUT is output current, TSW is the sum of T and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent.

ered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as:

charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and V side gate source voltage.

=6.5mΩ,Q

DSON

GATE

=44nC.

There are two factors causing the MOSFET power

Conduction loss is simply defined as:

P=IDRK

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

×××

...(20)

Switching loss is mainly caused by crossover

1 2

...(21)

Also MOSFET gate driver loss should be consid-

...(22)

where QHGATE is the high side MOSFETs gate

is the low

LGS

This power dissipation should not exceed maxi-

mum power dissipation of the driver device.

Over Current Limit Protection

Over current Limit for step down converter is achieved by sensing current through the low side MOSFET. For NX2141, the current limit is decided by the R FET is on, and the voltage on SW pin is below 320mV,

of the low side mosfet. When synchronous

DSON

the over current occurs. The over current limit can be calculated by the following equation.

SETDSON

The MOSFET R

is calculated in the worst case

DSON

situation, then the current limit for MOSFET IRF7822 is

320mV320mV

===

SET

R1.46.5m

DSON

×Ω

Layout Considerations

The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results.

There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to

sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended .

Layout guidelines:

1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them.

2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling ceramic cap which usually is 1uF need to be practically touch-

Rev. 1.6 05/15/07

Page 19

ing the drain pin of the upper MOSFET, a plane connection is a must.

3. The output capacitors should be placed as close as to the load as possible and plane connection is required.

4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible.

5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider.

8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals.

9. All GNDs need to go directly thru via to GND plane.

10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC.

11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.

NX2141

Rev. 1.6 05/15/07

Page 20

MLPQ 16 PIN 3 x 3 PACKAGE OUTLINE DIMENSIONS

NX2141

NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.

Rev. 1.6 05/15/07

Page 21

MLPQ 16 PIN 3 x 3 TAPE AND REEL INFORMATION

NX2141

Rev. 1.6 05/15/07

NOTE:

1. R7 = 7 INCH LOCK REEL, R13 = 13 INCH LOCK REEL.

2. ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.