Datasheet nx2130ds Datasheets

Evaluation board available.

NEXSEM

SINGLE CHANNEL MOBILE PWM CONTROLLER

DESCRIPTION

The NX2130 controller IC is a compact Buck controller
IC with 16 lead MLPQ package designed for step down
DC to DC converter in portable applicaitons. It can
be selected to operate in synchronous mode for con­tinuous fixed PWM or non-synchronous mode to im­prove the efficiency at light load.Voltage feedforward
provides fast response, good line regulation and nearly
constant power stage gain under wide voltage input
range. The NX2130 controller is optimized to convert
single supply up to 24V bus voltage to as low as 0.8V
output voltage. Internal UVLO keeps the regulator off
until the supply voltage exceeds 4.5V where internal
digital soft starts get initiated to ramp up output. Over
current protection and FB UVLO followed by latch off
feature. Other features includes: 5V gate drive capa­bility, power good indicator, over voltage protection,
output and adaptive dead band control.

NX2130

WITH PFM AND PWM MODE

PRELIMINARY DATA SHEET

Pb Free Product

FEATURES

n Bus voltage operation from 7V to 25V
n Less than 1uA shutdown current with Enable low
n Excellent dynamic response with input voltage

feed-forward and voltage mode control-PFM mode

n Selectable between Synchronous CCM and PWM/

PFM mode to improve efficiency at light load

n Fixed 300kHz switching frequency
n Internal Digital Soft Start Function
n Programmable current limit with latch off
n Over voltage protection with latch off
n FB UVLO with latch off
n Power Good indicator available
n Pb-free and RoHS compliant
n Output soft discharge
n Internal BST schottky diode

APPLICATIONS

n Notebook PCs and Desknotes
n Tablet PCs/Slates
n On board DC to DC such as

12V to 3.3V, 2.5V or 1.8V

n Hand-held portable instruments

TYPICAL APPLICATION

16

5V

PATENT PENDING

PGOOD

12

PVCC

10

PAD

2

3

4

5
6

VCC

GND

FCCM

EN

COMP

FB

VSENSE

8

N X 2 1 3 0

Vref_OC

Vp

7

Figure1 - Typical application of NX2130

VIN

DrvH

BST

SW

DrvL

PGND

1

14
13

15

11

10

9

VIN 7V~25V

Vout 0.8~3.3V

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX2130CMTR -10oC to 100oC MLPQ-16L 300kHz Yes

Rev. 1.4
03/24/07

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1

NEXSEM

CW

θ≈46/

NX2130

ABSOLUTE MAXIMUM RATINGS

VCC,PVCC to GND & BST to SW voltage ............ -0.3V to 6.5V

VIN to GND .......................................................... -0.3V to 25V

HDRV to SW Voltage .......................................... -0.3V to 6.5V

SW to GND ......................................................... -2V to 30V

All other pins ........................................................ VCC+0.3V

Storage Temperature Range ..................................-65oC to 150oC

Operating Junction Temperature Range .................-40oC to 125oC

ESD Susceptibility ............................................... 2kV

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

16-LEAD PLASTIC MLPQ

o

VIN

VCC

FCCM

EN

JA

PGOOD

SW

HDRV

BST

7

VP

13

8

VSENSE

12
11

10

9

PVCC

LDRV

PGND

VREF-OC

16

15 14

1
2
3
4

5

COMP

17

AGND

6

FB

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical
values refer to TA = 25oC.

PARAMETER SYM Test Condition Min TYP MAX Units

Supply Voltage(Vcc)

VCC Voltage Range V
Operating quiescent current I
VCC Shut down current I

Vcc UVLO

VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V

Rev. 1.4
03/24/07

CC
Q

SD

EN=HIGH 2
EN=LOW

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4.75 5.25

1

4.4

V

mA

uA

V

2

NEXSEM

Logic input high

1.4

V

Ldrv going Low to Hdrv going

NX2130

PARAMETER SYM Test Condition Min TYP MAX Units

Supply Voltage(Vin)

Vin Voltage Range V
Input Voltage Current Vin=24V 24 uA

Vin Shut Down Current EN=LOW

Vin UVLO

Vin-Threshold Vin_UVLO VCC Rising
Vin-Hysteresis Vin_Hyst VCC Falling 0.2 V

Oscillator (Rt)

Frequency F
Ramp Offset 0.5 V
Ramp/Vin Gain 0.4 V/V
Max Duty Cycle
Min on time

Error Amplifiers

open loop gain
Input Bias Current Ib 100 nA

maximum soucring current FB=GND 2 mA
maximum sinking current FB=VCC 300 uA

offset voltage 0 mV
COMP High voltage FB=0.4, Vp=0.8V, sink 40uA 3.5 V

in

S

5.5 24

1

70 DB

4.5

300 KHz

90 %

150

V

uA

V

nS

COMP low voltage source 80uA 0.1 V

Vref and Soft Start

Internal Reference voltage
reference accuracy -1 1 %
Soft Start time Tss 1.6 mS

SW zero cross comparator

offset voltage

N

Enable

Enable input high
Enalble input low 0.4 V

FCCM

Logic input low 0.4 V

High Side

R

(Hdrv) I=200mA

source

Current
Output Impedance , Sinking

Current
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(L to

R

(Hdrv) I=200mA ohm0.8

sink

H)

High, 10% to 10%

1.4

3

5

1 ohmOutput Impedance , Sourcing

30 ns

V

mV

V

Rev. 1.4
03/24/07

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3

NEXSEM

Hysteresis

5

%

FB Under Voltage

Current Limit

Over Voltage

Over temperature

NX2130

PARAMETER SYM Test Condition Min TYP MAX Units

Low Side Driver

Output Impedance, Sourcing
Output Impedance, Sinking
Rise Time TLdrv(Rise) 10% to 90% 50 ns

Fall Time TLdrv(Fall) 90% to 10% 50 ns

Power Good(Pgood)

Threshold Voltage as % of
Vref

FB Threshold 70 %*Vp
Time Delay 3 cycle

R

(Ldrv) I=200mA 1 ohm

source

R

(Ldrv) I=200mA 0.5 ohm

sink

10 nsDeadband Time Tdead(H to L)SW going Low to Ldrv going

High, 10% to 10%

FB ramping up 90 %

Ocset setting current 100k from VREF_OC to

GND

Over Voltage Trip Point 120 %Vref
Hysteresis 8 %Vref
Over Voltage Delay 2 cycle

Threshold 150 °C
Hysteresis 20 °C

30

uA

Rev. 1.4
03/24/07

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4

NEXSEM

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

This pin supplies the internal 5V bias circuit. A 1uF ceramic capacitor is placed as

VCC

BST

close as possible to this pin and ground pin.
This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic

capacitor is placed as close as possible to and connected to this pin and SW pin.

NX2130

PGND

FB

COMP

SW

HDRV

LDRV

EN

VIN

PGOOD

Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor

divider to the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to compen-

sate the voltage control feedback loop.
This pin is connected to source of high side FETs and provide return path for the high

side driver. It is also used to hold the low side driver low until this pin is brought low
by the action of high side turning off.

High side gate driver output.
Low side gate driver output.
Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts

down the controller and resets the soft start.
Bus voltage input provides power supply to oscillator and VIN UVLO signal.
An open drain output that requires a pull up resistor to Vcc or a voltage lower than

Vcc. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO
to HI state.

Rev. 1.4
03/24/07

FCCM

VSENSE

VREF_OC

VP
PVCC
AGND

Forced CCM operation. Pull this pin high will force step down converter works at
synchronous mode. Pull this pin low, the PWM controller with work at either synchro­nous PWM mode or Pulse frequency modulation (PFM) mode depending on the load
condition.

Voltage sensing pin.
Reference output voltage. A resistor from this pin to ground also set the current limit

threshold.
Output voltage indicator. This pin should set to be half of the desired output voltage.
Provide the voltage supply to the lower MOSFET drivers.
Analog ground.

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NEXSEM

BLOCK DIAGRAM

NX2130

VCC

Vref_OC

VIN

EN

Vp

FB

COMP

FCCM

Bias

POR

shut down

SS_finished

Iocset

start

1.25

3V

OSC

DAC

Mode
selection

mode

4.4/4.2

4.4/4.2

VIN

2.62/2.5

start

Vsen

MODE

Control
Logic

POR

UVLO

CLK

PWM/PFM

POR

start ODB

HD

Current
Limit
Logic

FET Driver

HD_IN

SW_high

Vref_OC

R

Q

S

HD

BST

DrvH

SW

PVCC

DrvL

PGND

8k

OCset

VIN

5V

Rev. 1.4
03/24/07

GND

PGOOD

OVP

SS_finished

1.2*Vref/0.75*Vref
FB

0.9*Vref

PORB

60ohm

Figure 2 - Simplified block diagram of the NX2130

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Vsen

6

NEXSEM

BUS

GND 1

1

BUS

C10
100u/35V

R21
open

Li

1 2

DO1813-561HC

NX2130

CI1

VDD

25TQC33M

CI2

VCC

1

C11
47u

VCC

FCCM

3

1

OUT

C13

10u/25V

4

SW

4

VCC

d

M5
2N7002

s

R14

26.1k

25TQC33M

4

56789

M1

BSC119N03S

123

56789

M3

BSC032N03S

123

4

R24

10.5k

JP2

123

123

56789

M2

56789

M4

1 2

C14

10u/25V

BSC119N03S

R15
10

C9
470p

BSC032N03S

g

R22
100k

Lo

1 2

0.33uH

Panasonic

D3

open

d

M6
2N7002

s

R20
51k

1

5

JSW

234

2R5TPE330MC

RL
1k

C5

3.3n
R9

3.24k

R10

17.4k

2R5TPE330MC

OUT

CO1

R8

1.2k

R25

C12

0.1u

0

1

CO2

GNDOUT

JOUT

5

VOUT

234

C6

1

U1

R11

16

12

C16
1u

2

C2
1u

4

C18
1u

3

9

R12
118k

7

R13

22.1k

8

PGOOD

PVCC

VCC

EN

FCCM

VREF-OC

VP

VSENSE

100k

R6

10

3

EN

2

1

2

R18

SW

open

C7

1n

C8

open

C15

open
R5

0

1u

VIN

HDRV

NX2130/MLPQ-16/4x4

COMP

PGND

AGND

10

17

BST

SW

LDRV

FB

VCC

3

D4
open

1

2

13

R19

0
C17
open

C1

0.1u

1

C4
150p

R17

10.5k

JP1

2

3

R2

0

R23

0

D2
BAT54A

R4

0

R7

6.65k

C3

2.7n

1 2

g

R16
100k

14

15

11

6

5

Figure 3- Demo board schematic based on ORCAD (VIN=7V to 20V,VOUT=1.1,IOUT=30A)

Rev. 1.4
03/24/07

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NEXSEM

Bill of Materials

Item Quantity Reference Value Manufacture

1 2 CI1,CI2 25TQC33M SANYO
2 2 CO1,CO2 2R5TPE330MC SANYO
3 2 C1,C12 0.1u
4 4 C2,C6,C16,C18 1u
5 1 C3 2.7n
6 1 C4 150p
7 1 C5 3.3n
8 1 C7 1n

9 1 C9 470p
10 1 C10 100u/35V
11 1 C11 47u
12 2 C13,C14 10u/25V
13 1 Li DO1813-561HC COILCRAFT
14 1 Lo 0.33uH PANASONIC
15 2 M1,M2 BSC119N03S INFINEON
16 2 M3,M4 BSC032N03S INFINEON
17 2 M5,M6 2N7002
18 1 RL 1k
19 6 R2,R4,R5,R19,R23,R25 0
20 2 R6,R15 10
21 1 R7 6.65k
22 1 R8 1.2k
23 1 R9 3.24k
24 1 R10 17.4k
25 3 R11,R16,R22 100k
26 1 R12 118k
27 1 R13 22.1k
28 1 R14 26.1k
29 2 R17,R24 10.5k
30 1 R20 51k
31 1 U1 NX2130/MLPQ-16 NEXSEM INC.

NX2130

Rev. 1.4
03/24/07

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8

NEXSEM

Demoboard waveforms

NX2130

Figure 4 - PWM mode

Figure 6 - Soft start

Figure 5 - PFM mode

Figure 7 - Soft shutdown

Figure 8 - Step response(PWM mode)

Rev. 1.4
03/24/07

Figure 9 - Step response(PFM and PWM transition)

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9

NEXSEM

NX2130

Figure 10 - Step Response(PFM only)

90.00%

85.00%

80.00%

75.00%

70.00%

65.00%

60.00%

55.00%

50.00%
0 10 20 30 40

Figure 12 - Efficiency vs IOUT @ PWM mode
(VOUT=1.1V)

VIN=7V
VIN=12V
VIN=19.5V

Figure 11 - Over Current Protection

(A)

Rev. 1.4
03/24/07

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10

NEXSEM

RIPPLEINS

1

IVF

0.430A12V300kHz

=10A

SOUT

ESR=2m

==Ω

ERIPPLE

12m10A

NX2130

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Switching frequency
DIRIPPLE - Inductor current ripple

Design Example

Power stage design requirements:
VIN=12V
VOUT=1.1V
IOUT =30A
DVTRAN<=50mV @ 5A step
FS=300kHz

Output Inductor Selection

The selection of inductor value is based on in­ductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:

V-VV

L=
I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.25, then

L=

OUT

L=0.28uH

OUT

Choose LOUT=0.33uH.

Current Ripple is calculated as

INOUT OUT

OUT

×

12V-1.1V1.1V1

×

××

××

...(1)

V-VV

I=

RIPPLE

INOUT OUT

LVF

12V-1.1V1.1V1

0.33uH12V300kHz

××

OUTINS

××=

1

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specifica­tion for the load transient. The optimum design may
require a couple of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C
tors.

Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.

For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically de­termines the output voltage ripple.

∆

tiple capacitors in parallel are better than a big capaci­tor. For example, for 50mV output ripple, POSCAP
2R5TPE330MC with 12mΩ are chosen.

integer. Choose N =2.

desire

If low ESR is required, for most applications, mul-

ESRI

N

=

Number of Capacitor is calculated as

N

N =2.4

The number of capacitor has to be round up to a

Ω×

=

50mV

is the value of output capaci-

OUT

V

RIPPLE

I10A

∆

RIPPLE

×∆

V

∆

RIPPLE

20mV

RIPPLE

××

8FC

...(5)

...(3)

...(4)

Rev. 1.4
03/24/07

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11

NEXSEM

tran

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.6H

=µ

12m330F1.86us

2

(0)

NX2130

If ceramic capacitors are chosen as output ca­pacitors, both terms in equation (3) need to be evalu­ated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capaci­tance per single unit is not sufficient to meet the tran­sient specification, which results in parallel configura­tion of multiple capacitors.

Based On Transient Requirement

Typically, the output voltage droop during tran­sient is specified as

∆V

droop

During the transient, the voltage droop during
the transient is composed of two sections. One sec­tion is dependent on the ESR of capacitor, the other
section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the
overshoot when load from high load to light load
with a DI
width of system is high enough, the overshoot can
be estimated as the following equation.

STEP

∆V

<

transient load, if assuming the band-

@step load DI

STEP

that case, the transient spec is mostly like to depen­dent on the ESR of capacitor.

Most case, the output capacitor is multiple ca­pacitor in parallel. The number of capacitor can be cal­culated by the following

ESRI

×∆

N

where




τ=

sient is 50mV for 5A load step.

ESR) is used, the crticial inductance is given as






For example, assume voltage droop during tran-

If the POSCAP 2R5TPE330MC(330uF, 12mohm

Estep

V2LCV

∆×××∆

tranEtran

0ifLL

LI

×∆

V

OUT

L

crit

12m330F1.1V

≤

crit

step

−×≥

ESRCV

××

EEOUT

==
Ω×µ×

5A

I

∆

step

V

OUT

...(9)

...(10)

V

VESRI

tance of each capacitor if multiple capacitors are used
in parallel.

output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency ca­pacitor such as electrolytic capacitor, the product of

ESR and capacitance is high and

overshootstep

where τ is the a function of capacitor,etc.

0ifLL




LI

×∆

τ=




V

OUT



where

ESRCVESRCV

L

==

crit

where ESRE and CE represents ESR and capaci-

The above equation shows that if the selected

≤

crit

step

−×≥

××××

II

∆∆

stepstep

OUT

2LC

××

OUT

...(6)

...(7)

...(8)

≤ is true. In

The selected inductor is 0.33uH which is smaller
than critical inductance. In that case, the output volt­age transient only dependent on the ESR.

number of capacitor is

LI

×∆

step

τ=−×

V

and transient requirement. Overall, we choose N=2.

0.33H5A

µ×

=−Ω×µ=−

1.1V

ESRI

N

=+×τ

∆×××∆

12m5A1.1V

Ω×

=+×

50mV20.33H330F50mV

1.82

=

The number of capacitors has to satisfy both ripple

It should be considered that the proposed equa-

ESRC

OUT

×∆

Estep

V2LCV

tranEtran

EE

V

OUT

×µ×µ×

2

Rev. 1.4
03/24/07

www.nexsem.com

12

NEXSEM

F ...(11)

F ...(12)

F ...(13)

F ...(14)

[

]

42233

(1sRC)1s(RR)C

NX2130

tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more ca­pacitors have to be chosen after the test. Typically,
forhigh frequency capacitor such as high quality
POSCAP especially ceramic capacitor, 20% to 100%
(for ceramic) more capacitors have to be chosen since
the ESR of capacitors is so low that the PCB parasitic
can affect the results tremendously. More capacitors
have to be selected to compensate these parasitic pa­rameters.

Compensator Design

Due to the double pole generated by LC filter of
the power stage, the power system has 180o phase
shift , and therefore, is unstable by itself. In order to
achieve accurate output voltage and fast transient re­sponse, compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
the Bode plot of the closed loop system has crossover
frequency between 1/10 and 1/5 of the switching fre­quency, phase margin greater than 50o and the gain
crossing 0dB with -20dB/decade. Power stage output
capacitors usually decide the compensator type. If
electrolytic capacitors are chosen as output capacitors,
type II compensator can be used to compensate the
system, because the zero caused by output capacitor
ESR is lower than crossover frequency. Otherwise type
III compensator should be chosen.

Voltage feedforward compensation is used in
NX2130 to compensate the output voltage variation
caused by input voltage changing. The feedforward
funtion is realized by using VIN pin voltage to program
the oscillator ramp voltage V
voltage, which provides nearly constant power stage
gain under wide voltage input range.

at about 4/10 of V

OSC

over frequency. In this case, it is necessary to com­pensate the system with type III compensator. The
following figures and equations show how to realize
the type III compensator by transconductance ampli­fier.

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator

amplifier is given by:

V

e

=×

VsR(CC)

OUT 221

Zin

1

×+

Vout

R3

1

×π××

2RC

2(RR)C

2RC

2R

42

1

×π×+×

×π××

×π××

233

1

33

1

×

CC

12

4

+

CC

12

+××++×

CC

(1sR)1sRC

+××+×

21

433

CC

21

Zf

C1

C2

R4

×
+

( )

R2

C3

Fb

Ve

IN

R1

Vref

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross-

Rev. 1.4
03/24/07

Figure 13 - Type III compensator

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13

NEXSEM

20.33uH660uF

212m660uF

R=8.64k

==Ω

=(-)

210k10.8kHz40.2kHz

=3.33nF

=660uF

20.7510.8kHz6.65k

×π×××Ω

26.65k150kHz

NX2130

Case 1: FLC<FO<F

(for most ceramic or low

ESR

ESR POSCAP, OSCON)

power stage

LC

F

Gain(db)

40dB/decade

loop gain

ESR

F

20dB/decade

compensator

F

Z1 Z2

F

F

O

F

F

P1

P2

Figure 14 - Bode plot of Type III compensator

(FLC<FO<F

ESR

)

Typical design example of type III compensator
in which the crossover frequency is selected as
FLC<FO<F

and FO<=1/10~1/5Fs is shown as the

ESR

following steps.

1. Calculate the location of LC double pole F

and ESR zero F

F

=

LC

2LC

=

.

ESR

1

×π××

OUTOUT

1

LC

×π××

10.8kHz

=

2. Set R2 equal to 3.24kΩ.

×

2REF

1

V-V1.1V-0.8V

OUT REF

3.24k0.8V

Ω×

RV

Choose R1=8.66kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

C=(-)

3

111

2RFF

×π×

×π×Ω

×

2z2p1

111

×

, calculate C

ESR

Choose C3=3.3nF.

4. Calculate R4 with the crossover frequency at

1/10~ 1/5 of the switching frequency. Set FO=40kHz.

V2FL

OSCO

R=C

4out

VC

4240kHz0.33uH

103.3nF

=6.63k

×π××

××

in3

×π××

××

Ω

Choose R4=6.65kΩ.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

1

2FR

×π××

Z14

1

C

=

2

=

2.9nF

=

Choose C2=2.7nF.

6. Calculate C1 by equation (14) with pole Fp2 at

half the switching frequency.

C

=

1

=

160pF

=

1

2RF

×π××

4P2

1

×π×Ω×

3.

F

=

ESR

2ESRC

×π××

=

×π×Ω×

40.2kHz

=

Rev. 1.4
03/24/07

1

OUT

1

Choose C1=150pF.

7. Calculate R3 by equation (13) with Fp1 =F

www.nexsem.com

ESR

14

.

NEXSEM

240.2kHz3.3nF

22.2uH2000uF

215m2000uF

==Ω

R=12k

=(-)

215k1.8kHz5.3kHz

=2.4nF

25.3kHz2.7F

230kHz2.2uH15k11k

15m15k11k

×π××Ω×Ω

ΩΩ+Ω

×π×××Ω

20.751.8kHz16k

NX2130

1

2FC

×π××

P13

1

×π××

R

=

3

=

1.2k

=Ω

Choose R3 =1.2kΩ.

Case 2: FLC<F

(for electrolytic capacitors)

ESR<FO

power stage

LC

F

ESR

F

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

F

Z1 Z2

F

F

F

P1

F

O

P2

Figure 15 - Bode plot of Type III compensator

(FLC<F

ESR<FO

)

If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F

and FO<=1/10~1/5Fs is shown

ESR<FO

as the following steps. Here two SANYO MV-WG1000
with 30 mΩ is chosen as output capacitor, output
inductor is 2.2uH.

1. Calculate the location of LC double pole F

and ESR zero F

=

F

LC

2LC

=

.

ESR

1

×π××

OUTOUT

1

LC

×π××

=

1.8kHz

=

F

ESR

2ESRC

=
=

5.3kHz

1

×π××

OUT

1

×π×Ω×

2. Set R2 equal to 15kΩ.

RV

2REF

1

V-V1.8V-0.8V

OUT REF

Ω×

15k0.8V

×

Choose R1=12kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

ESR

.

4. Calculate C3 .

111

C=(-)

3

×π×

2RFF

×π×Ω

×

2z2p1

111

×

Choose C3=2.7nF.

5. Calculate R3 .

1

×π××

2FC

P13

1

×π××

=

R

3

=
=Ω

11.1k

Choose R3 =11kΩ.

6. Calculate R4 with FO=30kHz.

R=

=0.1
=16k

V2FLRR

OSCO23

4

VESRRR

in23

×π×××

××

+

××

Ω

Choose R4=16kΩ.

7. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

1

×π××

Z14

1

=

C

2

2FR

=

=

4.2nF

Choose C2=4.7nF.

8. Calculate C1 by equation (14) with pole Fp2 at

half the switching frequency.

Rev. 1.4
03/24/07

www.nexsem.com

15

NEXSEM

Gain= ... (15)

F= ... (16)

F ... (17)

216k150kHz

NX2130

=

C

1

2RF

=
=

66pF

1

×π××

4P2

1

×π×Ω×

Choose C1=68pF.

B. Type II compensator design

If the electrolytic capacitors are chosen as
power stage output capacitors, usually the Type II
compensator can be used to compensate the sys­tem.

For this type of compensator, FO has to satisfy
FLC<F

Case 1:

RC circuit as shown in figure 17. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise. The following
equations show the compensator pole zero location and
constant gain.

<<FO<=1/10~1/5F

ESR

s.

Type II compensator can be realized by simple

R

3

R

2

1

z

2RC

×π××

31

≈

p

1

2RC

×π××

32

power stage

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

F

F

F

LC

Z

ESR

P

F

F

O

Figure 16 - Bode plot of Type II compensator

C2

Vout

R3

R2

Fb

R1

Vref

C1

Ve

Figure 17 - Type II compensator

Rev. 1.4
03/24/07

The following parameters are used as an example
for type II compensator design, three 1500uF with
19mohm Sanyo electrolytic CAP 6MV1500WGL are
used as output capacitors. Coilcraft DO5010P-152HC

1.5uH is used as output inductor. The power stage in­formation is that:VIN=12V, V
FS=300kHz.

1.Calculate the location of LC double pole F

and ESR zero F

www.nexsem.com

ESR

=1.2V, I

OUT

=12A,

OUT

LC

.

16

NEXSEM

21.5uH4500uF

26.33m4500uF

=10k

=40.6k

××Ω

237.4k0.751.94kHz

p

F

37.4k300kHz

OUT

REF

2REF

OUT REF

IID1-D

NX2130

=

F

LC

×π××

2LC

=

1

OUTOUT

1

×π××

=

1.94kHz

=

F

ESR

2ESRC

=
=

5.6kHz

1

×π××

OUT

1

×π×Ω×

2.Set crossover frequency FO=30kHz>>F

ESR

Output Voltage Calculation

external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation applies to figure 18, which shows
the relationship between
vider.

.

3. Set R2 equal to10kΩ. Based on output
voltage, using equation 21, the final selection of R1 is
20kΩ.

4.Calculate R3 value by the following equation.

V2FL

R=R

OSCO

32

VESR

in

1230kHz1.5uH

106.33m

Choose R3 =40.2kΩ.

5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.

C=

1

2RF

×π××

=

×π×Ω××

=2.7nF

Choose C1=2.7nF.

6. Calculate C2 by setting compensator pole
at half the swithing frequency.

C=

2

π××

=

π×Ω×

=27pF

Choose C2=27pF.

×π××

××

×π××

Ω

Ω

1

3z

1

1

RF

3s

1

Figure 18 - Voltage divider

of R1 value can be set by voltage divider.

Z

Input Capacitor Selection

quency ceramic capacitors and bulk capacitors. Ce­ramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS cur­rent rating. The RMS current in the input capacitors
can be calculated

as:

VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of
input RMS current is 3.4A.

recommended. One Sanyo OSCON CAP 25SVP56M

Output voltage is set by reference voltage and

V ,

V and voltage di-

Vout

R2

Fb

R1

Vref

RV

R=

1

where R

Input capacitors are usually a mix of high fre-

RMSOUT

D

=

For higher efficiency, low ESR capacitors are

×

V-V

is part of the compensator, and the value

2

...(18)

=××

V

OUT

V

INMIN

...(19)

Rev. 1.4
03/24/07

www.nexsem.com

17

NEXSEM

×−××

P=I(1D)RK

SWINOUTSWS

PVITF

=××××

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

SWOCPLDSON

I3V/R8k/R

8k

95kohm

=×Ω

=×Ω

NX2130

25V 56uF 28mΩ with 3.8A RMS rating are chosen
as input bulk capacitors.

Power MOSFETs Selection

The NX2130 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter

efficiency. For example, two IRF7822 are used. They
have the following parameters: VDS=30V, ID =18A,R

=5mΩ,Q

power loss:conduction loss, switching loss.

P=IDRK

P=PP

where the RDS(ON) will increases as MOSFET junc­tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to

1.4 at 125oC according to datasheet. Conduction loss
should not exceed package rating or overall system
thermal budget.

conduction at the switching transition. The total
switching loss can be approximated.

where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.

ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis­charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:

=44nC.

GATE

There are two factors causing the MOSFET

Conduction loss is simply defined as:

2

HCONOUTDS(ON)

LCONOUTDS(ON)

TOTALHCONLCON

Switching loss is mainly caused by crossover

Also MOSFET gate driver loss should be consid-

×××

2

+

1
2

...(22)

...(23)

DSON

where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS
is the high side gate source voltage, and V
low side gate source voltage.

This power dissipation should not exceed maxi­mum power dissipation of the driver device.

...(24)

Over Current Limit Protection

Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. Inside NX2130, current limit I
the resistance Rocset from pin Vref_OC to ground and
Vref_OC voltage. The current generated by 3V/Rocset
is mirrored to a current source, which injects to SW
node through a internal 8kohm resistor. This current
I

will determine the current limit threshold.

OCP

This current is very accurate and does not change
with silicon process and temperature, the over current
limit tripping point can be set more accurate than tradi­tional current source. When synchronous FET is on,
the voltage at node SW is given as

OCP

V=I8k- IR×Ω ×

When the voltage is below zero, the over current
occurs. The over current limit can be set by the follow­ing equation

=×Ω

SETocsetDSON

For example, For 20A current limit and 9mohm
Rdson for IRFR3706, the OCP set resistor is calcu­lated as

R

Rocset8k

3V

IR1.4

××

SETDSON

3V

20A9mohm1.4

××

=

Select Vref_OC pin to ground resistance
Rocset=102kohm.

Vp voltage setup

The input of Vp voltage should be set at Vout/2
and can be derived by resistor divider from Vref_OC
to ground. For example when Vout is 5V, the bottom
resistor of divider is

is the

LGS

is set by

Rev. 1.4
03/24/07

www.nexsem.com

18

NEXSEM

OC_BOTOCSET

102kohm

85kohm

OC_TOPOC_BOT

17.3kohm

NX2130

RR

=×
=

Choose R

RR

=×
=

Choose R

Vout/2

=×

V

REF_OC

5V/2

3V

=86.6kohm.

OC_BOT

VVout/2

=×

3V5V/2

OC_TOP

REF_OC

Vout/2

−

5V/2

=17.4kohm.

−

86.6kohm

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

There are two sets of components considered in
the layout which are power components and small sig­nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en­vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay­out which includes power plane, ground plane and sig­nal plane is recommended .

Layout guidelines:

1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.

2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-

cally touching the drain pin of the upper MOSFET, a

plane connection is a must.

3. The output capacitors should be placed as close
as to the load as possible and plane connection is re-

quired.

4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane ans as close as possible. A snubber nedds to be
placed as close to this junction as possible.

5. Source of the lower MOSFET needs to be con­nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.

6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by­passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.

8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.

9. All GNDs need to go directly thru via to GND
plane.

10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.

11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana­log control function.

Rev. 1.4
03/24/07

www.nexsem.com

19

NEXSEM

4x4 16 PIN MLPQ OUTLINE DIMENSIONS

NX2130

Rev. 1.4
03/24/07

NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.

www.nexsem.com

20