Page 1
Evaluation board available.
NX2124/2124A
300kHz SYNCHRONOUS PWM CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2124/2124A controller IC is a synchronous Buck
controller IC designed for step down DC to DC converter applications. It is optimized to convert bus voltages from 2V to 25V to outputs as low as 0.8V voltage.
The NX2124/2124A operates at fixed 300kHz, employs
fixed loss-less current limiting by sensing the Rdson of
synchronous MOSFET followed by hiccup feature.
NX2124A has higher current limit threshold than NX2124.
Feedback under voltage also triggers hiccup.
Other features of the device are: 5V gate drive, Adaptive
deadband control, Internal digital soft start, Vcc
undervoltage lock out and shutdown capability via the
comp pin.
Vin
HI=SD
+5V
M3
C7
27pF
C3
1uF
37.4k
C2
2.2nF
C4
100uF
R4
7
6
5
Vcc
COMP
FB
R5
10
NX2124
Gnd
1
BST
3
D1
MBR0530T1
Hdrv
SW
Ldrv
FEATURES
n Bus voltage operation from 2V to 25V
n Fixed 300kHz voltage mode controller
n Internal Digital Soft Start Function
n Prebias Startup
n Less than 50 nS adaptive deadband
n Current limit triggers hiccup by sensing Rdson of
Synchronous MOSFET
n No negative spike at Vout during startup and
shutdown
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic Card on board converters
n Memory Vddq Supply in mother board applications
n On board DC to DC such as
5V to 3.3V, 2.5V or 1.8V
n Hard Disk Drive
n Set Top Box
TYPICAL APPLICATION
L2 1uH
C5
1uF
C6
0.1uF
2
8
4
M1
L1 1.5uH
M2
C1
4.7nF
R1
4k
10k
R2
Cin
280uF
18mohm
Vout
Co
2 x (1500uF,13mohm)
+1.8V 9A
R3
8k
Figure1 - Typical application of 2124
ORDERING INFORMATION
Device Temperature Package Frequency OCP Threshold Pb-Free
NX2124CSTR 0 to 70oC SOIC-8L 300kHz 360mV Yes
NX2124ACSTR 0 to 70oC SOIC-8L 300kHz 540mV Yes
Rev.1.8
02/28/08
1
Page 2
NX2124/2124A
130CW
θ≈/
ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to GND & BST to SW voltage ................... 6.5V
BST to GND Voltage ...................................... 40V
SW to GND Voltage .......................................-3V to 35V
Storage Temperature Range ............................. -65oC to 150oC
Operating Junction Temperature Range ............. -40oC to 125oC
NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
8-PIN PLASTIC SOIC (S)
o
8
SW
7
Comp
6
Fb
5
Vcc
BST
HDrv
Gnd
LDrv
JA
1
2
3
4
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to T
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
Ref Voltage line regulation 0.4 %
Supply Voltage(Vcc)
VCC Voltage Range V
VCC Supply Current (Static) ICC (Static) Outputs not switching 3 mA
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Supply Current (Static) I
BST
V
Supply Current
BST
(Dynamic)
BST
)
REF
CC
I
CC
(Dynamic)
(Static) Outputs not switching 0.15 mA
BST
I
BST
(Dynamic)
4.5V<Vcc<5.5V
C
=3300pF FS=300kHz 5 mA
LOAD
C
=3300pF FS=300kHz 5 mA
LOAD
4.5
0.8
5
5.5
V
V
A
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.22 V
Rev.1.8
02/28/08
4.2
V
2
Page 3
NX2124/2124A
3.4
OCP
PARAMETER SYM Test Condition Min TYP MAX Units
SS
Soft Start time Tss Fsw=300Khz
Oscillator (Rt)
Frequency F
Ramp-Amplitude Voltage V
S
RAMP
Max Duty Cycle
Min Duty Cycle
NX2124, NX2124A 300 kHz
1.6 V
84 %
0
Error Amplifiers
Transconductance 2000 umho
Input Bias Current Ib 10 nA
Comp SD Threshold 0.3 V
FBUVLO
Feedback UVLO threshold percent of nominal
65
70
75
High Side Driver(CL=2200pF)
Output Impedance , Sourcing R
Output Impedance , Sinking R
Sourcing Current I
Sinking Current I
(Hdrv) I=200mA 1.9 ohm
source
(Hdrv) I=200mA 1.7 ohm
sink
(Hdrv) 1 A
source
(Hdrv) 1.2 A
sink
Rise Time THdrv(Rise) 14 ns
Fall Time THdrv(Fall) 17 ns
Deadband Time Tdead(L to H)Ldrv going Low to Hdrv
30 ns
going High, 10%-10%
Low Side Driver (CL=2200pF)
mS
%
%
Output Impedance, Sourcing
R
(Ldrv) I=200mA 1.9 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 1 ohm
sink
Current
Sourcing Current I
Sinking Current I
(Ldrv) 1 A
source
(Ldrv) 2 A
sink
Rise Time TLdrv(Rise) 13 ns
Fall Time TLdrv(Fall) 12 ns
10 nsDeadband Time Tdead(H to L)SW going Low to Ldrv
going High, 10% to 10%
NX2124 360
mVOCP voltage
NX2124A 540
Rev.1.8
02/28/08
3
Page 4
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 BST
This pin supplies voltage to the high side driver. A high frequency
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.
NX2124/2124A
2 HDRV
3 GND
4 LDRV
5 Vcc
6 FB
7 COMP
8 SW
High side MOSFET gate driver.
Ground pin.
Low side MOSFET gate driver. For the high current application, a 4.7nF capaci-
tor is recommended to be placed on low side MOSFET's gate to ground. This is
to prevent undesired Cdv/dt induced low side MOSFET's turn on to happen,
which is caused by fast voltage change on the drain of low side MOSFET in
synchronous buck converter and lower the system efficiency.
Voltage supply for the internal circuit as well as the low side MOSFET gate
driver. A 1uF high frequency ceramic capacitor must be connected from this pin
to GND pin.
This pin is the error amplifier inverting input. This pin is also connected to the
output UVLO comparator. When this pin falls below 0.56V, both HDRV and
LDRV outputs are in hiccup.
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut
down pin. When this pin is pulled below 0.3V, both drivers are turned off and
internal soft start is reset.
This pin is connected to the source of the high side MOSFET and provides
return path for the high side driver. Also SW senses the low side MOSFETS
current, when the pin voltage is lower than 360mV for NX2124, 540mV for NX2124A,
hiccup will be triggered.
Rev.1.8
02/28/08
4
Page 5
BLOCK DIAGRAM
NX2124/2124A
VCC
FB
COMP
GND
Bias
Generator
COMP
0.3V
START
Digital
start Up
0.8V
1.25V
ramp
START
0.8V
OSC
UVLO
0.6V
CLAMP
70%Vp
S
R
1.3V
CLAMP
FB
POR
Q
OC
START
PWM
Hiccup Logic
Hiccup Logic
OC
BST
HDRV
SW
Control
Logic
VCC
LDRV
360mV/540mV
OCP
comparator
Rev.1.8
02/28/08
Figure 2 - Simplified block diagram of the NX2124/NX2124A
5
Page 6
NX2124/2124A
RIPPLEINS
1
IVF
0.39A5V300kHz
=2.56A
SOUT
==Ω
ESR=7.8m
ERIPPLE
13m2.56A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2124, the
schematic is figure 1.
VIN = 5V
VOUT=1.8V
FS=300kHz
IOUT=9A
DVRIPPLE <=20mV
DVDROOP<=100mV @ 9A step
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
OUT
∆
INOUT OUT
××
×
5V-1.8V1.8V1
OUT
OUT
××
×
...(1)
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
L=1.4uH
Choose inductor from COILCRAFT DO5010P152HC with L=1.5uH is a good choice.
Current Ripple is recalculated as
V-VV
∆××
I=
RIPPLE
INOUT OUT
LVF
OUTINS
5V-1.8V1.8v1
1.5uH5v300kHz
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example,electrolytic capacitors are chosen as output capacitors, the ESR and inductor current
typically determines the output voltage ripple.
∆
tiple capacitors in parallel are better than a big capacitor. For example, SANYO electrolytic capacitor
16ME1500WG is chosen.
integer. Choose N =2.
desire
If low ESR is required, for most applications, mul-
ESRI
N
=
Number of Capacitor is calculated as
N
N =1.7
The number of capacitor has to be round up to a
If ceramic capacitors are chosen as output ca
Ω×
=
20mV
is the value of output capacitors.
OUT
V
RIPPLE
∆
I2.56A
RIPPLE
20mV
×∆
V
∆
RIPPLE
RIPPLE
××
8FC
...(5)
...(3)
...(4)
Rev.1.8
02/28/08
6
Page 7
NX2124/2124A
8300kHz100uF
DROOPTRAN
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
3.9H
=µ
2
1.2×∆=+×τ
pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors .
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.56A
RIPPLE
15mV
=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
V<V∆∆ @ step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI
transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the following equation.
VESRI
overshootstep
where τ is the a function of capacitor, etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
2.56A
××
STEP
V
OUT
2LC
××
OUT
...(6)
...(7)
STEP
...(8)
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤ is true. In that case, the
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 9A load step.
If the SANYO electrolytic capaictor 16ME1500WG
(1500uF, 13mΩ ) is used, the critical inductance is given
as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
13m1500F1.8V
9A
The selected inductor is 1.5uH which is smaller
than critical inductance. In that case, the output voltage
transient only dependent on the ESR.
number of capacitors is
ESRI
N
13m9A
=+
Estep
V2LCV
∆×××∆
tranEtran
Ω×
100mV
1.8V
21.5H220F100mV
×µ×µ×
V
OUT
2
(0)
×
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
Rev.1.8
02/28/08
7
Page 8
NX2124/2124A
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin.Ideally,the
Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency,
phase margin greater than 50o and the gain crossing
0dB with -20dB/decade. Power stage output capacitors
usually decide the compensator type. If electrolytic
capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensator should be chosen.
1
2RC
×π××
42
1
2(RR)C
×π×+×
233
1
2RC
×π××
33
1
CC
×
2R
×π××
4
CC
12
+
12
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 4.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.
Zin
Vout
Zf
C1
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev.1.8
02/28/08
R3
C2
R4
R2
C3
Fb
gm
Ve
R1
Vref
Figure 3 - Type III compensator using
transconductance amplifier
8
Page 9
Case 1: FLC<FO<F
21.5uH440uF
26m440uF
==Ω
R=8k
=(-)
210k6.2kHz60.3kHz
=2.3nF
=440uF
20.756.2kHz16.9k
×π×××Ω
216.9k150kHz
260.3kHz2.2nF
ESR
NX2124/2124A
×
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
10k0.8V
power stage
LC
F
Gain(db)
40dB/decade
loop gain
ESR
F
20dB/decade
compensator
F
Z1 Z2
F
F
O
F
P1
F
P2
Figure 4 - Bode plot of Type III compensator
Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<F
and FO<=1/10~1/5Fs. Here two POSCAP
ESR
2R5TPE220MC(220uF,12 mΩ) are chosen as output
capacitor.
1.Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
6.2kHz
=
Choose R
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate R
=8kΩ.
1
ESR
and C3 with the crossover
4
.
frequency at 1/10~ 1/5 of the switching frequency. Set
FO=30kHz.
C=(-)
R=C
=16.9k
111
3
2RFF
×π×
×π×Ω
V2FL
OSCO
4out
VC
1.5V230kHz1.5uH
5V2.2nF
×
2z2p1
111
××
in3
×
×π××
×π××
××
Ω
Choose C3=2.2nF, R4=16.9kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
2nF
=
Choose C2=2.2nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
63pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=68pF.
7. Calculate R3 by equation (13).
F
=
ESR
2ESRC
×π××
=
×π×Ω×
60.3kHz
=
1
OUT
1
2. Set R2 equal to 10kΩ.
Rev.1.8
02/28/08
R
=
3
2FC
=
1.2k
=Ω
Choose R3=1.2kΩ.
1
×π××
P13
1
×π××
9
Page 10
NX2124/2124A
21.5uH3000uF
26.5m3000uF
==Ω
R=8k
=(-)
210k2.3kHz8.2kHz
=4.76nF
28.2kHz4.7nF
1.5V230kHz1.5uH10k4k
5V6.5m10k4k
×π××Ω×Ω
ΩΩ+Ω
20.752.3kHz37.4k
×π×××Ω
237.4k150kHz
Case 2: FLC<F
power stage
Gain(db)
loop gain
compensator
F
Z1 Z2
ESR<FO
LC
F
ESR
F
F
40dB/decade
F
F
P1
O
20dB/decade
F
P2
2. Set R2 equal to 10kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
10k0.8V
×
Choose R1=8.06kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate C3 .
C=(-)
111
3
2RFF
×π×
×π×Ω
×
2z2p1
111
×
Choose C3=4.7nF.
5. Calculate R3 .
1
2FC
×π××
P13
1
×π××
R
=
3
=
4.1k
=Ω
Choose R3 =4kΩ.
6. Calculate R4 with FO=30kHz.
Ω×
ESR
.
Figure 5 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here two SANYO 16MV-WG1500
with 13 mΩ is chosen as output capacitor.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
2.3kHz
=
F
=
ESR
2ESRC
=
8.2kHz
=
1
×π××
OUT
1
×π×Ω×
R=
=
=37.3k
V2FLRR
4
VESRRR
×π×××
OSCO23
××
in23
+
××
Ω
Choose R4=37.4kΩ.
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
2.4nF
=
Choose C2=2.2nF.
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
28pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=27pF.
Rev.1.8
02/28/08
10
Page 11
B. Type II compensator design
Gain=gR ... (15)
F= ... (16)
F ... (17)
21.5uH3000uF
26.5m3000uF
==Ω
R=800
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 6. R3 and C
introduce a zero to cancel the double pole effect. C
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero location and constant gain.
R
1
××
m3
R+R
12
1
2RC
×π××
31
1
2RC
×π××
32
power stage
loop gain
40dB/decade
20dB/decade
z
≈
p
Gain(db)
NX2124/2124A
Vout
R2
Fb
1
2
R1
Vref
Figure 7 - Type II compensator with
transconductance amplifier
For this type of compensator, FO has to satisfy
FLC<F
tor design. Input voltage is 5V, output voltage is 1.8V,
output inductor is 1.5uH, output capacitors are two
1500uF with 13mΩ electrolytic capacitors.
and ESR zero F
<<FO<=1/10~1/5F
ESR
s.
The following is parameters for type II compensa-
1.Calculate the location of LC double pole F
.
ESR
F
=
LC
2LC
×π××
=
1
OUTOUT
1
×π××
2.3kHz
=
gm
Ve
R3
C2
C1
LC
compensator
F
Figure 6 - Bode plot of Type II compensator
Rev.1.8
02/28/08
F
=
ESR
2ESRC
Gain
F
F
LC
Z
ESR
P
F
F
O
8.2kHz
×π××
=
×π×Ω×
=
1
OUT
1
2.Set R2 equal to 1kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
1k0.8V
×
Choose R1=800Ω.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.
11
Page 12
4.Calculate R3 value by the following equation.
5V6.5m2.0mA/V
214.7k0.752.3kHz
p
F
p14.7k300kHz
OUT
REF
2REF
OUT REF
IID1-D
V2FLV
R=
3
VRgV
1.5V230kHz1.5uH1
=
=14.6k
×π××
OSCOOUT
×××
inESRmREF
×π××
××
1.8V
×
0.8V
1
Ω
Ω
Choose R3 =14.7kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=6.3nF
Choose C1=6.8nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
RF
π××
3s
×Ω×
1
=72pF
Choose C1=68pF.
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation and picture show the relationship
between
value of R1 value can be set by voltage divider.
V ,
V and voltage divider..
RV
R=
1
×
V-V
...(18)
where R2 is part of the compensator, and the
See compensator design for R1 and R2 selection.
NX2124/2124A
Vout
R2
Fb
R1
Vref
Voltage divider
Figure 8 - Voltage divider
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
=××
RMSOUT
V
OUT
D
=
V
IN
VIN = 5V, VOUT=1.8V, IOUT=9A, using equation (19),
the result of input RMS current is 4.3A.
For higher efficiency, low ESR capacitors are recommended. One Sanyo OS-CON 16SP270M 16V 270uF
18mΩ with 4.4A RMS rating are chosen as input bulk
capacitors.
Power MOSFETs Selection
The power stage requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, I
=75A,R
loss:conduction loss, switching loss.
DSON
=9mΩ,Q
GATE
=23nC.
There are two factors causing the MOSFET power
Conduction loss is simply defined as:
...(19)
D
Rev.1.8
02/28/08
12
Page 13
NX2124/2124A
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
I
KR
I26.7A
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
2
×××
2
K
+
...(20)
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3706 datasheet. Conduc-
tion loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
loss can be approximated.
1
2
...(21)
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Switching loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
is the low
LGS
side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2124, the current limit is decided by
the R
FET is on, and the voltage on SW pin is below 360mV,
the over current occurs. The over current limit can be
calculated by the following equation.
of the low side mosfet. When synchronous
DSON
360mV
=
SET
If MOSFET R
×
DSON
=9mΩ, the worst case thermal
DSON
consideration K=1.5, then
320mV360mV
===
SET
KR1.59m
××Ω
DSON
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
R
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be con-
Rev.1.8
02/28/08
13
Page 14
NX2124/2124A
nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
TYPICAL APPLICATION
Vin
+12V
C3
33uF
L2 1uH
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND plane.
10. The feedback part of the system should be kept
away from the inductor and other noise sources, and be
placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate loop
that does not interfere with the more sensitive analog control function.
C5
1uF
Cin
2 x 16SP180M
Vin
+5V
HI=SD
D1 MBR0530T1
C6
5
1uF
Vcc
7
M3
C1
220pF
R2
800
C2
15nF
R4
5k
6
Comp
Fb
1
BST
NX2124
Gnd
3
1kR1
Hdrv
SW
Ldrv
2
8
4
C7 4.7nF
C4
0.1uF
M1 IRF3706
L1 1uH
M2
2 x IRF3706
Figure 9 - High output current application of 2124
Vout
Co
2 x (1500uF,13mohm)
+1.8V,20A
Rev.1.8
02/28/08
14
Page 15
SOIC8 PACKAGE OUTLINE DIMENSIONS
NX2124/2124A
Rev.1.8
02/28/08
15
Page 16
NX2124/2124A
Rev.1.8
02/28/08
16
Page 17
Customer Service
NEXSEM Inc.
NX2124/2124A
500 Wald
Irvine, CA 92618
U.S.A.
Tel: (949)453-0714
Fax: (949)453-0713
WWW.NEXSEM.COM
Rev.1.8
02/28/08
17
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