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NEXSEM
SYNCHRONOUS PWM CONTROLLER WITH
NX2120
CURRENT LIMIT, POWER GOOD
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The 2120 family of products is synchronous Buck controller IC designed for step down DC to DC converter
applications. They are optimized to convert bus voltages from 2V to 25V to as low as 0.8V output voltage.
These products operate at fixed internal frequency of
300kHz, except that NX2120 operates at 300kHz and
2120A at 600kHz frequency. These products employ lossless current limiting protection by sensing the Rdson of
synchronous MOSFET followed by latch out feature.
Feedback under voltage triggers Hiccup.
Other features are; 5V gate drive, Power good indicator, Adaptive deadband control, Internal digital soft start;
Vcc undervoltage lock out and shutdown capability via
the comp pin.
L2 1uH
5
1
Vcc BST
Hdrv
OCP
NX2120A
Pgood
ON
OFF
Vin1
+12V
Vin2
+5V
R8
R7
10k
10k
C3
39uF
2N3904
C1
33pF
C4
1uF
17.4k
R3
10
C2
1.5nF
R4
8
Comp SW
7
Fb
3
Gnd
FEATURES
n Bus voltage operation from 2V to 25V
n Power Good indicator available
n Fixed 300kHz, 600kHz
n Internal Digital Soft Start Function
n Less than 50 nS adaptive deadband
n Current limit triggers latch out by sensing Rdson of
Synchronous MOSFET
n No negative spike at Vout during startup and
shutdown
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic Card on board converters
n Memory Vddq Supply
n On board DC to DC such as 2V to 3.3V, 2.5V or
1.8V
n ADSL Modem
TYPICAL APPLICATION
D1
MBR0530T1
Ldrv
C5
1uF
C7
0.1uF
2
10
9
3.7kR11
4
6
1k
R10
M1
L1 1uH
M2
+5V
Cin
270uF,18mohm
Co
2x (220uF,12mohm)
Vout
+1.8V,9A
R9
20kR1
C8
1nF2.61k
R2
16k
Figure 1 - Typical application of 2120A
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2120CUTR 0 to 70oC MSOP-10L 300kHz Yes
NX2120ACUTR 0 to 70oC MSOP-10L 600kHz Yes
Rev. 3.0
24/03/06
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NEXSEM
CW
θ≈200/
REF
CC
NX2120
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V
BST to GND Voltage ........................................ -0.3V to 35V
SW to GND ...................................................... -2V to 35V
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
NX2120/2120A
10-LEAD PLASTIC MSOP
o
10
SW
OCP
9
8
COMP
7
FB
PGOOD
6
BST
HDrv
GND
LDrv
VCC
JA
1
2
3
4
5
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to T
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
Ref Voltage line regulation 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
VCC Supply Current (Static) ICC (Static) Outputs not switching 3 mA
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Supply Current (Static) I
BST
V
Supply Current
BST
(Dynamic)
BST
)
I
CC
(Dynamic)
(Static) Outputs not switching TBD mA
BST
I
BST
(Dynamic)
C
=3300pF
LOAD
FS=300kHz
C
=3300pF
LOAD
FS=300kHz
4.5
0.8
5
TBD mA
TBD mA
5.5
V
V
A
Rev. 3.0
24/03/06
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NEXSEM
S
RAMP
(CL=3300pF)
BST-VSW
OCP current
40
uA
Ldrv going Low to Hdrv going
NX2120
PARAMETER SYM Test Condition Min TYP MAX Units
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V
Oscillator
Frequency F
2120A 600 kHz
Ramp-Amplitude Voltage V
Max Duty Cycle
Min Duty Cycle
Error Amplifiers
Transconductance 2000 umho
Input Bias Current Ib 10 nA
EN & SS
Soft Start time Tss mS
Enable HI Threshold 1.25 V
Enable Hysterises 150 mV
Comp Shutdown Threshold 0.3 V
High Side Driver
2120 300 kHz
NX2120 6.8
NX2120A
3.8
4
1.5 V
95 %
4.2
0
V
%
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time THdrv(Rise) V
Fall Time THdrv(Fall) V
Deadband Time
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv going
OCP Adjust
Power Good(Pgood)
Threshold Voltage as % of
Vref
Hysteresis 5 %
R
(Hdrv) I=200mA
source
R
(Hdrv) I=200mA
sink
BST-VSW
Tdead(L to
H)
R
(Ldrv) I=200mA 0.9 ohm
source
R
(Ldrv) I=200mA 0.5 ohm
sink
High, 10%-10%
High, 10% to 10%
FB ramping up 90 %
=4.5V 50 ns
=4.5V 50 ns
0.9 ohm
ohm0.65
ns30
30
ns
Rev. 3.0
24/03/06
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NEXSEM
PIN DESCRIPTIONS
PIN SYMBOL PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to
VCC
BST
and connected to this pin and ground pin. The maximum rating of this pin is 5V.
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is
placed as close as possible to and connected to these pins and respected SW pins.
NX2120
GND
FB
OCP
SW
HDRV
LDRV
PGOOD
COMP
Ground pin.
This pin is the error amplifier inverting input. It is connected via resistor divider to the
output of the switching regulator to set the output DC voltage.
This pin is connected to the drain of the external low side MOSFET via resistor and is the
input of the over current protection(OCP) comparator. An internal current source 40uA is
flown to the external resistor which sets the OCP voltage across the Rdson of the low side
MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is
reached the Hdrv and Ldrv pins are switched low and an internal hiccup circuit is set that
recycles the soft start circuit after 2048 switching cycles.
This pin is connected to source of high side FET and provides return path for the high side
driver. It is also used to hold the low side driver low until this pin is brought low by the
action of high side turning off. LDRV can only go high if SW is below 1V threshold .
High side gate driver output.
Low side gate driver output.
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI
state.
This pin is the output of error amplifier and is used to compensate the voltage control
feedback loop. This pin can also be used to perform a shutdown if pulled lower than 0.3V.
Rev. 3.0
24/03/06
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NEXSEM
BLOCK DIAGRAM
NX2120
VCC
FB
COMP
GND
Bias
Generator
START
Digital
start Up
0.8V
COMP
0.3V
START
1.25V
0.8V
ramp
OSC
UVLO
0.6V
CLAMP
S
R
1.3V
CLAMP
POR
Q
OC
START
PWM
OC
Hiccup Logic
FB
0.9Vref
/0.85Vref
Control
Logic
OCP
comparator
PGOOD
BST
HDRV
SW
VCC
LDRV
40uA
OCP
Rev. 3.0
24/03/06
Figure 2 - Simplified block diagram of the NX2120
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NEXSEM
RIPPLEINS
1
IVF
0.39A12V600kHz
=2.55A
SOUT
==Ω
ESR=7.8m
ERIPPLE
12m2.56A
NX2120
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2120A,
the schematic is figure 1.
VIN = 12V
VOUT=1.8V
FS=600kHz
IOUT=9A
DVRIPPLE <=20mV
DVDROOP<=100mV @ 9A step
Output Inductor Selection
The selection of inductor value is based on induc-
tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu-
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli-
cation requirements. The inductor value can be calcu-
lated by using the following equations:
V-VV
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
L=0.94uH
Choose inductor from COILCRAFT DO3316P-
102HC with L=1uH is a good choice.
Current Ripple is recalculated as
INOUT OUT
OUT
∆
12V-1.8V1.8V1
OUT
OUT
××
×
××
×
...(1)
V-VV 1
∆××
I=
RIPPLE
INOUT OUT
LVF
OUTINS
12V-1.8V1.8v1
1uH12V600kHz
××=
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically de-
termines the output voltage ripple.
∆
tiple capacitors in parallel are better than a big capaci-
tor. For example, for 20mV output ripple, POSCAP
2R5TPE220MC with 12mΩ are chosen.
integer. Choose N =2.
desire
If low ESR is required, for most applications, mul-
ESRI
N
=
Number of Capacitor is calculated as
Ω×
=
N
N =1.5
The number of capacitor has to be round up to a
If ceramic capacitors are chosen as output ca
20mV
is the value of output capacitors.
OUT
V 20mV
RIPPLE
∆
I2.55A
RIPPLE
×∆
V
∆
RIPPLE
RIPPLE
××
8FC
...(5)
...(3)
...(4)
Rev. 3.0
24/03/06
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NEXSEM
8600kHz100uF
DROOPTRAN
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.56H
=µ
12m220F2.36us
2
=+×τ
NX2120
pacitors, both terms in equation (3) need to be evalu-
ated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capaci-
tance per single unit is not sufficient to meet the tran-
sient specification, which results in parallel configura-
tion of multiple capacitors .
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.55A
RIPPLE
10.4mV
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
=
V<V∆∆ @ step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI
transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the fol-
lowing equation.
VESRI
tance of each capacitor if multiple capacitors are used
in parallel.
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
overshootstep
where τ is the a function of capacitor, etc.
0ifLL
LI
×∆τ=
V
where
ESRCVESRCV
L
==
crit
where ESRE and CE represents ESR and capaci-
The above equation shows that if the selected out-
≤
crit
step
−×≥
OUT
××××
II
∆∆
stepstep
2.56A
××
STEP
V
OUT
2LC
××
OUT
...(6)
...(7)
STEP
...(8)
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
ESRI
×∆
N
where
For example, assume voltage droop during tran-
sient is 100mV for 9A load step.
If the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is
used, the critical inductance is given as
Estep
V2LCV
∆×××∆
tranEtran
0ifLL
LI
×∆τ=
step
12m220F1.8V
−×≥
V
OUT
ESRCV
L
==
crit
Ω×µ×
≤ is true. In that case, the
V
OUT
≤
crit
××
EEOUT
I
∆
step
...(9)
...(10)
9A
The selected inductor is 1uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitors is
LI
×∆
step
τ=−×
V
OUT
1H9A
µ×
=−Ω×µ=
ESRC
EE
1.8V
ESRI
×∆
N
=+
21H220F100mV
×µ×µ×
1.3
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
Estep
V2LCV
∆×××∆
tranEtran
12m9A
Ω×
100mV
1.8V
V
OUT
(2.36us)
×
2
Rev. 3.0
24/03/06
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NEXSEM
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
NX2120
It should be considered that the proposed equa-
tion is based on ideal case, in reality, the droop or over-
shoot is typically more than the calculation. The equa-
tion gives a good start. For more margin, more capaci-
tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es-
pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin.Ideally,the
Bode plot of the closed loop system has crossover fre-
quency between1/10 and 1/5 of the switching frequency,
phase margin greater than 50o and the gain crossing
0dB with -20dB/decade. Power stage output capacitors
usually decide the compensator type. If electrolytic
capacitors are chosen as output capacitors, type II com-
pensator can be used to compensate the system, be-
cause the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensa-
tor should be chosen.
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 4.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
For the voltage amplifier, the transfer function of
compensator is
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desir-
able if R1||R2||R3>>1/gm can be met at the same time.
=
V
e
=
To achieve the same effect as voltage amplifier,
Zin
1
2RC
×π××
42
1
2(RR)C
×π×+×
2RC
×π××
2R
×π××
+×+
Vout
233
1
33
1
CC
12
4
CC
12
−×
×
+
Zf
C1
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross-
over frequency. In this case, it is necessary to compen-
sate the system with type III compensator. The follow-
ing figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev. 3.0
24/03/06
R3
C3
Figure 3 - Type III compensator using
transconductance amplifier
www.nexsem.com
R2
R1
C2
Fb
Vref
R4
gm
Ve
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NEXSEM
21uH440uF
26m440uF
==Ω
R=16k
=(-)
220k7.6kHz60.3kHz
=440uF
20.757.6kHz17.4k
×π×××Ω
217.4k300kHz
260.3kHz1nF
NX2120
Case 1: FLC<FO<F
power stage
LC
F
Gain(db)
loop gain
compensator
F
Z1
F
Z2
ESR
40dB/decade
ESR
F
20dB/decade
O
F
P1
F
Choose R
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate R
=16kΩ.
1
and C3 with the crossover
4
ESR
.
frequency at 1/10~ 1/5 of the switching frequency. Set
FO=50kHz.
C=(-)
111
3
2RFF
×π×
×π×Ω
×
2z2p1
111
×
=916pF
V2FL
OSCO
R=C
4out
VC
1.5V250kHz1uH
×π××
××
in3
×π××
××
12V1nF
=17.2k
Choose C3=1nF, R
Ω
=17.4kΩ.
4
5. Calculate C2 with zero Fz1 at 75% of the LC
F
P2
double pole by equation (11).
Figure 4 - Bode plot of Type III compensator
Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<F
1.Calculate the location of LC double pole F
and ESR zero F
and FO<=1/10~1/5F
ESR,
.
ESR
F
=
LC
2LC
×π××
=
s.
LC
1
OUTOUT
1
×π××
7.6kHz
=
F
ESR
=
2ESRC
×π××
=
1
OUT
1
×π×Ω×
60.3kHz
=
2. Set R
1
equal to 20kΩ.
2
× Ω×
RV 20k0.8V
2REF
V-V1.8V-0.8V
OUT REF
1
2FR
×π××
Z14
1
C
=
2
=
1.6nF
=
Choose C2=1.5nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
30pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=33pF
7. Calculate R3 by equation (13).
1
2FC
×π××
P13
1
R
=
3
=
×π××
2.64k
=Ω
Choose R
=2.61kΩ.
3
Rev. 3.0
24/03/06
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NEXSEM
21uH3000uF
26.5m3000uF
==Ω
R=8k
=(-)
210k2.9kHz8.2kHz
28.2kHz3.3nF
1.5V260kHz1uH10k5.9k
12V6.5m10k5.9k
×π××Ω×Ω
ΩΩ+Ω
20.752.9kHz26.7k
×π×××Ω
226.7k300kHz
NX2120
Case 2: FLC<F
power stage
Gain(db)
loop gain
compensator
F
Z1
ESR<FO
LC
F
ESR
F
F
Z2
40dB/decade
O
F
P1
F
20dB/decade
F
P2
2. Set R
1
Choose R
equal to 10kΩ.
2
× Ω×
RV 10k0.8V
2REF
V-V1.8V-0.8V
OUT REF
=8kΩ.
1
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate C3 .
C=(-)
111
3
2RFF
×π×
×
2z2p1
111
×
×π×Ω
=3.5nF
Choose C3=3.3nF.
5. Calculate R3 .
1
2FC
×π××
P13
1
R
=
3
=
×π××
5.9k
=Ω
Choose R
=5.9kΩ.
3
6. Calculate R4 with FO=60kHz.
ESR
.
Figure 5 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here two SANYO MV-WG1500
with 13 mΩ is chosen as output capacitor.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
2.9kHz
=
F
=
ESR
2ESRC
=
1
×π××
OUT
1
×π×Ω×
8.2kHz
=
R=
=
=26.9k
V2FLRR
4
VESRRR
Choose R
×π×××
OSCO23
××
in23
+
××
Ω
=26.7kΩ.
4
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
2nF
=
Choose C2=2.2nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
20pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=22pF.
Rev. 3.0
24/03/06
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NEXSEM
Gain=gR ... (15)
F= ... (16)
F ... (17)
21uH3000uF
26.5m3000uF
==Ω
R=800
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa-
tor can be used to compensate the system.
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 7. R3 and C
introduce a zero to cancel the double pole effect. C
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero lo-
cation and constant gain.
R
1
××
m3
R+R
12
1
2RC
×π××
31
1
2RC
×π××
32
power stage
40dB/decade
20dB/decade
z
≈
p
Gain(db)
loop gain
NX2120
Vout
R2
Fb
1
2
R1
Vref
Figure 7 - Type II compensator with
transconductance amplifier
For this type of compensator, FO has to satisfy
FLC<F
tor design. Input voltage is 12V, output voltage is 1.8V,
output inductor is 1uH, output capacitors are two 1500uF
with 13mΩ electrolytic capacitors.
and ESR zero F
<<FO<=1/10~1/5F
ESR
The following is parameters for type II compensa-
1.Calculate the location of LC double pole F
.
ESR
F
=
LC
2LC
×π××
=
s.
1
OUTOUT
1
×π××
2.9kHz
=
gm
Ve
R3
C2
C1
LC
compensator
F
Figure 6 - Bode plot of Type II compensator
Rev. 3.0
24/03/06
Z LCFESR
F
1
OUT
1
Gain
F
ESR
=
2ESRC
×π××
=
×π×Ω×
8.2kHz
F
P
O
F
2.Set R
Choose R
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=60kHz.
4.Calculate R3 value by the following equation.
www.nexsem.com
=
equal to 1kΩ.
2
× Ω×
RV 1k0.8V
2REF
1
V-V1.8V-0.8V
OUT REF
=806Ω.
1
11
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NEXSEM
12V6.5m2.0mA/V
28.2k0.752.9kHz
p
F
8.2k300kHz
OUT
REF
V
2REF
OUT REF
IID1-D
4.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1.5V260kHz1uH1
=
=8.15k
Choose R
5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.
C=
1
2RF
=
=8.9nF
Choose C1=8.2nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
=129pF
Choose C1=120pF.
Output Voltage Calculation
Output voltage is set by reference voltage and ex-
ternal voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation and picture show the relationship between
V ,
R=
1
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
×π××
×××
inESRmREF
×π××
××
1.8V
×
1
Ω
0.8V
Ω
=8.2kΩ.
3
1
×π××
3z
1
×π×Ω××
1
RF
π××
3s
1
π×Ω×
and voltage divider..
RV
×
V-V
...(18)
NX2120
Vout
R2
Fb
R1
Vref
Voltage divider
Figure 8 - Voltage divider
Input Capacitor Selection
Z
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca-
pacitors bypass the high frequency noise, and bulk ca-
pacitors supply switching current to the MOSFETs. Usu-
ally 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are de-
cided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
=××
RMSOUT
V
OUT
D
=
V
IN
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation (19),
the result of input RMS current is 3.2A.
For higher efficiency, low ESR capacitors are rec-
ommended. One Sanyo OS-CON 16SP180M 16V 180uF
20mΩ with 3.4A RMS rating is chosen as input bulk
capacitors.
Power MOSFETs Selection
The power stage requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3709Z are
used. They have the following parameters: VDS=30V,R
=6.5mΩ,Q
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
GATE
=17nC.
...(19)
DSON
Rev. 3.0
24/03/06
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12
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NEXSEM
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
SWLDSON
IR+V
OCPOCP
DSON
===Ω
R3.656k
NX2120
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
2
×××
2
K
+
...(20)
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3709Z datasheet. Conduc-
tion loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover con-
duction at the switching transition. The total switching
loss can be approximated.
1
2
...(21)
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Switching loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
is the low
LGS
side gate source voltage.
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Over Current Protection
Over current protection is achieved by sensing cur-
rent through the low side MOSFET. An internal current
source of 40uA flows through an external resistor con-
nected from OCP pin to SW node sets the over current
protection threshold. When synchronous FET is on, the
voltage at node SW is given as
V=-IR×
The voltage at pin OCP is given as
×
OCPOCPSW
When the voltage is below zero, the over current
occurs as shown in figure 10.
vbus
OCP
I
40uA
OCP
comparator
OCP
SW
OCP
R
Figure 10 - Over current protection
The over current limit can be set by the following
equation
SET
If MOSFET R
R
consideration K=1.5 and the current limit is set at 15A,
×
KR
=6.5mΩ, the worst case thermal
DSON
×
IR
=
I
then
Choose R
I40uA
OCP
=3.7kΩ
OCP
×× ××Ω
IKR 15A1.56.5m
SETDSON
OCP
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the
connection in the top layer with wide, copper filled ar-
eas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input ca-
pacitor directly to the drain of the high-side MOSFET, to
reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced.
The goal is to localize the high current path to a
Rev. 3.0
24/03/06
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13
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NEXSEM
separate loop that does not interfere with the more sen-
sitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.
NX2120
Rev. 3.0
24/03/06
www.nexsem.com
14
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