Page 1
NX2116/2116A/2116B/2117/2117A
SYNCHRONOUS PWM CONTROLLER WITH
CURRENT LIMIT, POWER GOOD & OVER VOLTAGE
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2116/2117 family of products are synchronous
Buck controller IC designed for step down DC to DC
converter applications. They are optimized to convert
bus voltages from 2V to 25V to as low as 0.8V output
voltage. The NX2116 and 2117 offer an Enable pin that
can be used to program the converter's start up voltage
using an external divider from bus voltage. These products operate at fixed internal frequency of 300kHz, except that NX2116A operates at 600kHz and 2116B at
1MHz frequency. These products employ loss-less current limiting protection by sensing the Rdson of synchronous MOSFET followed by latch out feature. Feedback under voltage triggers Hiccup.
Other features are; 5V gate drive, Power good indicator, Adaptive deadband control, Internal digital soft start;
Vcc undervoltage lock out and shutdown capability via
the enable pin or comp pin.
L2 1uH
4
Vcc
NX2116A
ON
OFF
R8
10k
R7
10k
Vin1
+12V
Vin2
+5V
2N3904
C3
39uF
R5
68k
R6
12.4k
C1
33pF
C4
1uF
17.4k
R3
10
C2
1.5nF
R4
6
8
7
11
EN
Comp
Fb
Gnd
FEATURES
n Bus voltage operation from 2V to 25V
n Power Good indicator available in NX2116
n Fixed 300kHz, 600kHz and 1MHz for NX2116 and
300kHz, 600kHz for NX2117 family.
n Internal Digital Soft Start Function
n Less than 50 nS adaptive deadband
n Enable pin to program BUS UVLO for NX2116/2117
n Programmable current limit triggers latch out by
sensing Rdson of
Synchronous MOSFET
n No negative spike at Vout during startup and
shutdown
APPLICATIONS
n Graphic Card on board converters
n Memory Vddq Supply
n On board DC to DC such as 2V to 3.3V, 2.5V or
1.8V
n ADSL Modem
TYPICAL APPLICATION
D1
MBR0530T1
1
BST
Hdrv
SW
OCP
Ldrv
Pgood
C5
1uF
C7
0.1uF
2
10
9
3.7kR11
3
5
1k
R10
M1
L1 1uH
M2
+5V
Cin
270uF,18mohm
Co
2x (220uF,12mohm)
Vout
+1.8V,9A
R9
2.61k
20kR1
C8
1nF
R2
16k
Figure 1 - Typical application of 2116
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2116CMTR 0 to 70oC MLPD-10L 300kHz Yes
NX2116ACMTR 0 to 70oC MLPD-10L 600kHz Yes
NX21 16BCMTR 0 to 70oC MLPD-10L 1MHz Yes
NX2117CUTR 0 to 70oC MSOP-10L 300kHz Yes
NX2117ACUTR 0 to 70oC MSOP-10L 600kHz Yes
Rev. 3.0
03/14/06
1
Page 2
NX2116/2116A/2116B/2117/2117A
θ≈52/
CW
CW
θ≈200/
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage .................... -0.3V to 6.5V
BST to GND Voltage ........................................ -0.3V to 35V
SW to GND ...................................................... -2V to 35V
All other pins .................................................... -0.3V to VCC+0.3V or 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
NX2116/2116A/2116B NX2117/2117A
10-LEAD PLASTIC MLPD 10-LEAD PLASTIC MSOP
o
10
SW
OCP
9
8
COMP
7
FB
EN
6
BST
HDrv
LDrv
VCC
PGOOD
o
JA
1
2
3
Gnd
(PAD)
4
5
10
9
8
7
6
SW
OCP
COMP
FB
EN
BST
HDrv
GND
LDrv
VCC
JA
1
2
3
4
5
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to T
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
REF
Ref Voltage line regulation 0.2 %
Supply Voltage(Vcc)
VCC Voltage Range V
CC
4.5
VCC Supply Current (Static) ICC (Static) Outputs not switching 3 mA
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Supply Current (Static) I
BST
V
Supply Current
BST
BST
)
(Dynamic)
I
CC
(Dynamic)
(Static) Outputs not switching TBD mA
BST
I
BST
(Dynamic)
C
=3300pF
LOAD
FS=300kHz
C
=3300pF
LOAD
FS=300kHz
0.8
5
5.5
V
V
TBD mA
TBD mA
A
Rev. 3.0
03/14/06
2
Page 3
NX2116/2116A/2116B/2117/2117A
(CL=3300pF)
uA
Vref
Ldrv going Low to Hdrv going
PARAMETER SYM Test Condition Min TYP MAX Units
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
3.8
VCC-Hysteresis VCC_Hyst VCC Falling 0.2 V
Oscillator
Frequency F
S
2116, 2117 300 kHz
2116A,2117A 600 kHz
2116B 1000 kHz
Ramp-Amplitude Voltage V
Max Duty Cycle
RAMP
Min Duty Cycle
Error Amplifiers
Transconductance 2000 umho
Input Bias Current Ib 10 nA
EN & SS
Soft Start time Tss mS
NX2116,NX2117 6.8
NX2116A, NX2117A
NX2116B
Enable HI Threshold 1.25 V
Enable Hysterises 150 mV
High Side Driver
4
4.2
1.5 V
95 %
0
V
%
Output Impedance , Sourcing
R
(Hdrv) I=200mA
source
0.9 ohm
Current
Output Impedance , Sinking
R
(Hdrv) I=200mA
sink
ohm0.65
Current
Rise Time THdrv(Rise) V
Fall Time THdrv(Fall) V
Deadband Time
Tdead(L to
H)
BST-VSW
BST-VSW
High, 10%-10%
=4.5V 50 ns
=4.5V 50 ns
ns30
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 0.9 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 0.5 ohm
sink
Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
30
nsDeadband Time Tdead(H to L)SW going Low to Ldrv going
High, 10% to 10%
OCP Adjust
OCP current 40
Power Good(Pgood)
Threshold Voltage as % of
FB ramping up 90 %
Hysteresis 5 %
Rev. 3.0
03/14/06
3
Page 4
NX2116/2116A/2116B/2117/2117A
PIN DESCRIPTIONS
PIN SYMBOL PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to
VCC
BST
and connected to this pin and ground pin. The maximum rating of this pin is 5V.
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is
placed as close as possible to and connected to these pins and respected SW pins.
GND
FB
OCP
SW
HDRV
LDRV
PGOOD
Ground pin.
This pin is the error amplifier inverting input. It is connected via resistor divider to the
output of the switching regulator to set the output DC voltage. When FB pin voltage is
lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching
cycles.
This pin is connected to the drain of the external low side MOSFET via resistor and is the
input of the over current protection(OCP) comparator. An internal current source 40uA is
flown to the external resistor which sets the OCP voltage across the Rdson of the low side
MOSFET. Current limit point is this voltage divided by the Rds-on. Once this threshold is
reached the Hdrv and Ldrv pins are latched out.
This pin is connected to source of high side FET and provides return path for the high side
driver. It is also used to hold the low side driver low until this pin is brought low by the
action of high side turning off. LDRV can only go high if SW is below 1V threshold .
High side gate driver output.
Low side gate driver output.
An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc.
When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI
state.
Rev. 3.0
03/14/06
EN
COMP
A resistor divider is connected from the respective switcher BUS voltages to these pins
that holds off the controller's soft start until this threshold is reached. An external low cost
Transistor can be connected to this pin for external enable control.
This pin is the output of error amplifier and is used to compensate the voltage control
feedback loop. This pin can also be used to perform a shutdown if pulled lower than 0.3V.
4
Page 5
BLOCK DIAGRAM
NX2116/2116A/2116B/2117/2117A
VCC
EN
FB
COMP
GND
Bias
Generator
1.25/1.15
START
Digital
start Up
0.8V
1.25V
ramp
START
0.8V
OSC
UVLO
0.6V
CLAMP
S
R
1.3V
CLAMP
FB
0.6V
Q
POR
OC
START
Latch Out
Hiccup Logic
PWM
OC
OC
Control
Logic
OCP
comparator
FB
0.9Vref
/0.85Vref
BST
HDRV
SW
VCC
LDRV
40uA
OCP
PGOOD
Rev. 3.0
03/14/06
Figure 2 - Simplified block diagram of the NX2116
5
Page 6
NX2116/2116A/2116B/2117/2117A
RIPPLEINS
1
IVF
0.39A12V600kHz
=2.55A
SOUT
==Ω
ESR=7.8m
ERIPPLE
12m2.56A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2116A,
the schematic is figure 1.
VIN = 12V
VOUT=1.8V
FS=600kHz
IOUT=9A
DVRIPPLE <=20mV
DVDROOP<=100mV @ 9A step
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
V-VV
L=
I=kI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.3, then
L=
L=0.94uH
Choose inductor from COILCRAFT DO3316P102HC with L=1uH is a good choice.
Current Ripple is recalculated as
INOUT OUT
OUT
∆
××
×
12V-1.8V1.8V1
OUT
OUT
××
×
...(1)
V-VV
∆××
I=
RIPPLE
INOUT OUT
LVF
OUTINS
12V-1.8V1.8v1
1uH12V600kHz
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
∆
tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP
2R5TPE220MC with 12mΩ are chosen.
integer. Choose N =2.
desire
If low ESR is required, for most applications, mul-
ESRI
N
=
Number of Capacitor is calculated as
Ω×
=
N
N =1.5
The number of capacitor has to be round up to a
If ceramic capacitors are chosen as output ca
20mV
is the value of output capacitors.
OUT
V
RIPPLE
∆
I2.55A
RIPPLE
20mV
×∆
V
∆
RIPPLE
RIPPLE
××
8FC
...(5)
...(3)
...(4)
Rev. 3.0
03/14/06
6
Page 7
NX2116/2116A/2116B/2117/2117A
8600kHz100uF
DROOPTRAN
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.56H
=µ
12m220F2.36us
2
1.3×∆=+×τ
pacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors .
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.55A
RIPPLE
10.4mV
=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
V<V∆∆
@ step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI
transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the following equation.
VESRI
overshootstep
where τ is the a function of capacitor, etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
2.56A
××
STEP
V
OUT
2LC
××
OUT
...(6)
...(7)
STEP
...(8)
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤
is true. In that case, the
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 9A load step.
If the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is
used, the critical inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
12m220F1.8V
9A
The selected inductor is 1uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitors is
LI
×∆
step
τ=−×
V
OUT
1H9A
µ×
=−Ω×µ=
1.8V
ESRI
N
=+
∆×××∆
12m9A
Ω×
100mV
21H220F100mV
×µ×µ×
ESRC
EE
Estep
V2LCV
tranEtran
1.8V
V
OUT
(2.36us)
×
2
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
Rev. 3.0
03/14/06
7
Page 8
NX2116/2116A/2116B/2117/2117A
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient
response,compensator is employed to provide highest
possible bandwidth and enough phase margin.Ideally,the
Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency,
phase margin greater than 50o and the gain crossing
0dB with -20dB/decade. Power stage output capacitors
usually decide the compensator type. If electrolytic
capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower
than crossover frequency. Otherwise type III compensator should be chosen.
1
2RC
×π××
42
1
2(RR)C
×π×+×
233
1
2RC
×π××
33
1
CC
×
2R
×π××
4
CC
12
+
12
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 4.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.
Zin
Vout
Zf
C1
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev. 3.0
03/14/06
R3
C2
R4
R2
C3
Fb
gm
Ve
R1
Vref
Figure 3 - Type III compensator using
transconductance amplifier
8
Page 9
NX2116/2116A/2116B/2117/2117A
21uH440uF
26m440uF
==Ω
R=16k
=(-)
220k7.6kHz60.3kHz
=440uF
20.757.6kHz17.4k
×π×××Ω
217.4k300kHz
260.3kHz1nF
Case 1: FLC<FO<F
power stage
LC
F
Gain(db)
loop gain
compensator
F
F
Z1 Z2
ESR
40dB/decade
ESR
F
20dB/decade
F
O
P1
F
Choose R1=16kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate R
and C3 with the crossover
4
ESR
.
frequency at 1/10~ 1/5 of the switching frequency. Set
FO=50kHz.
C=(-)
111
3
2RFF
×π×
×π×Ω
×
2z2p1
111
×
=916pF
V2FL
OSCO
R=C
4out
VC
1.5V250kHz1uH
12V1nF
=17.2k
×π××
××
in3
×π××
××
Ω
Choose C3=1nF, R4=17.4kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
F
P2
double pole by equation (11).
Figure 4 - Bode plot of Type III compensator
Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<F
1.Calculate the location of LC double pole F
and ESR zero F
and FO<=1/10~1/5F
ESR,
.
ESR
F
=
LC
2LC
×π××
=
s.
LC
1
OUTOUT
1
×π××
7.6kHz
=
F
=
ESR
2ESRC
×π××
=
×π×Ω×
60.3kHz
=
1
OUT
1
2. Set R2 equal to 20kΩ.
×
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
20k0.8V
1
2FR
×π××
Z14
1
C
=
2
=
1.6nF
=
Choose C2=1.5nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
30pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=33pF
7. Calculate R3 by equation (13).
1
2FC
×π××
P13
1
×π××
R
=
3
=
2.64k
=Ω
Choose R3=2.61kΩ.
Rev. 3.0
03/14/06
9
Page 10
NX2116/2116A/2116B/2117/2117A
21uH3000uF
26.5m3000uF
==Ω
R=8k
=(-)
210k2.9kHz8.2kHz
=3.5nF
28.2kHz3.3nF
1.5V260kHz1uH10k5.9k
12V6.5m10k5.9k
×π××Ω×Ω
ΩΩ+Ω
20.752.9kHz26.7k
×π×××Ω
226.7k300kHz
Case 2: FLC<F
power stage
Gain(db)
loop gain
compensator
F
Z1 Z2
ESR<FO
LC
F
ESR
F
F
40dB/decade
F
F
P1
O
20dB/decade
F
P2
2. Set R2 equal to 10kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
10k0.8V
×
Choose R1=8kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
4. Calculate C3 .
C=(-)
111
3
2RFF
×π×
×π×Ω
×
2z2p1
111
×
Choose C3=3.3nF.
5. Calculate R3 .
1
2FC
×π××
P13
1
×π××
R
=
3
=
5.9k
=Ω
Choose R3 =5.9kΩ.
6. Calculate R4 with FO=60kHz.
Ω×
ESR
.
Figure 5 - Bode plot of Type III compensator
(FLC<F
ESR<FO
)
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<F
and FO<=1/10~1/5Fs is shown
ESR<FO
as the following steps. Here two SANYO MV-WG1500
with 13 mΩ is chosen as output capacitor.
1. Calculate the location of LC double pole F
and ESR zero F
F
=
LC
=
.
ESR
1
2LC
×π××
OUTOUT
1
LC
×π××
2.9kHz
=
F
=
ESR
2ESRC
=
8.2kHz
=
1
×π××
OUT
1
×π×Ω×
R=
=
=26.9k
V2FLRR
4
VESRRR
×π×××
OSCO23
××
in23
+
××
Ω
Choose R4=26.7kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
2nF
=
Choose C2=2.2nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
20pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=22pF.
Rev. 3.0
03/14/06
10
Page 11
NX2116/2116A/2116B/2117/2117A
Gain=gR ... (15)
F= ... (16)
F ... (17)
21uH3000uF
26.5m3000uF
==Ω
R=800
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
Type II compensator can be realized by simple RC
circuit without feedback as shown in figure 7. R3 and C
introduce a zero to cancel the double pole effect. C
introduces a pole to suppress the switching noise. The
following equations show the compensator pole zero location and constant gain.
R
1
××
m3
R+R
12
1
2RC
×π××
31
1
2RC
×π××
32
power stage
loop gain
40dB/decade
20dB/decade
z
≈
p
Gain(db)
Vout
R2
Fb
1
2
R1
Vref
gm
Ve
R3
C2
C1
Figure 7 - Type II compensator with
transconductance amplifier
For this type of compensator, FO has to satisfy
FLC<F
tor design. Input voltage is 12V, output voltage is 1.8V,
output inductor is 1uH, output capacitors are two 1500uF
with 13mΩ electrolytic capacitors.
and ESR zero F
<<FO<=1/10~1/5F
ESR
s.
The following is parameters for type II compensa-
1.Calculate the location of LC double pole F
.
ESR
F
=
LC
2LC
×π××
=
1
OUTOUT
1
×π××
2.9kHz
=
LC
compensator
F
Figure 6 - Bode plot of Type II compensator
Rev. 3.0
03/14/06
F
=
ESR
2ESRC
Gain
F
F
LC
Z
ESR
P
F
F
O
8.2kHz
×π××
=
×π×Ω×
=
1
OUT
1
2.Set R2 equal to 1kΩ.
RV
2REF
1
V-V1.8V-0.8V
OUT REF
Ω×
1k0.8V
×
Choose R1=806Ω.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=60kHz.
4.Calculate R3 value by the following equation.
11
Page 12
NX2116/2116A/2116B/2117/2117A
12V6.5m2.0mA/V
28.2k0.752.9kHz
p
F
8.2k300kHz
OUT
REF
2REF
OUT REF
IID1-D
4.Calculate R3 value by the following equation.
V2FLV
OSCOOUT
R=
3
VRgV
1.5V260kHz1uH1
=
=8.15k
Choose R3 =8.2kΩ.
5. Calculate C1 by setting compensator zero F
at 75% of the LC double pole.
C=
1
2RF
=
=8.9nF
Choose C1=8.2nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
=129pF
Choose C1=120pF.
Output Voltage Calculation
Output voltage is set by reference voltage and ex-
ternal voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation and picture show the relationship between
V ,
V and voltage divider..
R=
1
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
×π××
×××
inESRmREF
×π××
××
1.8V
×
0.8V
1
Ω
Ω
1
×π××
3z
1
×π×Ω××
1
RF
π××
3s
1
π×Ω×
RV
×
V-V
...(18)
Z
Vout
R2
Fb
R1
Vref
Voltage divider
Figure 8 - Voltage divider
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
=××
RMSOUT
V
OUT
D
=
V
IN
...(19)
VIN = 12V, VOUT=1.8V, IOUT=9A, using equation (19),
the result of input RMS current is 3.2A.
For higher efficiency, low ESR capacitors are recommended. One Sanyo OS-CON 16SP180M 16V 180uF
20mΩ with 3.4A RMS rating is chosen as input bulk
capacitors.
Power MOSFETs Selection
The power stage requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3709Z are
used. They have the following parameters: VDS=30V,R
=6.5mΩ,Q
GATE
=17nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
DSON
Rev. 3.0
03/14/06
12
Page 13
NX2116/2116A/2116B/2117/2117A
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
2
(9V1.25V)R
SWLDSON
IR+V
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
2
×××
2
K
+
...(20)
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3709Z datasheet. Conduc-
tion loss should not exceed package rating or overall
system thermal budget.
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
loss can be approximated.
1
2
...(21)
where IOUT is output current, TSW is the sum of T
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Switching loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
...(22)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V
is the low
LGS
side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
Soft Start and Enable
NX2116 has digital soft start for switching controller and has one enable pin for this start up. When the
Power Ready (POR) signal is high and the voltage at
enable pin is above 1.25V the internal digital counter
starts to operate and the voltage at positive input of Error
amplifier starts to increase, the feedback network will
force the output voltage follows the reference and starts
the output slowly. After 2048 cycles, the soft start is
complete and the output voltage is regulated to the de-
sired voltage decided by the feedback resistor divider.
Vbus
+
OFF
ON
10k
R1
R2
EN
1.25V/
1.15V
POR
Digital
start
up
Figure 9 - Enable and Shut down the NX2116
with Enable pin.
The start up of NX2116 can be programmed through
resistor divider at Enable pin. For example, if the input
bus voltage is12V and we want NX2116 starts when Vbus
is above 9V. We can select using the following equa-
R
tion.
−×
=
R
1
1.25V
The NX2116 can be turned off by pulling down the
Enable pin by extra signal MOSFET as shown in the
above Figure. When Enable pin is below 1.25V, the digital soft start is reset to zero. In addition, all the high side
and low side driver is off and no negative spike will be
generated during the turn off.
Over Current Protection
Over current protection is achieved by sensing current through the low side MOSFET. An internal current
source of 40uA flows through an external resistor connected from OCP pin to SW node sets the over current
protection threshold. When synchronous FET is on, the
voltage at node SW is given as
V=-IR×
The voltage at pin OCP is given as
×
OCPOCPSW
When the voltage is below zero, the over current
occurss as shown in figure 10.
Rev. 3.0
03/14/06
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Page 14
vbus
OCPOCP
DSON
===Ω
R3.656k
OCP
I
40uA
OCP
comparator
OCP
SW
OCP
R
Figure 10 - Over current protection
The over current limit can be set by the following
equation
×
IR
=
I
SET
×
KR
NX2116/2116A/2116B/2117/2117A
If MOSFET R
=6.5mΩ, the worst case thermal
DSON
consideration K=1.5 and the current limit is set at 15A,
then
IKR
SETDSON
OCP
Choose R
I40uA
OCP
=3.7kΩ
OCP
××Ω
15A1.56.5m
××
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the
connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to
reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more sensitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.
Rev. 3.0
03/14/06
14
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