Page 1
Evaluation board available.
NX2114/2114A
300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product
DESCRIPTION
The NX2114 controller IC is a synchronous Buck controller IC designed for step down DC to DC converter
applications. Synchronous control operation replaces
the traditional catch diode with an Nch MOSFET resulting in improved converter efficiency. Although the NX2114
controller is optimized to convert single 5V bus voltages
to supplies as low as 0.8V output voltage, however using a few external components it can also be used for
other input supplies such as 12V input (See NX2113
data sheet for more optimized solution). The NX2114
operates at 300kHz while 2114A is set at 600kHz
operation which together with less than 50 nS of dead
band provides an efficient and cost effective solution.
Other features of the device are:
Internal digital soft start; Vcc undervoltage lock out; Output undervoltage protection with digital filter and shutdown capability via the enable pin.
L2 1uH
D1 MBR0530T1
1
BST
Hdrv
SW
NX2114
Ldrv
ON
OFF
R6
R7
10k
10k
Vin
+5V
C4
47uF,70mohm
47uF,70mohm
2N3904
C1
47pF
C8
C2
1.5nF
R4
22.1k
7
6
C6
1uF
Comp
Fb
5
Vcc
R5
10
Gnd
3
FEATURES
n Synchronous Controller in 8 Pin Package
n Bus voltage operation from 2V to 25V
n Single 5V Supply Operation
n Short protection with feedback UVLO
n Internal 300kHz for 2114 and 600kHz for 2114A
n Internal Digital Soft Start Function
n Shut Down via pulling comp pin low
n Pb-free and RoHS compliant
APPLICATIONS
n Graphic Card on board converters
n Memory Vddq Supply in mother board applications
n On board DC to DC such as
5V to 3.3V, 2.5V or 1.8V
n Hard Disk Drive
n Set Top Box
TYPICAL APPLICATION
C5
C7
0.1uF
2
8
4
1uF
M1
L1 1.5uH
M2
Cin
220uF,12mohm
Co
2 x (220uF,15mohm)
Vout
+1.6V,6A
Rev. 4.0
06/20/06
R1
R3
1.5k
10.2k
C3
2.2nF
R2
10.2k
Figure1 - Typical application of 2114
ORDERING INFORMATION
Device Temperature Package Frequency Pb-Free
NX2114CSTR 0 to 70oC SOIC-8L 300kHz Yes
NX2114ACSTR 0 to 70oC SOIC-8L 600kHz Yes
1
Page 2
NX2114/2114A
130CW
θ≈/
ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to GND & BST to SW voltage ................... 6.5V
BST to GND Voltage ...................................... 35V
Storage Temperature Range ............................. -65oC to 150oC
Operating Junction Temperature Range ............. -40oC to 125oC
NOTE1: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
8-PIN PLASTIC SOIC (S)
o
8
SW
7
Comp
6
Fb
5
Vcc
BST
HDrv
Gnd
LDrv
JA
1
2
3
4
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to T
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER SYM Test Condition Min TYP MAX Units
Reference Voltage
Ref Voltage V
Ref Voltage line regulation 0.1 %
Supply Voltage(Vcc)
VCC Voltage Range V
VCC Supply Current (Static) ICC (Static) Outputs not switching 2.1 mA
VCC Supply Current
(Dynamic)
Supply Voltage(V
V
Supply Current (Static) I
BST
V
Supply Current
BST
(Dynamic)
BST
)
REF
CC
I
CC
(Dynamic)
(Static) Outputs not switching 0.15 mA
BST
I
BST
(Dynamic)
4.5V<Vcc<5.5V
C
=3300pF FS=300kHz 5 mA
LOAD
C
=3300pF FS=300kHz 5 mA
LOAD
4.5
0.8
5
5.5
V
V
A
Under Voltage Lockout
VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.22 V
Rev. 4.0
06/20/06
4.2
V
2
Page 3
NX2114/2114A
Fsw=300Khz, 2114
3.4
PARAMETER SYM Test Condition Min TYP MAX Units
SS
Soft Start time Tss
Oscillator (Rt)
Frequency F
S
2114 300 kHz
2114A 600 kHz
Ramp-Amplitude Voltage V
RAMP
Max Duty Cycle
Min Duty Cycle
1.7 V
94 %
0
Error Amplifiers
Transconductance 1900 umho
Input Bias Current Ib 10 nA
Comp SD Threshold 0.3 V
FB Under Voltage Protection
FB Under voltage threshold 0.4 V
High Side Driver(CL=3300pF)
R
(Hdrv) I=200mA
source
1.1 ohmOutput Impedance , Sourcing
Current
Output Impedance , Sinking
R
(Hdrv) I=200mA
sink
Current
Output Sourcing Current V
Output Sinking Current V
BST-VHDRV
HDRV-VSW
=5V 2 A
=5V 2 A
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(L to H)Ldrv going Low to Hdrv
30 ns
going High, 10%-10%
mS
%
ohm0.8
Low Side Driver (CL=3300pF)
Output Impedance, Sourcing
R
(Ldrv) I=200mA 1.1 ohm
source
Current
Output Impedance, Sinking
R
(Ldrv) I=200mA 0.5 ohm
sink
Current
Output Sourcing Current V
Output Sinking Current V
PVCC-VLDRV
-PGND=5V 4 A
LDRV
=5V 2 A
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv
30 ns
going High, 10% to 10%
Rev. 4.0
06/20/06
3
Page 4
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 BST
This pin supplies voltage to the high side driver. A high frequency
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.
NX2114/2114A
2 HDRV
3 GND
4 LDRV
5 Vcc
6 FB
7 COMP
8 SW
High side MOSFET gate driver.
Ground pin.
Low side MOSFET gate driver.
Voltage supply for the internal circuit as well as the low side MOSFET gate
driver. A 1uF high frequency ceramic capacitor must be connected from this pin
to GND pin.
This pin is the error amplifier inverting input. This pin is also connected to the
output UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV
outputs are latched off.
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut
down pin. When this pin is pulled below 0.3V, both drivers are turned off and
internal soft start is reset.
This pin is connected to the source of the high side MOSFET and provides
return path for the high side driver.
Rev. 4.0
06/20/06
4
Page 5
BLOCK DIAGRAM
VCC
5
UVLO
Q
Q
DRIVER
S
R
OSC
0.3V
NX2114/2114A
1
BST
2
Hdrv
8
SW
4
Ldrv
3
GND
7
COMP
6
FB
LATCH
DIGITAL SS
TIMER
VREF
Figure 1 - Simplified block diagram of the NX2114
0.4V
Rev. 4.0
06/20/06
5
Page 6
Demoboard design and waveforms
Vin
L2 1uH
sdfd
NX2114/2114A
+5V
C4
47uF,70mohm
47uF,70mohm
C8
C1
47pF
R2
10.2k
Bill of Material
R5
C2
1.5nF
R4
22.1k
7
6
C6
1uF
Comp
Fb
10
5
Vcc
D1 1N5819
1
BST
Hdrv
SW
NX2114
Ldrv
C7
0.1uF
2
8
4
M1
M2
Gnd
3
R1
10.2k
R3
1.5kohm
C3
2.2nF
Figure 2 - demoboard design on NX2114
C5
1uF
L1 1.5uH
Cin
220uF,12mohm
Co
2 x (220uF,15mohm)
Vout
+1.6V,6A
Name Component description Vendor Vendor P/N Number
R1 10.2k 1% chip resistor 1
R2 10.2k 1% chip resistor 1
R3 1.5k 1% chip resistor 1
R4 22.1k 1% chip resistor 1
sdfdsf
R5 10 chip resistor 1
C1 47pF ceramic 1
C2 1.5nF ceramic 1
C3 2.2nF ceramic 1
C4,C8 47uF,16V,70mohm,SMD Sanyo 16TQC47M 1
C5,C6 1uF ceramic 1
C7 0.1uF ceramic 1
C
IN
C
O
220uF,6.3V,12mohm,SMD Sanyo 6TPD220M 1
220uF,4V,15mohm,SMD Sanyo 4TPE220MF 2
D1 Diode D1N5819 1
M1,M2 MOSFET Fairchild FDS6294 1
L1 1.5uH,6.8A Coilcraft DO3316P-152 1
L2 1uH,6.4A Coilcraft DO3316P-102 1
Note: To make sure short circuit protection of device functions correctly, C8 and R5 are necessary for
filtering noise in single power supply design.
Rev. 4.0
06/20/06
6
Page 7
Vin=5V,Vout=1.6V
95
Efficiency (%) f
90
85
80
75
70
0 1 2 3 4 5 6
Current (A)
NX2114/2114A
Figure 3: Output efficiency
Figure 5: Start up time
Figure 4: Voltage ripple @1.6 V output
voltage, 7A output current
Figure 6: Output voltage transient
response for load curent 0A-6A
Figure 7: Output voltage droop during
transient(0A-6A)
Rev. 4.0
06/20/06
Figure 8: Startup operation waveform
7
Page 8
NX2114/2114A
RIPPLEINS
1LIVF
0.46A5V300kHz
=2.4A
SOUT
==Ω
ESR=8.6m
ERIPPLE
15m2.3A
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2114, the
schematic is figure 2.
VIN = 5V
VOUT=1.6V
IOUT=6A
DVRIPPLE <=20mV
DVDROOP<=60mV @ 6A step
Output Inductor Selection
The selection of inductor value is based on
inductor ripple current, power rating, working frequency
and efficiency. Larger inductor value normally means
smaller ripple current. However if the inductance is
chosen too large, it brings slow response and lower
efficiency. Usually the ripple current ranges from 20%
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
various application requirements. The inductor value
can be calculated by using the following equations:
V-VV
INOUT OUT
=××
OUT
IkI
RIPPLEOUTPUT
where k is between 0.2 to 0.4.
Select k=0.4, then
L=
L=1.51uH
Choose inductor from COILCRAFT DO3316P-152
with L=1.5uH is a good choice.
Current Ripple is recalculated as
∆
=×
5V-1.6V1.6V1
OUT
OUT
××
×
...(1)
V-VV
I=
∆××
RIPPLE
INOUT OUT
LVF
OUTINS
5V-1.6V1.6v1
1.5uH5v300kHz
××=
1
...(2)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
∆
I
∆=×∆+
VESRI
RIPPLERIPPLE
Where ESR is the output capacitors' equivalent
series resistance,C
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically determines the output voltage ripple.
∆
tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP
4TPE220MF with 15mΩ are chosen.
integer. Choose N =2.
desire
If low ESR is required, for most applications, mul-
ESRI
N
=
Number of Capacitor is calculated as
Ω×
=
N
N =1.8
The number of capacitor has to be round up to a
20mV
is the value of output capacitors.
OUT
V
RIPPLE
∆
I2.3A
RIPPLE
20mV
×∆
V
∆
RIPPLE
RIPPLE
××
8FC
...(5)
...(3)
...(4)
Rev. 4.0
06/20/06
8
Page 9
NX2114/2114A
8300kHz100uF
DROOPTRAN
2
∆=×∆+×τ
OUTcrit
ESRCifLL
OUTOUTEEOUT
crit
LL
2
=+×τ
EEcrit
ESRCifLL
0.88H
=µ
15m220F2.3us
2
1.7×∆=+×τ
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated
to determine the overall ripple. Usually when this type of
capacitors are selected, the amount of capacitance per
single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple
capacitors.
For example, one 100uF, X5R ceramic capacitor
with 2mΩ ESR is used. The amount of output ripple is
∆=Ω×+
V2m2.3A
RIPPLE
4.6mV9.6mV13.2mV
=+=
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as:
V<V∆∆
@ step load DI
During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI
sient load, if assuming the bandwidth of system is high
enough, the overshoot can be estimated as the following
equation.
VESRI
overshootstep
where τ is the a function of capacitor, etc.
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
where
ESRCVESRCV
××××
==
II
∆∆
stepstep
L
crit
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected output inductor is smaller than the critical inductance, the
2.3A
××
STEP
STEP
V
OUT
2LC
××
OUT
...(6)
...(7)
...(8)
tran-
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and
≤
is true. In that case, the
transient spec is dependent on the ESR of capacitor.
In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following
ESRI
×∆
N
Estep
V2LCV
∆×××∆
tranEtran
V
OUT
...(9)
where
0ifLL
LI
×∆
τ=
V
OUT
≤
crit
step
−×≥
...(10)
For example, assume voltage droop during transient is 100mV for 6A load step.
If the POSCAP 2R5TPE220MC (220uF, 12mΩ ) is
used, the critical inductance is given as
ESRCV
××
EEOUT
==
I
∆
step
Ω×µ×
L
crit
15m220F1.6V
6A
The selected inductor is 1.5uH which is bigger than
critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance.
number of capacitors is
LI
×∆
step
τ=−×
V
OUT
1.5H6A
µ×
=−Ω×µ=
1.6V
ESRI
N
15m6A
Ω×
=+
60mV
21.5H220F60mV
×µ×µ×
ESRC
EE
Estep
V2LCV
∆×××∆
tranEtran
1.6V
V
×
OUT
2.3us
2
=
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we can choose N=2.
Rev. 4.0
06/20/06
9
Page 10
NX2114/2114A
F ...(11)
F ...(12)
F ...(13)
F ...(14)
OUT minin1
V1gZZ/R
f
OUT in
Z
VZ
−
It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
Compensator Design
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with 20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should
be chosen.
1
2RC
×π××
42
1
2(RR)C
×π×+×
233
1
2RC
×π××
33
1
CC
×
2R
×π××
4
CC
12
+
12
=
Z1
=
Z2
=
P1
=
P2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator. Their locations are shown in figure 10.
The transfer function of type III compensator for
transconductance amplifier is given by:
V 1gZ
e mf
=
−×
+×+
For the voltage amplifier, the transfer function of
compensator is
V
e
=
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm
is desirable.
Zin
Vout
Zf
C1
A. Type III compensator design
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The following figures and equations show how to realize the type III
compensator by transconductance amplifier.
Rev. 4.0
06/20/06
R3
C2
R4
R2
C3
Fb
gm
Ve
R1
Vref
Figure 9 - Type III compensator using
transconductance amplifier
10
Page 11
21.5uH440uF
27.5m440uF
20.756.2kHz22.1k
×π×××Ω
222.1k150kHz
248kHz2.2nF
FO=30kHz.
=(-)
210k6.2kHz48kHz
=2.2nF
=440uF
NX2114/2114A
power stage
LC
F
Gain(db)
40dB/decade
loop gain
ESR
F
20dB/decade
compensator
F
F
Z1 Z2
Figure 10 - Bode plot of Type III compensator
F
O
F
P1
F
P2
C=(-)
111
3
2RFF
×π×
×
2z2p1
111
×
×π×Ω
V2FL
OSCO
R=C
4out
VC
1.7V230kHz1.5uH
5V2.2nF
=19.2k
×π××
××
in3
×π××
××
Ω
Choose C3=2.2nF, R4=22.1kΩ.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1
2FR
×π××
Z14
1
C
=
2
=
1.55nF
=
Design example for type III compensator are in
order. The crossover frequency has to be selected as
FLC<FO<F
1. Calculate the location of LC double pole F
and ESR zero F
and FO<=1/10~1/5F
ESR,
.
ESR
F
=
LC
2LC
×π××
=
s.
LC
1
OUTOUT
1
×π××
6.2kHz
=
F
=
ESR
2ESRC
=
48kHz
=
1
×π××
OUT
1
×π×Ω×
2. Set R2 equal to10.2kΩ, then R1= 10.2kΩ.
3. Set zero FZ2 = FLC and Fp1 =F
ESR
.
4. Calculate R4 and C3 with the crossover
frequency at 1/10~ 1/5 of the switching frequency. Set
Choose C2=1.5nF.
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
C
=
1
=
48pF
=
1
2RF
×π××
4P2
1
×π×Ω×
Choose C1=47pF.
7. Calculate R3 by equation (13).
1
2FC
×π××
P13
1
×π××
R
=
3
=
1.5k
=Ω
Choose R3=1.5kΩ.
Rev. 4.0
06/20/06
11
Page 12
NX2114/2114A
Gain=gR ... (15)
F= ... (16)
F ... (17)
21.5uH1360uF
220.5m1360uF
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensator can be used to compensate the system.
Type II compensator can be realized by simple
RC circuit without feedback as shown in figure 12. R3
and C1 introduce a zero to cancel the double pole
effect. C2 introduces a pole to suppress the switching
noise. The following equations show the compensator
pole zero location and constant gain.
R
1
××
m3
R+R
12
1
2RC
×π××
31
1
2RC
×π××
32
power stage
z
≈
p
Vout
R2
Fb
gm
R1
Vref
Ve
R3
C2
C1
Figure 12 - Type II compensator with
transconductance amplifier
For this type of compensator, FO has to satisfy
FLC<F
an example for type II compensator design, two 680uF
with 41mΩ electrolytic capacitors are used.
and ESR zero F
<<FO<=1/10~1/5F
ESR
s.
The following uses typical design in figure 19 as
1.Calculate the location of LC double pole F
.
ESR
LC
40dB/decade
Gain(db)
loop gain
20dB/decade
compensator
Gain
F
F
F
LC
Z
ESR
P
F
F
O
Figure 11- Bode plot of Type II compensator
1
OUTOUT
1
F
=
LC
2LC
×π××
=
×π××
3.5kHz
=
1
×π××
OUT
1
×π×Ω×
F
=
ESR
2ESRC
=
5.7kHz
=
2.Set R2 equal to10.2kΩ. Using equation 18, the
final selection of R1 is 3.24kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
4.Calculate R3 value by the following equation.
Rev. 4.0
06/20/06
12
Page 13
NX2114/2114A
1220.51.9mA/V
24.51k0.753.5kHz
p
F
p3.74k300kHz
OUT
REF
2REF
OUT REF
R1.6V1.6V/(1/16W)40
=×=Ω
IID1-D
1.6V, the result of R1 is 10kΩ.
V2FL
R=
3
VRgR
1.7V230kHz1.5uH1
=
=4.23k
×π××
OSCO 12
×××
inESRm1
×π××
××
10.2k+3.24k
×
ΩΩ
3.24k
Ω
Ω
R+R
1
Ω
Choose R3 =4.53kΩ.
5. Calculate C1 by setting compensator zero F
Z
at 75% of the LC double pole.
C=
1
=
1
2RF
×π××
3z
1
×π×Ω××
=13.3nF
Choose C1=12nF.
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
C=
2
=
1
pRF
××
3s
1
×Ω×
=235pF
Choose C2=220pF.
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation and picture show the relationship
between
value of R1 value can be set by voltage divider.
V ,
V and voltage divider..
RV
R=
1
×
V-V
...(18)
where R2 is part of the compensator, and the
Choose R2=10kΩ, to set the output voltage at
Vout
R2
Fb
R1
Vref
Voltage divider
Figure 13 - Voltage divider
In general, the minimum output load impedance
including the resistor divider should be less than 5kΩ to
prevent overcharge the output voltage by leakage current (e.g. Error Amplifier feedback pin bias current). A
minimum load for 5kΩ less (<1/16w for most of application) is recommended to put at the output. For example,
in this application,
Vout=1.6V
The power loss is 1/16W less
LOAD
Select minimum load, 1kΩ should be good enough.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply current to the MOSFETs. Usually 1uF
ceramic capacitor is chosen to decouple the high frequency noise. The bulk input capacitors are decided by
voltage rating and RMS current rating. The RMS current
in the input capacitors can be calculated as:
=××
RMSOUT
V
VIN = 5V, VOUT=1.6V, IOUT=6A, using equation
(19), the result of input RMS current is 2.80A.
ommended. One Sanyo TPD series POSCAP 6TPD220M
6V 220uF with 12mΩ is chosen as input bulk capacitor.
OUT
D
=
V
IN
...(19)
For higher efficiency, low ESR capacitors are rec-
Rev. 4.0
06/20/06
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Page 14
NX2114/2114A
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
P=I(1D)RK
×−××
SWINOUTSWS
PVITF
=××××
Power MOSFETs Selection
The NX2114 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two Fairchild FDS6294
are used. They have the following parameters: VDS=30V,
ID =13A, R
There are three factors causing the MOSFET power
loss: conduction loss, switching loss and gate driver loss.
Gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:
where QHGATE is the high side MOSFETs gate
charge, QLGATE is the low side MOSFETs gate charge,
VHGS is the high side gate source voltage, and VLGS is
the low side gate source voltage.
According to equation (20), PGATE =0.03W. This
power dissipation should not exceed maximum power
dissipation of the driver device.
Conduction loss is simply defined as:
P=IDR
HCONOUTDS(ON)
LCONOUTDS(ON)
P=PP
TOTALHCONLCON
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K equals to 1.43 at 125oC
according to FDS6294 datasheet. Using equation (21),
the result of PTOTAL is 0.75W. Conduction loss should
not exceed package rating or overall system thermal
budget.
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
loss can be approximated.
where IOUT is output current, TSW is swithing time,and FS
is switching frequency. Swithing loss PSW is frequency
=14.4mΩ,QGATE =10nC.
DSON
2
×××
2
+
1
2
...(20)
K
...(21)
...(22)
dependent.
Soft Start, Enable and shut Down
The NX2114 has a digital start up. It is based on
digital counter with 1024 cycles. For NX2114 with 300kHz
operation, the start up time is about 3.5ms. For NX2114A
with 600kHz operation, the start up time is about half of
NX2114, 1.75mS.
NX2114/NX2114A can be enabled or disabled by
pulling COMP pin below 0.3V. The function is illustrated
in the following diagram. During the normal operation,
the lowest COMP voltage is clamped to be about 700mV
, the COMP voltage is higher than 0.3V. If external switch
with 10Ω R
or less to pull down COMP pin, when
dson
COMP is below 0.3V, the digital soft start will be reset to
zero. All the drivers will be off. The synchronous buck is
shut off. When external switch is released, and COMP
is above 0.3V, a soft start will initiates and system starts
from the beginning.
2114
Shut
down
FB
Compensation
Network
comp
OFF
ON
0.3V
0.6
1.3V
Clamp
Figure 14 - Enable and Shut down NX2114 by
pulling down COMP pin.
Feedback Under Voltage Shut Down
NX2114 relies on the Feedback Under Voltage Lock
Out (FB UVLO ) to provide short circuit protection. Basically, NX2114 has a comparator compare the feedback
voltage with the FB UVLO threshold 0.4V.
Rev. 4.0
06/20/06
14
Page 15
NX2114/2114A
During the normal operation, if the output is short,
the feedback voltage will be lower than 0.4V and comparator will change the state. After certain internal delay,
both high side and low side driver will be turned off. The
output will be latched. The normal operation should be
achieved by removing the short and recycle the VCC.
Figure 15 - Operation waveforms during short condition.
CH3-bus voltage
5V/DIV
CH2-Vcc voltage
5V/DIV
CH1-Fb voltage
0.5V/DIV
Figure 16 - Operation waveform with start up at
short.
During the start up, the output voltage is discharged
to zero by the synchronous FET. FB voltage starts increase from zero when digital start block operates. Before half of the start up time, the Feedback Under Volt-
CH4-output current
10A/DIV
age Lock Out comparator is disabled. After half of start
up time, the Feedback UVLO comparator is enabled.
The FB UVLO threshold is set to be half of voltage at the
positive input of error amplifier. With this set up, if the
output is short before soft start, the Feedback UVLO
comparator can catch it and turn off the driver. The short
circuit operation waveform during normal operation and
during the soft start are shown as follows.
During the normal operation, Feedback UVLO
will take the role. But during the soft start, due to the
input voltage dropping, UVLO Vcc will take the role,
hiccup happens.
The Feedback UVLO can provide short circuit protection under certain conditions. However, since feedback does not have accurate information of current, this
protection only provides certain level of over current protection. MOSFET should design such that it can survive
with high pulse current for a short period of time.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small signal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switching power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is
recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
Rev. 4.0
06/20/06
15
Page 16
cap which usually is 1uF need to be practically touching the drain pin of the upper MOSFET, a plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible. A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
NX2114/2114A
Rev. 4.0
06/20/06
16
Page 17
TYPICAL APPLICATION
Single Supply 5V Input
NX2114/2114A
Vin
+5V
C1
150pF
C4
33uF
C3
33uF
C2
8.2nF
R4
7k
7
6
C6
1uF
Comp
Fb
5
Vcc
R3
10
1
BST
NX2114
L2 1uH
D1 MBR0530T1
2
Hdrv
8
SW
4
Ldrv
C7
0.1uF
C5
1uF
M1
L1 1.5uH
M2
Cin
2 x (470uF,60mohm)
Co
4 x (330uF,80mohm)
Gnd
3
R1
10
k 1%
4.7
R2
k 1%
Figure 17 - Application of NX2114 for 5V input and 2.5V output with electrolytic capacitors
Vin
L2 1uH
Vout
+2.5V,10A
+5V
C1
4.7pF
C3
22uF
C4
22uF
C2
330pF
R4
120
7
k
6
C6
1uF
5
Vcc
Comp
Fb
R3
10
1
BST
NX2114A
Hdrv
SW
Ldrv
2
8
4
D1
MBR0530T1
C7
0.1uF
C5
1uF
M1
L1 3.3uH
M2
Cin
3 x 22uF
X7R
Co
10 x 22uF
X7R
Vout
+1.2V,4A
Gnd
3
R1
10
R3
787
k 1%
C3
820pF
R2
20
k 1%
Figure 18 - Application of NX2114 A for 5V input and 1.2V output with ceramic output capacitors
Rev. 4.0
06/20/06
17
Page 18
TYPICAL APPLICATIONS(CONT')
Dual power supply (+5V BIAS,+12V BUS)
NX2114/2114A
Vin
+12V
Vin
+5V
L2 1uH
C3
33uF
D1 MBR0530T1
C6
5
Vcc
1
BST
Hdrv
SW
NX2114
Ldrv
C4
0.1uF
2
8
4
1uF
1R8
k
5R7
10
R5
k
680R6
k
2N3904
2N3904
C1
270pF
3.74
C2
15nF
R4
7
k
6
Comp
Fb
C5
1uF
M1
L1 1.5uH
M2
Cin
2 x (47uF,60mohm)
Vout
Co
2 x (680uF,41mohm)
+3.3V,10A
Gnd
3
10.2R1
k 1%
3.24
R2
k 1%
Figure 19 -Application of NX2114 for 5V bias and 12V input bus
Single power supply (+11V to +24V BUS)
Vin
+11~25V
C4
33uF
TL431
3
C1
220pF
R5
k
2N3904
R6
k
10
R7
10
k
7
C2
2.7nF
R4
15
k
6
R2
10
k 1%
C6
2.2uF
5
Vcc
Comp
Fb
L2 1uH
Gnd
3
R1
R3
787
D1 MBR0530T1
1
BST
Hdrv
SW
NX2114
Ldrv
10
k 1%
C3
1nF
C5
1uF
C7
0.1uF
2
8
4
M1
L1 5uH
M2
Cin
2 x (47uF,60mohm)
Co
2 x (680uF,41mohm)
Vout
+1.6V,5A
Rev. 4.0
06/20/06
Figure 20 -Application of NX2114 for high input bus application
18
Page 19
SOIC8 PACKAGE OUTLINE DIMENSIONS
NX2114/2114A
Rev. 4.0
06/20/06
19
Page 20
NX2114/2114A
Rev. 4.0
06/20/06
20
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