Datasheet nx2113ds, nx2113 Datasheets

300kHz & 600kHz SYNCHRONOUS PWM CONTROLLER WITH

DESCRIPTION

The NX2113 controller IC is a synchronous Buck con­troller IC designed for step down DC to DC converter
applications. Synchronous control operation replaces the
traditional catch diode with an Nch MOSFET resulting
in improved converter efficiency. The NX2113 controller
is optimized to convert bus voltages from 2V to 25V to
outputs as low as 0.8V voltage using Enable pin to
program the BUS voltage start up threshold. The NX2113
operates at 300kHz while 2113A is set at 600kHz
operation which together with less than 50 nS of dead
band provides an efficient and cost effective solution.
Other features of the device are:
Internal digital soft start; Vcc undervoltage lock out;
Output undervoltage protection with digital filter and shut­down capability via the enable pin.

Evaluation board available.

NX2113/2113A

PROGRAMMABLE BUS UVLO

PRELIMINARY DATA SHEET

Pb Free Product

FEATURES

n Synchronous Controller in 10 Pin Package
n Bus voltage operation from 2V to 25V
n Enable pin allows programmable BUS UVLO
n Less than 50 nS adaptive deadband
n Internal 300kHz for 2113 and 600kHz for 2113A
n Internal Digital Soft Start Function
n Separated power ground and analog ground for

extra noise filtering
n Pb-free and RoHS compliant

APPLICATIONS

n Graphic Card on board converters
n Memory Vcore or Vddq supply
n On board DC to DC such as
12V, 5V to 3.3V, 2.5V or 1.8V
n Hard Disk Drive

ON

OFF

TYPICAL APPLICATION

C6
1uF

6

Vcc

PGnd

3

L2 1uH

1

5

BST

PVcc

Hdrv

SW

NX2113A

Ldrv

Gnd

11

10k 1%R1

C8

R9

1.2k

D1

2.2nF

C5
1uF

C7

0.1uF

2

10

4

M1

L1 1.5uH

M2

Cin

270uF,18mohm

Co
3x (220uF,12mohm)

Vout
+1.6V,10A

Vin

+12V

Vin

+5V

2N3904

R8

10k

R7

10k

C3

47uF

C9

1uF

R5

68k

R6

12.4k

C1

47pF

R3
10

C4

1uF

C2

2.7nF
R4

11k

R2

10k 1%

7

9

8

EN

Comp

Fb

Figure1 - Typical application of 2113A

Rev. 2.0
11/18/05

ORDERING INFORMATION

Device Temperature Package Frequency Pb-Free
NX2113CMTR 0 to 70oC MLPD-10L 300kHz Yes
NX2113CUTR 0 to 70oC MSOP-10L 300kHz Yes

NX2113ACMTR 0 to 70oC MLPD-10L 600kHz Yes

NX2113ACUTR 0 to 70oC MSOP-10L 600kHz Yes

1

NX2113/2113A

θ≈52/

CW

CW

θ≈200/

3.4

ABSOLUTE MAXIMUM RATINGS

Vcc to GND & BST to SW voltage ................... 6.5V

BST to GND Voltage ...................................... 35V

Storage Temperature Range ............................. -65oC to 150oC

Operating Junction Temperature Range ............. -40oC to 125oC

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

10-LEAD PLASTIC MSOP 10-LEAD PLASTIC MLPD

JA

PAD

(Gnd)

o

10

SW

9

Comp

8

Fb

7

EN

6

Vcc

BST

HDrv

PGnd/Gnd

LDrv

PVcc

JA

1
2
3
4
5

o

10

9
8
7
6

SW
Comp
Fb
EN
Vcc

PGnd

PVcc

BST

HDrv

LDrv

1
2
3
4

5

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc = 5V, and TA = 0 to 70oC. Typical values refer to T
= 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient

PARAMETER SYM Test Condition Min TYP MAX Units

Reference Voltage

Ref Voltage V

REF

Ref Voltage line regulation 0.4 %

Supply Voltage(Vcc)

VCC Voltage Range V

CC

VCC Supply Current (Static) ICC (Static) Outputs not switching 2.1 mA
VCC Supply Current
(Dynamic)

Supply Voltage(V

V

Supply Current (Static) I

BST

V

Supply Current

BST

BST

)

(Dynamic)

I

CC

(Dynamic)

(Static) Outputs not switching 0.15 mA

BST

I

BST

(Dynamic)

4.5V<Vcc<5.5V

4.5

C

=3300pF FS=300kHz 5 mA

LOAD

C

=3300pF FS=300kHz 5 mA

LOAD

0.8

5

5.5

V

V

A

Under Voltage Lockout

VCC-Threshold VCC_UVLO VCC Rising
VCC-Hysteresis VCC_Hyst VCC Falling 0.22 V

SS

Soft Start time Tss Fsw=300Khz, 2113

Rev. 2.0
11/18/05

Fsw=600Khz, 2113A

4.1

V

mS

1.7

2

NX2113/2113A

PARAMETER SYM Test Condition Min TYP MAX Units

Oscillator (Rt)

Frequency F

S

2113A 600 kHz
Ramp-Amplitude Voltage V

RAMP

Max Duty Cycle
Min Duty Cycle

Error Amplifiers

Transconductance 2100 umho
Input Bias Current Ib 10 nA

FB Under Voltage Protection

FB Under voltage threshold 0.4 V

EN

Enable Threshold Voltage Enable ramp up 1.25 V
Enable Hysterises 0.2 V

High Side Driver(CL=3300pF)

2113 300 kHz

2.1 V
93 %

0

%

R

(Hdrv) I=200mA

source

1.1 ohmOutput Impedance , Sourcing

Current
Output Impedance , Sinking

R

(Hdrv) I=200mA

sink

ohm0.8

Current
Rise Time THdrv(Rise) V

Fall Time THdrv(Fall) V
Deadband Time Ldrv going Low to Hdrv

Tdead(L to

H)

BST-VSW
BST-VSW

going High, 10%-10%

=4.5V 50 ns
=4.5V 50 ns

ns30

Low Side Driver (CL=3300pF)

Output Impedance, Sourcing

R

(Ldrv) I=200mA 1.1 ohm

source

Current
Output Impedance, Sinking

R

(Ldrv) I=200mA 0.5 ohm

sink

Current
Rise Time TLdrv(Rise) 10% to 90% 50 ns

Fall Time TLdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(H to L)SW going Low to Ldrv

30

ns

going High, 10% to 10%

Rev. 2.0
11/18/05

3

PIN DESCRIPTIONS

PIN # PIN SYMBOL PIN DESCRIPTION
1 BST

This pin supplies voltage to the high side driver. A high frequency
ceramic capacitor of 0.1 to 1 uF must be connected from this pin to SW pin.

NX2113/2113A

2 HDRV
3 PGND/Gnd

4 LDRV
5 PVcc

6 Vcc

7 EN

8 FB

9 COMP

High side MOSFET gate driver.
Power and analog ground pin. For MLPD package, analog ground and power ground

are separated, additional pad pin(11) is available for analog ground.
Low side MOSFET gate driver.

Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to
GND directly.

Voltage supply for the internal circuit as well as the low side MOSFET gate driver. A
1uF high frequency ceramic capacitor must be connected from this pin to GND pin.

Pull up this pin to Vcc for normal operation. Pulling this pin down below 1.25V
shuts down the controller and resets the soft start. This pin can also be used as
a UVLO detector for the bus voltage via a resistor divider.

This pin is the error amplifier inverting input. This pin is also connected to the output
UVLO comparator. When this pin falls below 0.4V, both HDRV and LDRV outputs
are latched off.

This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop.

10 SW

Rev. 2.0
11/18/05

This pin is connected to the source of the high side MOSFET and provides return
path for the high side driver.

4

BLOCK DIAGRAM

NX2113/2113A

VCC

EN

FB

COMP

GND

Bias
Generator

1.25/1.15

START

Digital
start Up

START

1.25V

0.8V

OSC

UVLO

FB

S
R

POR

BST

START

DRVH

SW

0.4
PVCC

DRVL

Q

Rev. 2.0
11/18/05

5

Demo Board Schematic

NX2113/2113A

TP1

2N3904

R13

10k

0

Q3

R14

10k

JP2

JP3

C16

open

1
2

1
2

C25

1uF

C17

open

R6

open

BUS

VCC

C11
47p

R12

68k

C24

1u

R11

12.4k

9

C15

2.7n

R5

11k

8

C12
47u

C13
47u

7

EN

COMP

Fb

VCC1

6

VCC

GND

11

L2

DO1608C-102

R10
OP

R4
10

U1

5

BST

PVCC

Hdrv

SW

Ldrv

1

2
10
4

C14
1u

D1N5819

VCC2

NX2113A

3

PGND

(GND
PAD)

D1

C20

.1u

Hdrv

Ldrv

BUS1

Q1

IRFR3706

4

R1
0

R2
0

4

Q2

IRFR3706

C7

C8
OP

16SP270M

C9

1u

567

8

123

OUT1

567

8

D2

D1N5819

123

L1

DO5010P-781HC

C1

OP

R3
OP

C18

2R5TPE220MC

C21

OUT2

2R5TPE220MC

C22

2R5TPE220MC

R15
2k

1
2

JP5

Rev. 2.0
11/18/05

C19

R7

1.2k

2.2n

R9

10k

R8

10k

Figure 2 - Demoboard design on NX2113A

GND

C2

.1u

J1

1

234

5

6

NX2113/2113A

Bill of Materials

Item Quantity Reference Part Manufacture

1 6 C1,R3,C8,R10,C23,D2 OPEN
2 2 C2,C20 .1uF
3 1 C7 16SP270M SANYO
4 3 C9,C14,C24 1uF
5 1 C11 47pF
6 2 C12,C13 47uF
7 1 C15 2.7nF
8 3 R6,C16,C17 OPEN

9 3 C18,C21,C22 220uF 2R5TPE220MC SANYO
10 1 C19 2.2nF
11 1 C25 1uF
12 2 D1 D1N5819
13 3 JP2,JP3,JP5 CON2
14 2 J1 SCOPE TP Tektronics
15 1 L1 DO5010P-781HC Coilcraft
16 1 L2 DO1608C-102 Coilcraft
17 2 Q1,Q2 IRFR3706 International Rectifier
18 1 Q3 2N3904
19 2 R1,R2 0
20 1 R4 10
21 1 R5 11k
22 2 R8,R9,R13,R14 10k
23 1 R7 1.2k
24 1 R11 12.4k
25 1 R12 68k
26 1 R15 2k
27 1 U1 NX2113 NEXSEM INC.

Rev. 2.0
11/18/05

7

DEMO BOARD WAVEFORM

NX2113/2113A

Figure 3: Output efficiency

Figure 5: Output voltage transient response
for load curent 0A-9A

Figure 4: Voltage ripple @1.6 V output voltage.
(Ch2-ripple, Ch3-Hdrv)

Figure 6: Start up time(Ch1-input volatge,
Ch2-output voltage)

Figure 7: ENABLE function.(Ch1-enable, Ch2-Ldrv,
Ch3-output voltage)

Rev. 2.0
11/18/05

Figure 8: Startup operation waveform

8

NX2113/2113A

RIPPLEINS

1

IVF

0.310A12V600kHz

=3A

SOUT

ESR=6.7m

==Ω

ERIPPLE

12m3A

APPLICATION INFORMATION

Symbol Used In Application Information:

VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple

Design Example

The following is typical application for NX2113A,
the schematic is figure 2.
VIN = 12V
VOUT=1.6V
IOUT=10A
DVRIPPLE <=20mV
DVDROOP<=80mV @ 10A step
FS=600kHz

Output Inductor Selection

The selection of inductor value is based on induc­tor ripple current, power rating, switching frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu­ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli­cation requirements. The inductor value can be calcu­lated by using the following equations:

V-VV

OUT

∆

INOUT OUT

××

×

12V-1.6V1.6V1

OUT

OUT

×

××

...(1)

L=
I=kI

RIPPLEOUTPUT

where k is between 0.2 to 0.4.

Select k=0.3, then

L=
L=0.8uH

Choose inductor from COILCRAFT DO5010P­781HC with L=0.78uH is a good choice.

Current Ripple is recalculated as

V-VV

I=

∆××

RIPPLE

INOUT OUT

LVF

OUTINS

12V-1.6V1.6v1

0.78uH12v600kHz

××=

1

...(2)

Output Capacitor Selection

Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.

Based on DC Load Condition

The amount of voltage ripple during the DC load
condition is determined by equation(3).

∆

I

∆=×∆+

VESRI

RIPPLERIPPLE

Where ESR is the output capacitors' equivalent
series resistance,C

Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.

For this example, POSCAP are chosen as output
capacitors, the ESR and inductor current typically de­termines the output voltage ripple.

∆

tiple capacitors in parallel are better than a big capaci­tor. For example, for 20mV output ripple, POSCAP
2R5TPE220MC with 12mΩ are chosen.

integer. Choose N =2.

desire

If low ESR is required, for most applications, mul-

ESRI

N

=

Number of Capacitor is calculated as

N

=

N =1.8

The number of capacitor has to be round up to a

If ceramic capacitors are chosen as output ca-

Ω×

20mV

is the value of output capacitors.

OUT

V

RIPPLE

I3A

∆

RIPPLE

20mV

×∆

V

∆

RIPPLE

RIPPLE

××

8FC

...(5)

...(3)

...(4)

Rev. 2.0
11/18/05

9

NX2113/2113A

8600kHz100uF

DROOPTRAN

2

∆=×∆+×τ

OUTcrit

ESRCifLL

OUTOUTEEOUT

crit

LL

2

=+×τ

EEcrit

ESRCifLL

0.42H

=µ

12m220F2.24us

2

1.7×∆=+×τ

pacitors, both terms in equation (3) need to be evaluated
to determine the overall ripple. Usually when this type of
capacitors are selected, the amount of capacitance per
single unit is not sufficient to meet the transient specifi­cation, which results in parallel configuration of multiple
capacitors .

For example, one 100uF, X5R ceramic capacitor

with 2mΩ ESR is used. The amount of output ripple is

∆=Ω×+

V2m3A

RIPPLE

6mV6.2mV12.2mV

=+=

3A

××

Although this meets DC ripple spec, however it

needs to be studied for transient requirement.

Based On Transient Requirement

Typically, the output voltage droop during transient

is specified as:

V<V∆∆ @ step load DI

STEP

During the transient, the voltage droop during the
transient is composed of two sections. One Section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well as
input, output voltage. For example, for the overshoot,
when load from high load to light load with a DI

STEP

transient load, if assuming the bandwidth of system is
high enough, the overshoot can be estimated as the fol­lowing equation.

V

VESRI

overshootstep

OUT

2LC

××

OUT

...(6)

where τ is the a function of capacitor, etc.

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(7)

where

ESRCVESRCV

××××

==

II

∆∆

stepstep

...(8)

L

crit

where ESRE and CE represents ESR and capaci­tance of each capacitor if multiple capacitors are used
in parallel.

The above equation shows that if the selected out­put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR

of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-

pacitance is high and

≤

is true. In that case, the

transient spec is dependent on the ESR of capacitor.

In most cases, the output capacitors are multiple
capacitors in parallel. The number of capacitors can be
calculated by the following

ESRI

×∆

N

Estep

V2LCV

∆×××∆

tranEtran

V

OUT

...(9)

where

0ifLL




LI

×∆

τ=




V

OUT



≤

crit

step

−×≥

...(10)

For example, assume voltage droop during tran­sient is 100mV for 10A load step.

If the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is
used, the critical inductance is given as:

ESRCV

××

L

crit

12m220F1.6V

EEOUT

==

I

∆

step

Ω×µ×

10A

The selected inductor is 0.78uH which is bigger
than critical inductance. In that case, the output voltage
transient not only dependent on the ESR, but also ca­pacitance.

number of capacitors is

LI

×∆

step

τ=−×

V

0.78H10A

µ×

=−Ω×µ=

1.6V

ESRI

N

12m10A

Ω×

=+

80mV

21.5H220F80mV

×µ×µ×

ESRC

OUT

Estep

V2LCV

∆×××∆

1.6V

EE

V

OUT

tranEtran

(2.24us)

×

2

≈

The number of capacitors has to satisfy both ripple
and transient requirement. Overall, we can choose N=3.

Rev. 2.0
11/18/05

10

It should be considered that the proposed equa-

F ...(11)

F ...(12)

F ...(13)

F ...(14)

OUT minin1

V1gZZ/R

f

OUT in

Z

VZ

−

tion is based on ideal case, in reality, the droop or over­shoot is typically more than the calculation. The equa­tion gives a good start. For more margin, more capaci­tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es­pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.

Compensator Design

Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with ­20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than cross­over frequency. Otherwise type III compensator should
be chosen.

NX2113/2113A

=

Z1

=

Z2

=

P1

=

P2

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator. Their locations are shown in figure 10.

The transfer function of type III compensator for

transconductance amplifier is given by:

V 1gZ

e mf

For the voltage amplifier, the transfer function of
compensator is

the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm. R1||R2||R3>>1/gm
is desirable.

=

V

e

=

To achieve the same effect as voltage amplifier,

Vout

Zin

1

2RC

×π××

42

1

2(RR)C

×π×+×

233

1

2RC

×π××

33

1

CC

×

2R

×π××

−×

+×+

4

CC

12

+

12

Zf

C1

A. Type III compensator design

For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross­over frequency. In this case, it is necessary to compen­sate the system with type III compensator. The follow­ing figures and equations show how to realize the type III
compensator by transconductance amplifier.

Rev. 2.0
11/18/05

R3

C2

R4

R2

C3

Fb

gm

Ve

R1

Vref

Figure 9 - Type III compensator using
transconductance amplifier

11

NX2113/2113A

20.78uH660uF

24m660uF

211k300kHz

260kHz2.2nF

=(-)

210k7kHz60kHz

=2nF

=660uF

20.757kHz11k

×π×××Ω

smaller than 1/10~ 1/5 of the switching frequency. Set
FO=45kHz.

power stage

LC

F

Gain(db)

40dB/decade

loop gain

ESR

F

20dB/decade

compensator

F

Z1 Z2

F

F

O

F

P1

F

P2

Figure 10 - Bode plot of Type III compensator

Design example for type III compensator are in
order. Use the same power stage requirement as demo
board. The crossover frequency has to be selected as
FLC<FO<F

1.Calculate the location of LC double pole F

and ESR zero F

and FO<=1/10~1/5F

ESR,

.

ESR

F

=

LC

2LC

×π××

=

s.

LC

1

OUTOUT

1

×π××

7kHz

=

F

=

ESR

2ESRC

×π××

=

×π×Ω×

60kHz

=

1

OUT

1

C=(-)

111

3

2RFF

×π×

×

2z2p1

111

×

×π×Ω

V2FL

R=C

4out

VC

2V245kHz0.78uH

12V2.2nF

=11k

×π××

OSCO

××

in3

×π××

××

Ω

Choose C3=2.2nF, R4=11kΩ.

5. Calculate C2 with zero Fz1 at 75% of the LC

double pole by equation (11).

C

2.75nF

=

2

2FR

=

=

1

×π××

Z14

1

Choose C2=2.7nF.

6. Calculate C1 by equation (14) with pole Fp2 at

half the swithing frequency.

C

=

1

2RF

=

48pF

=

1

×π××

4P2

1

×π×Ω×

Choose C1=47pF.

7. Calculate R3 by equation (13).

1

2FC

×π××

P13

1

×π××

R

=

3

=

1.2k

=Ω

Choose R3=1.2kΩ.

2.Set R2 equal to10kΩ, then R1= 10kΩ.

3. Set zero FZ2 = FLC and Fp1 =F

4. Calculate R4 and C3 with the crossover frequency

Rev. 2.0
11/18/05

ESR

.

12

NX2113/2113A

Gain=gR ... (15)

F= ... (16)

F ... (17)

24.7uH1360uF

218m1360uF

R4.7k

==Ω

12V18m2.5mA/V

B. Type II compensator design

If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa­tor can be used to compensate the system.

Vout

R2

Fb

gm

R1

Vref

Figure 11 - Type II compensator with
transconductance amplifier

power stage

Ve

R3

C2

C1

noise. The following equations show the compensator
pole zero location and constant gain.

R

1

××

m3

R+R

12

1

z

2RC

×π××

≈

p

31

1

2RC

×π××

32

For this type of compensator, FO has to satisfy

FLC<F

<<FO<=1/10~1/5F

ESR

s.

The following uses typical design in figure 18 as
an example for type II compensator design, two 680uF
with 36mΩ electrolytic capacitors are used.

1.Calculate the location of LC double pole F

and ESR zero F

F

LC

.

ESR

=

2LC

×π××

=

1

OUTOUT

1

LC

×π××

2.0kHz

=

40dB/decade

Gain(db)

loop gain

20dB/decade

compensator

Gain

F

F

LC

Z

ESRFO

P

F

F

Figure 12 - Bode plot of Type II compensator

Type II compensator can be realized by simple
RC circuit without feedback as shown in figure 11. R3
and C1 introduce a zero to cancel the double pole
effect. C2 introduces a pole to suppress the switching

F

ESR

6.5kHz

2.Set R

1

=

2ESRC

×π××

=

×π×Ω×

=

equal to10kΩ. Using equation 18.

2

10k0.8V

Ω×

2.5V-0.8V

1

OUT

1

3. Set crossover frequency at 1/10~ 1/5 of the

swithing frequency, here FO=30kHz.

4.Calculate R3 value by the following equation.

V2FL

OSCO

R=

3

VRgR

2V230kHz4.7uH1

=

=10.3k

×π××

×××

inESRm1

×π××

××

10k+4.7k

ΩΩ

×

4.7k

Ω

Ω

1

R+R

12

Ω

Choose R3 =10kΩ.

Rev. 2.0
11/18/05

13

NX2113/2113A

210k0.756.5kHz

p

F

10k300kHz

OUT

REF

2REF

OUT REF

R1.6V1.6V/(1/16W)40

=×=Ω

IID1-D

5. Calculate C1 by setting compensator zero F

Z

at 75% of the LC double pole.

C=

1

=

1

2RF

×π××

3z

1

×π×Ω××

=10.7nF

Choose C1=10nF.

6. Calculate C

by setting compensator pole

2

at

half the swithing frequency.

C=

2

=

1

RF

π××

3s

1

π×Ω×

=106pF

Choose C2=100pF.

Output Voltage Calculation

Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation and picture show the relationship
between

value of R1 value can be set by voltage divider.

1.6V, the result of R1 is 10kΩ.

V ,

R=

1

where R

V and voltage divider..

RV

×

V-V

2 is part of the compensator, and the

...(18)

Choose R2=10kΩ, to set the output voltage at

Vout

R2

Fb

R1

Vref

Voltage divider

Figure 13 - Voltage divider load

In general, the minimum output load impedance
including the resistor divider should be less than 5kΩ to
prevent overcharge the output voltage by leakage cur­rent (e.g. Error Amplifier feedback pin bias current). A
minimum load for 5kΩ less (<1/16w for most of applica­tion) is recommended to put at the output. For example,
in this application,

Vout=1.6V

The power loss is 1/16W less

LOAD

Select minimum load is 1kΩ should be good
enough.

Input Capacitor Selection

Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca­pacitors bypass the high frequency noise, and bulk ca­pacitors supply current to the MOSFETs. Usually 1uF
ceramic capacitor is chosen to decouple the high fre­quency noise. The bulk input capacitors are decided by
voltage rating and RMS current rating. The RMS current
in the input capacitors can be calculated as:

=××

RMSOUT

V

OUT

D

=

V

IN

...(19)

VIN = 12V, VOUT=1.6V, IOUT=10A, using equation
(19), the result of input RMS current is 3.4A.

For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON SP series
16SP270M 16V 270uF with 4.4A is chosen as input
bulk capacitor.

Power MOSFETs Selection

The NX2113 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, I
=75A,R

=9mΩ,Q

DSON

GATE

=23nC.

D

Rev. 2.0
11/18/05

14

NX2113/2113A

gateHGATEHGSLGATELGSS

P(QVQV)F

=×+××

P=I(1D)RK

×−××

SWINOUTSWS

PVITF

=××××

R6.8k

==Ω

There are three factors causing the MOSFET power

loss: conduction loss, switching loss and gate driver loss.

Gate driver loss is the loss generated by discharg­ing the gate capacitor and is dissipated in driver circuits.
It is proportional to frequency and is defined as:

...(20)

where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and V

LGS

is

the low side gate source voltage.

According to equation (20), PGATE =0.14W. This
power dissipation should not exceed maximum power
dissipation of the driver device.

Conduction loss is simply defined as:

P=IDR

HCONOUTDS(ON)

LCONOUTDS(ON)

P=PP

TOTALHCONLCON

2

×××

2

K

+

...(21)

where the RDS(ON) will increases as MOSFET junc­tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K equals to 1.4 at 125oC ac­cording to IRFR3706 datasheet. Using equation (21),
the result of PTOTAL is 0.54W. Conduction loss should
not exceed package rating or overall system thermal
budget.

Switching loss is mainly caused by crossover con­duction at the switching transition. The total switching
loss can be approximated.

1
2

...(22)

where IOUT is output current, TSW is the sum of TR and T
which can be found in mosfet datasheet, and FS is switch­ing frequency. The result of PSW is 3W. Swithing loss
PSW is frequency dependent.

Soft Start, Enable and shut Down

The NX2113 has a digital start up. It is based on
digital counter with 1024 cycles. For NX2113 with 300kHz
operation, the start up time is about 3.5ms. For NX2113A
with 600kHz operation, the start up time is about half of
NX2113, 1.75mS.

Vbus

+

POR

ON

OFF

10k

R1

R2

EN

1.25/1.15

Figure 14 - Enable and Shut down NX2113 by

pulling down EN pin.

The start up of NX2113/2113A can be programmed
through resistor divider at Enable pin. For example, if
the input bus voltage is 12V and we want NX2113 starts
when Vbus is above 8V. We can select

R2=1.24k

(8V1.25V)R

1

1.25V

−×

2

The NX2113 can be turned off by pulling down the
ENable pin by extra signal MOSFET or NPN transistor
such as 2N3904 as shown in the above Figure. When
Enable pin is below 1.15V, the digital soft start is reset
to zero. In addition, all the high side is off and output
voltage is turned off.

A resistor should be added as preload to prevent
leakage current from FB pin charging the output capaci­tors.

Feedback Under Voltage Shut Down

NX2113 relies on the Feedback Under Voltage Lock
Out (FB UVLO ) to provide short circuit protection. Ba-

F

sically, NX2113 has a comparator compares the feed­back voltage with the FB UVLO threshold 0.4V.

During the normal operation, if the output is short,
the feedback voltage will be lower than 0.4V and com­parator will change the state. After certain internal delay,
both high side and low side driver will be turned off. The
output will be latched. The normal operation should be
achieved by removing the short and recycle the VCC.

During the start up, the output voltage is dis­charged to zero by the synchronous FET. FB voltage
starts increase from zero when digital start block

Digital
start
up

Rev. 2.0
11/18/05

15

NX2113/2113A

operates. Before half of the start up time, the Feedback

Under Voltage Lock Out comparator is disabled. After
half of start up time, the Feedback UVLO comparator is
enabled. The FB UVLO threshold is set to be half of
voltage at the positive input of error amplifier. With this
set up, if the output is short before soft start, the
Feedback UVLO comparator can catch it and turn off
the driver. The short circuit operation waveform during
normal operation and during the soft start are shown as
follows.

CH3-FB voltage

0.5V/DIV

CH1-SW voltage

10V/DIV

The Feedback UVLO can provide certain short cir­cuit protection. However, since feedback does not have
accurate information of current, this protection only pro­vides certain level of over current protection. MOSFET
should design such that it can survive with high pulse
current for a short period of time.

The value of the capacitor on enable pin to ground
and the resistor value of voltage divider on enable pin
should be big enough to keep enable pin high during
short. Otherwise, once output shorts, the input bus volt­age drops, the chip is disabled before Feedback UVLO
takes effect, and the system goes into hiccup status.
This phenomena is easy to be found during system
startup, if related resistor and capacitor value is not big
enough.

Figure 15 - Operation waveforms during short con-

dition.

Figure 16 - Feedback UVLO with start up at

short.

CH4-load current

10A/DIV

CH2-output voltage

1V/DIV

CH4-load current

10A/DIV

CH2-Output voltage

1V/DIV

CH4-load current

10A/DIV

Figure 17 -Hiccup with start up at short.

Layout Considerations

The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.

Start to place the power components, make all the
connection in the top layer with wide, copper filled ar­eas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input ca­pacitor directly to the drain of the high-side MOSFET, to

Rev. 2.0
11/18/05

16

reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir­cuit ground (analog ground), to which all signals are ref­erenced.

The goal is to localize the high current path to a
separate loop that does not interfere with the more sen­sitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.

NX2113/2113A

Rev. 2.0
11/18/05

17

TYPICAL APPLICATION

Dual power supply (+5V BIAS,+12V BUS)

NX2113/2113A

Vin

+12V

Vin

+5V

1k

C4
47uF

R5

1k

R6

C1

100pF

R5
10

C5

1uF

C2
10nF

R4

10k

R2

4.7k 1%

7

9

8

C6

1uF

6

Vcc

EN

Comp

Fb

Figure 18 -Application of NX2113 for 5V bias and 12V input bus

Single power supply (+11V to +24V BUS)

5

PVcc

NX2113

PGnd/Gnd

3

10k 1%R1

L2 1uH

1

BST

Hdrv

SW

Ldrv

C5
1uF

D1

C7

2

0.1uF

10

4

M1

L1 4.7uH

M2

Cin

39uF,31mohm

Co
2 x (680uF,36mohm)

Vout
+2.5V,4A

Vin

+11~25V

L2 1uH

TL431

C1

R5

3k

2N3904

R6

12.7k

R7

10k

C2
10nF

R4

10k

R2

4.7k 1%

R8

76.8k

R9

10k

7

9

8

R5
10

C8

1uF

EN

Comp

Fb

Vcc

PGnd

6

3

C6
1uF

PVcc

1

5

BST

Hdrv

SW

NX2113

Ldrv

Gnd

11

R1

10k 1%

D1

C7

2

0.1uF

10

4

M1

M2

C4

47uF

100pF

Figure 19 -Application of NX2113 for high input bus application

C5
1uF

L1 4.7uH

Cin

2 x (47uF,60mohm)

Co

2 x (680uF,36mohm)

Vout
+1.6V,5A

Rev. 2.0
11/18/05

18

TYPICAL APPLICATION

Single Supply 5V Input

NX2113/2113A

Vin

+5V

R4

120k

C2

330pF

C4

10uF

X7R

C1

4.7pF

R2

20k 1%

L2 1uH

R5

10

C8
1uF

7

EN

9

Comp

8

Fb

6

Vcc

PGnd

C6
1uF

5

PVcc

Gnd

3

R1

10k 1%

R3

787

D1

1

BST

2

Hdrv

10

SW

NX2113A

11

C3

820pF

Ldrv

4

C7

0.1uF
M1

L1 3.3uH

M2

C5
1uF

Cin
3 x 22uF
X7R

Co
10 x 22uF

X7R

Vout
+1.2V,4A

Figure 20 - Application of NX2113 A for 5V input and 1.6V output with ceramic output capacitors

Rev. 2.0
11/18/05

19