Page 1
NVTFS4823N
Power MOSFET
30 V, 10.5 mW, 30 A, Single N−Channel
Features
• Small Footprint (3.3x3.3 mm) for Compact Design
• Low R
• Low Capacitance to Minimize Driver Losses
• NV Prefix for Automotive and Other Applications Requiring
AEC−Q101 Qualified Site and Change Controls
• These are Pb−Free Devices
to Minimize Conduction Losses
DS(on)
V
(BR)DSS
30 V
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R
MAX ID MAX
DS(on)
10.5 mW @ 10 V
17.5 mW @ 4.5 V
30 A
MAXIMUM RATINGS (T
Parameter
Drain−to−Source Voltage V
Gate−to−Source Voltage V
Continuous Drain Current R
2, 3, 4)
Power Dissipation
R
Y
J−mb
Continuous Drain Current R
& 4)
Power Dissipation
R
q
JA
Pulsed Drain Current
Operating Junction and Storage Temperature TJ, T
Source Current (Body Diode) I
Single Pulse Drain−to−Source Avalanche
Energy (T
I
L(pk)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
(Notes 1,
Y
J−mb
(Notes 1, 2, 3)
(Notes 1, 3,
q
JA
(Notes 1, 3)
= 25°C, VDD = 24 V, VGS = 10 V,
J
= 24 A, L = 0.1 mH, RG = 25 W)
= 25°C unless otherwise noted)
J
Symbol Value Unit
DSS
I
P
I
P
I
DM
E
T
Steady
State
Steady
State
TA = 25°C, t
Tmb = 25°C
Tmb = 100°C 21
Tmb = 25°C
Tmb = 100°C 11
TA = 25°C
TA = 100°C 9.0
TA = 25°C
TA = 100°C 1.6
= 10 ms
p
GS
D
D
S
AS
D
D
stg
L
30 V
"20 V
30
21
13
3.1
198 A
−55 to
175
19 A
28.8 mJ
260 °C
A
W
A
W
°C
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Mounting Board (top) − Steady
State (Note 2, 3)
Junction−to−Ambient − Steady State (Note 3)
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
Symbol Value Unit
°C/W
R
Y
J−mb
R
q
JA
7.0
47
N−Channel
D (5 − 8)
G (4)
S (1, 2, 3)
MARKING DIAGRAM
1
WDFN8
(m8FL)
CASE 511AB
4823 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
1
S
4823
S
AYWWG
S
G
G
D
D
D
D
ORDERING INFORMATION
Device Package Shipping
NVTFS4823NTAG WDFN8
(Pb−Free)
NVTFS4823NTWG WDFN8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1500/Tape & Reel
5000/Tape & Reel
†
© Semiconductor Components Industries, LLC, 2011
January, 2011 − Rev. 0
1 Publication Order Number:
NVTFS4823N/D
Page 2
NVTFS4823N
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise noted)
J
Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current I
Gate−to−Source Leakage Current I
V
(BR)DSS
DSS
GSS
VGS = 0 V, ID = 250 mA
VGS = 0 V,
V
= 30 V
DS
VDS = 0 V, VGS = "20 V "100 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Drain−to−Source On Resistance R
V
GS(TH)
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V, ID = 15 A 8.1 10.5 mW
VGS = 4.5 V, ID = 15 A 13.5 17.5
Forward Transconductance g
FS
VDS = 1.5 V, ID = 20 A 34 S
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Threshold Gate Charge Q
Gate−to−Source Charge Q
Gate−to−Drain Charge Q
Total Gate Charge Q
C
iss
oss
rss
G(TOT)
G(TH)
GS
GD
G(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V, ID = 15 A
VGS = 10 V, VDS = 15 V, ID = 15 A 12 nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
Fall Time t
t
d(on)
d(off)
r
f
VGS = 4.5 V, VDS = 15 V,
= 15 A, RG = 3.0 W
I
D
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time t
Charge Time t
Discharge Time t
Reverse Recovery Charge Q
V
SD
RR
a
b
RR
VGS = 0 V,
I
= 15 A
S
VGS = 0 V,
/dt = 100 A/ms,
dI
S
I
= 15 A
S
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
30 V
TJ = 25°C 1.0 mA
TJ = 125°C 10
1.5 2.5 V
750
175
100
6.0
0.8
2.4
2.4
12
22
14
4
TJ = 25°C 0.85 1.1
TJ = 125°C 0.72
12
6.0
6.0
5.0 nC
pF
nC
ns
V
ns
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2
Page 3
NVTFS4823N
TYPICAL CHARACTERISTICS
60
10 V
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
012345
5.5 V
VGS = 4.5 V
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°C
4.1 V
3.8 V
3.5 V
3.2 V
2.9 V
Figure 1. On−Region Characteristics
0.020
0.019
0.018
0.017
0.016
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
, DRAIN−TO−SOURCE RESISTANCE (W)
0.006
345678910
DS(on)
R
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 15 A
T
= 25°C
J
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
60
VDS ≥ 10 V
50
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
12345
TJ = 125°C
TJ = 25°C
TJ = −55°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
0.025
TJ = 25°C
0.020
VGS = 4.5 V
0.015
0.010
0.005
, DRAIN−TO−SOURCE RESISTANCE (W)
0
5 1015202530354045505560
DS(on)
R
ID, DRAIN CURRENT (A)
VGS = 10 V
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
ID = 15 A
1.6
V
= 10 V
GS
1.4
1.2
1.0
, DRAIN−TO−SOURCE
0.8
DS(on)
R
RESISTANCE (NORMALIZED)
0.6
50 25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
10000
1000
100
, LEAKAGE (nA)
DSS
I
10
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3
VGS = 0 V
TJ = 150°C
TJ = 125°C
5 1015202530
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
Page 4
NVTFS4823N
TYPICAL CHARACTERISTICS
1200
VGS = 0 V
1000
800
C
iss
TJ = 25°C
600
400
C
C, CAPACITANCE (pF)
oss
200
C
rss
0
0 5 10 15 20 25 30
DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
VDD = 15 V
I
= 10 A
D
= 10 V
V
GS
100
t
t, TIME (ns)
10
1.0
d(off)
t
d(on)
t
f
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
10
Q
T
8
6
(V)
4
Q
gs
2
, GATE−TO−SOURCE VOLTAGE
GS
V
0
024681012
Q
gd
VDS = 15 V
I
= 15 A
D
= 25°C
T
J
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage vs. Total
Charge
40
VGS = 0 V
TJ = 25°C
30
t
r
20
10
, SOURCE CURRENT (A)
S
I
0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
1000
VGS = 10 V
Single Pulse
TC = 25°C
100
10
, DRAIN CURRENT (A)
1
D
R
I
DS(on)
Limit
Thermal Limit
Package Limit
0.1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
100 ms
10 ms
1 ms
dc
, SINGLE PULSE DRAIN−TO−
AS
E
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4
30
ID = 24 A
25
20
15
10
5
SOURCE AVALANCHE ENERGY (mJ)
0
25 50 75 100 125 150 200
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
Page 5
100
10
NVTFS4823N
TYPICAL CHARACTERISTICS
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
THERMAL RESISTANCE
(°C/W) EFFECTIVE TRANSIENT
JA(t)
q
R
0.01
Single Pulse
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
Figure 13. Thermal Response
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5
Page 6
NVTFS4823N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB−01
ISSUE B
0.05
0.10 C
0.10 C
8X
A0.10 BC
c
G
D
D1
78
1234
TOP VIEW
SIDE VIEW
b
L
14
E2
8
D2
BOTTOM VIEW
56
5
2X
E1
e/2
K
C
0.20
A
B
E
A
DETAIL A
M
L1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
2X
0.20 C
4X
q
c
6X
e
A1
C
SEATING
PLANE
DETAIL A
PROTRUSIONS OR GATE BURRS.
DIM MIN NOM
MILLIMETERS
A 0.70 0.75
A1 0.00 −−−
b 0.23 0.30
c 0.15 0.20
D
D1 2.95 3.05
D2 1.98 2.11
E
E1 2.95 3.05
E2 1.47 1.60
e 0.65 BSC
G 0.30 0.41
K 0.64 −−−
L 0.30 0.43
L1 0.06 0.13
M 1.40 1.50
q 0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
−−−
0.56
0.20
1.60
12
_
INCHES
MIN NOM
0.028 0.030
0.000 −−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.026 BSC
0.012 0.016
0.025 −−−
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
−−−
0.022
0.008
0.063
12
_
SOLDERING FOOTPRINT*
0.75
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
4X
0.66
3.60
2.30
0.47
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NVTFS4823N/D
6
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