Datasheet nvmfs4841n-d Datasheet

Download

Page 1

NVMFS4841N

Power MOSFET

30V, 7 mW, 89A, Single N−Channel SO8FL

Features

• Small Footprint (5x6 mm) for Compact Design

• Low R

• Low Q

• AEC−Q101 Qualified

• These are Pb−Free Devices*

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

2, 3, 4)

Power Dissipation R

J−mb

Continuous Drain Current R

3, 4)

Power Dissipation

(Notes 1, 3)

Pulsed Drain Current

Current limited by package (Note 4)

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V,

= 19 A, L = 1.0 mH, RG = 25 W)

L(pk)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)

Junction−to−Mounting Board (top) − Steady

State (Note 2, 3)

Junction−to−Ambient − Steady State (Note 3)

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted.

2. Psi (Y) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface.

3. Surface−mounted on FR4 board using a 650 mm

4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle.

to Minimize Conduction Losses

DS(on)

and Capacitance to Minimize Driver Losses

= 25°C unless otherwise noted)

Parameter

(Notes 1,

J−mb

(Notes 1, 2, 3)

(Notes 1 &

Parameter

Steady

State

Steady

State

TA = 25°C, t

Tmb = 25°C

Tmb = 100°C 63

Tmb = 25°C

Tmb = 100°C 56

TA = 25°C

TA = 100°C 11

TA = 25°C

TA = 100°C 1.8

= 10 ms

TA = 25°C I

Symbol Value Unit

DmaxPkg

Symbol Value Unit

, 2 oz. Cu pad.

DSS

J−mb

stg

30 V

"20 V

112

3.7

336 A

80 A

−55 to 175

51 A

180 mJ

260 °C

1.3

°C

°C/W

http://onsemi.com

(BR)DSS

30 V

G (4)

MAX ID MAX

DS(ON)

7.0 mW @ 10 V

11.4 mW @ 4.5 V

D (5,6)

S (1,2,3)

N−CHANNEL MOSFET

89 A

MARKING DIAGRAM

SO−8 FLAT LEAD

CASE 488AA

STYLE 1

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

S S S

V4841

AYWWG

ORDERING INFORMATION

Device Package Shipping

NVMFS4841NT1G SO−8FL

NVMFS4841NT3G SO−8FL

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*For additional information on our Pb−Free strategy and

soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

(Pb−Free)

Tape & Reel

†

1500 /

5000 /

December, 2010 − Rev. 0

1 Publication Order Number:

NVMFS4841N/D

Page 2

NVMFS4841N

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V,

= 30 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V ID = 30 A 4.7 7.0

VGS = 4.5 V ID = 30 A 9.2 11.4

Forward Transconductance g

VDS = 15 V, ID = 15 A 16 S

CHARGES AND CAPACITANCES

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1 MHz, VDS = 12 V

VGS = 4.5 V, VDS = 15 V; ID = 30 A

VGS = 10 V, VDS = 15 V,

= 30 A

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

VGS = 4.5 V, VDS = 15 V, ID = 15 A,

= 3.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V,

= 30 A

VGS = 0 V, dIS/dt = 100 A/ms,

= 30 A

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

30 V

TJ = 25 °C 1

TJ = 125°C 10

1.5 2.5 V

5.6 mV/°C

1436

348

177

11.5 17

2.0

5.0

5.1

25.4

13.5

66.5

15.5

7.5

TJ = 25°C 0.9 1.2

TJ = 125°C 0.8

20.5

11.6

8.9

10.7 nC

mV/°C

http://onsemi.com

Page 3

NVMFS4841N

TYPICAL PERFORMANCE CURVES

130 120 110 100

90 80 70 60 50 40 30

, DRAIN CURRENT (AMPS)

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.018

0.017

0.016

0.015

0.014

0.013

0.012

0.011

0.010

0.009

0.008

0.007

, DRAIN−TO−SOURCE RESISTANCE (W)

0.006

0.005

DS(on)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance vs. Gate−to−Source

130

5.5 V to 10 V

TJ = 25°C

VGS = 5 V

120

110

100

VDS = 10 V

4.5 V

80 70 60

4 V

3.8 V

3.6 V

3.4 V

50 40 30

, DRAIN CURRENT (AMPS)

TJ = 125°C

TJ = 25°C

, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

678

0.017 ID = 30 A T

= 25°C

0.014

TJ = 25°C

VGS = 4.5 V

0.011

0.008

VGS = 10 V

0.005

, DRAIN−TO−SOURCE RESISTANCE (W)

0.002

620

789

10 11

DS(on)

40 5545 5035

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and

Voltage

Gate Voltage

1.9 ID = 30 A

1.8 V

= 10 V

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

(NORMALIZED)

0.9

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.7

0.6

DS(on)

−50 250−25 50 10075

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

150

125

175

http://onsemi.com

10000

1000

100

, LEAKAGE (nA)

DSS

0.1

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 25°C

1510 305

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

Page 4

NVMFS4841N

TYPICAL PERFORMANCE CURVES

2200

2000

1800

1600

1400

iss

TJ = 25°C

iss

1200

1000

800

600

C, CAPACITANCE (pF)

400

200

rss

oss

rss

10 0 10 15 30

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

VDD = 15 V I

= 15 A

= 10 V

100

12 11

9 8

, GATE−TO−SOURCE VOLTAGE (VOLTS)

2 1

426

, TOTAL GATE CHARGE (nC)

1614 2612

VDD = 15 V V

= 30 A

= 25°C

18 20 22

Figure 8. Gate−To−Source and Drain−To−Source

Voltage vs. Total Charge

VGS = 0 V

TJ = 25°C

= 10 V

t, TIME (ns)

d(off)

d(on)

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

VGS = 20 V

, DRAIN CURRENT (AMPS)

0.1 1 100

SINGLE PULSE TC = 25°C

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

, SOURCE CURRENT (AMPS)

0.5 1.0

0.6 0.7

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

0.8 0.9

Figure 10. Diode Forward Voltage vs. Current

180

160

140

120

100

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

50 75

, STARTING JUNCTION TEMPERATURE (°C)

100 125

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

ID = 19 A

150

175

http://onsemi.com

Page 5

100

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

0.01

0.1

NVMFS4841N

TYPICAL PERFORMANCE CURVES

THERMAL RESISTANCE

(°C/W) EFFECTIVE TRANSIENT

J(t)

SINGLE PULSE

0.01

0.000001 0.00001 0.0001 0.001 0.01 0.1 1000

t, PULSE TIME (s)

1 10 100

Figure 13. FET Thermal Response

http://onsemi.com

Page 6

0.05

0.10 C

1234

TOP VIEW

SIDE VIEW

A0.10 BC

BOTTOM VIEW

2 X

e/2

0.20

DETAIL A

NVMFS4841N

PACKAGE DIMENSIONS

DFN5 5x6, 1.27P

(SO−8FL)

CASE 488AA−01

ISSUE D

2 X

0.20 C

DETAIL A

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

3 X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

DIM MIN NOM

4 X

A1 0.00 −−−

D1 4.50 4.90

D2 3.50 −−−

E1 5.50 5.80 E2 3.45 −−−

SEATING

PLANE

L1 0.05 0.17

MILLIMETERS

A 0.90 1.00

b 0.33 0.41

c 0.23 0.28

D 5.15 BSC

E 6.15 BSC

e 1.27 BSC G 0.51 0.61 K 0.51 −−− L 0.51 0.61

M 3.00 3.40

q 0 −−−

MAX

1.10

0.05

0.51

0.33

5.10

4.22

6.10

4.30

0.71

−−−

0.71

0.20

3.80 12

SOLDERING FOOTPRINT*

3X 4X

1.330

3.200

0.965

0.495

1.270

4.560

1.530

0.750

0.905

0.475

1.000

4.530

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local Sales Representative

NVMFS4841N/D