Datasheet nus5530mn Datasheet

Page 1

NUS5530MN

Integrated Power MOSFET with PNP Low V

CE(sat)

Switching Transistor

This integrated device represents a new level of safety and board−space reduction by combining the 20 V P−Channel FET with a PNP Silicon Low V product provides higher efficiency and accuracy for battery powered portable electronics.

Features

• Low R

(MOSFET) and Low V

DS(on)

• Higher Efficiency Extending Battery Life

• Logic Level Gate Drive (MOSFET)

• Performance DFN Package

• This is a Pb−Free Device

Applications

• Power Management in Portable and Battery−Powered Products; i.e.,

Cellular and Cordless Telephones and PCMCIA Cards

MAXIMUM RATINGS FOR P−CHANNEL FET

(TA = 25°C unless otherwise noted)

Rating Symbol 5 sec

Drain−Source Voltage V

Gate−Source Voltage V

Continuous Drain Current

(TJ = 150°C) (Note 1) TA = 25°C TA = 85°C

Pulsed Drain Current I

Continuous Source Current

(Note 1)

Maximum Power Dissipation

(Note 1) TA = 25°C TA = 85°C

Operating Junction and Storage

Temperature Range

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).

switching transistor. This newly integrated

CE(sat)

(Transistor)

CE(sat)

Steady

State

−20 V

"12 V

−5.3

−3.8

−5.3 −3.9 A

2.5

1.3

−55 to +150 °C

−3.9

−2.8

"20 A

TJ, T

stg

Unit

1.3

0.7

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(Top View)

DFN8

CASE 506AL

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

MARKING DIAGRAM

AYW W G

PIN ASSIGNMENT

Emitter

Base

N/C

Gate

Collector

Drain

(Bottom View)

ORDERING INFORMATION

Device Package Shipping

NUS5530MNR2G DFN8

(Pb−Free)

3000/Tape & Reel

5530

N/C

Collector

Source

Drain

†

May, 2006 − Rev. 0

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1 Publication Order Number:

NUS5530MN/D

Page 2

NUS5530MN

MAXIMUM RATINGS FOR PNP TRANSISTORS (T

Rating

Collector-Emitter Voltage V

Collector-Base Voltage V

Emitter-Base Voltage V

Collector Current − Continuous I

Collector Current − Peak I

= 25°C)

Symbol Max Unit

CEO

CBO

EBO

−35 Vdc

−55 Vdc

−5.0 Vdc

−2.0 Adc

−7.0 A

Electrostatic Discharge ESD HBM Class 3

MM Class C

THERMAL CHARACTERISTICS FOR P−CHANNEL FET

Characteristic Symbol Typ Max Unit

Maximum Junction−to−Ambient (Note 4)

t v 5 sec Steady State

Maximum Junction−to−Foot (Drain)

Steady State

40 80

15 20 °C/W

THERMAL CHARACTERISTICS FOR PNP TRANSISTORS

Characteristic Symbol Max Unit

Total Device Dissipation

TA = 25°C

Derate above 25°C

Thermal Resistance, Junction−to−Ambient

Total Device Dissipation

TA = 25°C

Derate above 25°C

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Lead #1

Total Device Dissipation (Single Pulse < 10 sec) P

Junction and Storage Temperature Range TJ, T

1. FR− 4 @ 100 mm2, 1 oz copper traces.

2. FR− 4 @ 500 mm2, 1 oz copper traces.

3. Thermal response.

PD (Note 1) 635

(Note 1)

PD (Note 2) 1.35

(Note 2)

Dsingle

(Notes 2 & 3)

stg

2.75 W

−55 to +150 °C

5.1

200 °C/W

90 °C/W

15 °C/W

°C/W

mW/°C

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Page 3

NUS5530MN

ELECTRICAL CHARACTERISTICS FOR P−CHANNEL FET (T

= 25°C unless otherwise noted)

Characteristic Symbol Test Condition Min Typ Max Unit

Static

Gate Threshold Voltage V

Gate−Body Leakage I

Zero Gate Voltage Drain Current I

GS(th)

GSS

DSS

VDS = VGS, ID = −250 mA

VDS = 0 V, VGS = "12 V "100 nA

VDS = −16 V, VGS = 0 V −1.0 mA

−0.6 −1.2 V

VDS = −16 V, VGS = 0 V,

TJ = 85°C

On−State Drain Current (Note 5) I

Drain−Source On−State Resistance (Note 5) r

D(on)

DS(on)

VDS v −5.0 V, VGS = −4.5 V −20 A

VGS = −3.6 V, ID = −1.0 A − 0.050 0.06 W

VGS = −2.5 V, ID = −1.0 A 0.070 0.083

Forward Transconductance (Note 5) g

Diode Forward Voltage (Note 5) V

VDS = −10 V, ID = −3.9 A 12 Mhos

IS = −2.1 A, VGS = 0 V −0.8 −1.2 V

Dynamic (Note 6)

Total Gate Charge Q

Gate−Source Charge Q

Gate−Drain Charge Q

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

Source−Drain Reverse Recovery Time t

iss

oss

rss

d(on)

d(off)

VDS = −10 V, VGS = −4.5 V,

ID = −3.9 A

VDS = −5.0 Vdc, VGS = 0 Vdc,

f = 1.0 MHz

VDD = −10 V, RL = 10 W

ID ^ −1.0 A, V

RG = 6 W

GEN

= −4.5 V,

IF = −1.1 A, di/dt = 100 A/ms

4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).

5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

6. Guaranteed by design, not subject to production testing.

−5.0

9.7 22

1.2

3.6

710

400

140

14 30

22 55

42 100

35 70

30 60

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Page 4

NUS5530MN

ELECTRICAL CHARACTERISTICS FOR PNP TRANSISTORS (T

Characteristic

= 25°C unless otherwise noted)

Symbol Min Typical Max Unit

OFF CHARACTERISTICS

Collector −Emitter Breakdown Voltage (IC = −10 mAdc, IB = 0) V

Collector −Base Breakdown Voltage (IC = −0.1 mAdc, IE = 0) V

Emitter −Base Breakdown Voltage (IE = −0.1 mAdc, IC = 0) V

Collector Cutoff Current (VCB = −35 Vdc, IE = 0) I

Collector−Emitter Cutoff Current (V

= −35 Vdc) I

CES

Emitter Cutoff Current (VEB = −6.0 Vdc) I

(BR)CEO

(BR)CBO

(BR)EBO

CBO

CES

EBO

−35 −45 − Vdc

−55 −65 − Vdc

−5.0 −7.0 − Vdc

− −0.03 −0.1

− −0.01 −0.1

ON CHARACTERISTICS

DC Current Gain (Note 7) (IC = −1.0 A, VCE = −2.0 V) (IC = −1.5 A, VCE = −2.0 V) (I

= −2.0 A, VCE = −2.0 V)

Collector −Emitter Saturation Voltage (Note 7) (IC = −0.1 A, IB = −0.010 A) (IC = −1.0 A, IB = −0.010 A) (IC = −2.0 A, IB = −0.02 A)

Base −Emitter Saturation Voltage (Note 7) (IC = −1.0 A, IB = −0.01 A)

Base −Emitter Turn−on Voltage (Note 7) (IC = −2.0 A, VCE = −3.0 V)

Cutoff Frequency (IC = −100 mA, VCE = −5.0 V, f = 100 MHz) f

CE(sat)

BE(sat)

BE(on)

100 100 100

−

200 200 200

−

400

−

−0.10

−0.15

−0.30

− −0.68 −0.85

− −0.81 −0.875

100 − − MHz

Input Capacitance (VEB = −0.5 V, f = 1.0 MHz) Cibo − 600 650 pF

Output Capacitance (VCB = −3.0 V, f = 1.0 MHz) Cobo − 85 100 pF

Turn−on Time (VCC = −10 V, IB1 = −100 mA, IC = −1 A, RL = 3 W)

Turn−off Time (VCC = −10 V, IB1 = IB2 = −100 mA, IC = 1 A, RL = 3 W)

off

− 35 − nS

− 225 − nS

7. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%

mAdc

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Page 5

NUS5530MN

TYPICAL ELECTRICAL CHARACTERISTICS FOR P−CHANNEL FET

−4.5 V

−4 V

DRAIN CURRENT (AMPS)

−I

0.5

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

0.2

0.15

0.1

−3.5 V−5 V

−3 V

VGS = −1.5 V

TJ = 25°C

−2.5 V

−2 V

2.5

31.51

DRAIN CURRENT (AMPS)

−I

0.5

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = −55°C

25°C

1.512

125°C

2.5 3

Figure 2. Transfer Characteristics

0.2

ID = −3.9 A TJ = 25°C

0.15

0.1

TJ = 25°C

VGS = 2.5 V

0.05

DRAIN−TO−SOURCE RESISTANCE (W)

DS(on),

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance versus

Gate−to−Source Voltage

1.6 ID = −3.9 A VGS = −4.5 V

1.4

1.2

DRAIN−TO−SOURCE

0.8

DS(on),

RESISTANCE (NORMALIZED)

0.6

−50 0−25 25

Figure 5. On−Resistance Variation with

0.05

DRAIN−TO−SOURCE RESISTANCE (W)

218201410

DS(on),

Figure 4. On−Resistance versus Drain Current

50 125100

75 150

TJ, JUNCTION TEMPERATURE (°C)

Temperature

VGS = 3.6 V

VGS = 4.5 V

−ID, DRAIN CURRENT (AMPS)

and Gate Voltage

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Page 6

NUS5530MN

TYPICAL ELECTRICAL CHARACTERISTICS FOR P−CHANNEL FET

1500

1200

900

600

C, CAPACITANCE (pF)

300

TJ = 25°C VGS = 0

iss

oss

ID = −3.9 A

GATE−TO−SOURCE VOLTAGE (VOLTS)

012345678910

GS,

−V

QG, TOTAL GATE CHARGE (nC)

Figure 7. Gate−to−Source and

rss

8124016

−VDS, DRAIN−TO−SOURCE VOLTAGE ()

Figure 6. Capacitance Variation

= 25°C

QGD/QGS = 3.0

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS,

−V

Drain−to−Source Voltage versus Total Charge

VGS = 0 V TJ = 25°C

, SOURCE CURRENT (AMPS)

−I

0.30.1 0.5 0.7 0.9

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 8. Diode Forward Voltage versus

Current

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

THERMAL IMPEDANCE

0.01

NORMALIZED EFFECTIVE TRANSIENT

0.0001 1

Single Pulse

0.001

SQUARE WAVE PULSE DURATION (sec)

Figure 9. Normalized Thermal Transient Impedance, Junction−to−Ambient

DUTY CYCLE, D = t1/t

PER UNIT BASE = R TJM − TA = PDMZ SURFACE MOUNTED

100.10.01

= 80°C/W

(t)

100 1000

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Page 7

, COLLECTOR EMITTER SATURATION

VOLTAGE (VOLTS)

0.1

0.01

NUS5530MN

TYPICAL ELECTRICAL CHARACTERISTICS FOR PNP TRANSISTOR

0.25

IC/IB = 50

, COLLECTOR EMITTER SATURATION

0.20

0.15

0.10

VOLTAGE (VOLTS)

0.05

IC/IB = 100

100°C

25°C

−55°C

CE(sat)

0.001

0.01 0.1 1.0 0.01

IC, COLLECTOR CURRENT (A)

Figure 10. Collector Emitter Saturation Voltage

versus Collector Current

500

450

400

350

300

250

200

, DC CURRENT GAIN

150

100

0.001 0.01 0.1 1 10

125°C (5 V)

125°C (2 V)

25°C (5 V)

25°C (2 V)

−55°C (5 V)

−55°C (2 V)

IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)

Figure 12. DC Current Gain versus

Collector Current

CE(sat)

VOLTAGE (VOLTS)

, BASE EMITTER SATURATION

BE(sat)

IC, COLLECTOR CURRENT (A)

0.1 1.00.001

Figure 11. Collector Emitter Saturation Voltage

versus Collector Current

1.0

0.8

0.6

0.4

0.2

−55°C

25°C

100°C

0.010.001

0.1 1.0

Figure 13. Base Emitter Saturation Voltage

versus Collector Current

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

, BASE EMITTER TURN−ON VOLTAGE (VOLTS)V

0.3

BE(on)

100°C

25°C

−55°C

0.10.001

IC, COLLECTOR CURRENT (A)

1.0

Figure 14. Base Emitter Turn−On Voltage

versus Collector Current

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750

700

650

600

550

500

450

, INPUT CAPACITANCE (pF)

400

ibo

350

300

0.5 5.01.0

1.50.01

VEB, EMITTER BASE VOLTAGE (V)

3.02.0 2.5 3.5 4.0 4.5

Figure 15. Input Capacitance

Page 8

NUS5530MN

TYPICAL ELECTRICAL CHARACTERISTICS FOR PNP TRANSISTOR

225

200

175

150

125

100

, OUTPUT CAPACITANCE (pF)

obo

1000

100

155.0 10

VCB, COLLECTOR BASE VOLTAGE (V)

Figure 16. Output Capacitance

D = 0.50

D = 0.20

D = 0.05

D = 0.10

3020 25 35

1 s

1.00

, (A)

0.10

0.01

0.10 1 10 100

Thermal Limits

VCE, (Vdc)

1 ms

Figure 17. Safe Operating Area

P(pk)

10 ms

100 ms

0.1

, TRANSIENT THERMAL RESISTANCE

(t)

0.01

D = 0.01

Single Pulse

t1, TIME (Sec)

Figure 18. Normalized Thermal Response

Duty Cycle = D = t1/t

qJC = 174°C/W

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Page 9

REFERENCE

2 X

PIN ONE

0.15 C

2 X

0.10 C

0.15 C

TOP VIEW

NUS5530MN

PACKAGE DIMENSIONS

DFN8

CASE 506AL−01

ISSUE A

(A3)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND

0.30mm.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN NOM MAX

A 0.80 0.90 1.00 A1 0.00 0.03 0.05 A3 0.20 REF

b 0.35 0.40 0.45

D 3.30 BSC D2 0.95 1.05 1.15

E 3.30 BSC E2 1.80 1.90 2.00

e 0.80 BSC

K 0.21 −−− −−−

L 0.30 0.40 0.50

8 X

0.08 C

L8 X

SIDE VIEW

SEATING PLANE

2.95

2 X

K8 X

8 X

0.10 B

BOTTOM VIEW

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

0.05ACC

NOTE 3

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

3.60

1.20

1.95

0.45

0.60

0.55

0.80

PITCH

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NUS5530M N/D