• Optimized Gate Charge to Minimize Switching Losses
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• Low−Side DC−DC Converters
• Power Load Switch
• Notebook Battery Management
• Motor Control
MAXIMUM RATINGS (T
Drain−to−Source VoltageV
Gate−to−Source VoltageV
Continuous Drain
Current R
Power Dissipation R
(Note 1)
Continuous Drain
Current R
(Note 1)
Power Dissipation
≤ 10 s (Note 1)
R
q
JA
Continuous Drain
Current R
Power Dissipation
(Note 2)
R
q
JA
Continuous Drain
Current R
Power Dissipation
(Note 1)
R
q
JC
Pulsed Drain Current
Operating Junction and Storage TemperatureTJ,
Source Current (Body Diode)I
Drain to Source dV/dtdV/dt6.0V/ns
Single Pulse Drain−to−Source Avalanche Energy
(T
= 25°C, VDD = 50 V, VGS = 10 V,
J
= 37 Apk, L = 0.1 mH, RG = 25 W)
I
L
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
to Minimize Conduction Losses
DS(on)
= 25°C unless otherwise stated)
J
Parameter
(Note 1)
q
JA
q
JA
≤ 10 s
q
JA
Steady
State
(Note 2)
q
JA
(Note 1)
q
JC
TA = 25°C, tp = 10 ms
SymbolValueUnit
DSS
GS
TA = 25°C
TA = 85°C12
TA = 25°CP
TA = 25°C
TA = 85°C18
TA = 25°CP
TA = 25°C
TA = 85°C8.0
TA = 25°CP
TC = 25°C
TC = 85°C54
TC = 25°CP
I
D
D
I
D
D
I
D
D
I
D
D
I
DM
T
stg
S
E
AS
T
L
30V
±20V
17
2.24W
25
4.6W
11
0.86W
75
43.1W
230A
−55 to
+150
48A
68.5mJ
260°C
A
A
A
A
°C
http://onsemi.com
V
(BR)DSS
30 V
R
DS(on)
4.5 mW @ 10 V
7.0 mW @ 4.5 V
N−Channel MOSFET
D (5−8)
G (4)
MAXID MAX
75 A
S (1,2,3)
MARKING DIAGRAM
1
WDFN8
(m8FL)
CASE 511AB
4937= Specific Device Code
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
1
S
4937
S
AYWWG
S
G
G
D
D
D
D
ORDERING INFORMATION
DevicePackageShipping
NTTFS4937NTAGWDFN8
(Pb−Free)
NTTFS4937NTWGWDFN8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
6. Switching characteristics are independent of operating junction temperatures.
9.8
19.8
28.8
4.0
TJ = 25°C0.851.1
TJ = 125°C0.75
38.5
20.2
18.2
33nC
0.38
0.054
1.3
1.12.0
ns
V
ns
nH
W
http://onsemi.com
3
Page 4
NTTFS4937N
TYPICAL CHARACTERISTICS
100
10 V
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
D
20
I
10
0
4.5 V
VDS, DRAIN−TO−SOURCE VOLTAGE (V)VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 4.0 V
2.4 V
TJ = 25°C
43.52.51.50.54.5
Figure 1. On−Region CharacteristicsFigure 2. Transfer Characteristics
0.060
ID = 20 A
T
GS
= 25°C
J
0.050
0.040
0.030
0.020
0.010
, DRAIN−TO−SOURCE RESISTANCE (W)
0.000
DS(on)
2345678910
R
VGS (V)ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. V
2.0
1.9
ID = 20 A
1.8
V
= 10 V
GS
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
, DRAIN−TO−SOURCE
0.8
0.7
DS(on)
R
0.6
RESISTANCE (NORMALIZED)
0.5
0.4
−50−250255075100125150
TJ, JUNCTION TEMPERATURE (°C)VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
2.6 V
90
80
70
60
50
40
30
, DRAIN CURRENT (A)
20
D
I
10
53210
0
0.0070
0.0065
0.0060
0.0055
0.0050
0.0045
0.0040
0.0035
, DRAIN−TO−SOURCE RESISTANCE (W)
0.0030
10150160
DS(on)
R
Figure 4. On−Resistance vs. Drain Current and
10,000
1000
, LEAKAGE (nA)
100
DSS
I
10
VDS ≥ 10 V
TJ = 25°C
TJ = 125°C
TJ = −55°C
2.5
TJ = 25°C
VGS = 4.5 V
VGS = 10 V
20 30 40 50 60 70 80 90 100110120130140
Gate Voltage
VGS = 0 V
TJ = 150°C
TJ = 125°C
TJ = 85°C
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
4.03.53.02.01.51.0
30252015105
http://onsemi.com
4
Page 5
NTTFS4937N
TYPICAL CHARACTERISTICS
2800
C
2600
iss
2400
2200
2000
1800
1600
1400
1200
C
oss
VGS = 0 V
T
= 25°C
J
1000
800
C, CAPACITANCE (pF)
600
400
200
0
C
rss
2520151050
VDS, DRAIN−TO−SOURCE VOLTAGE (V)Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance VariationFigure 8. Gate−to−Source and
1000
VDD = 15 V
I
= 15 A
D
= 10 V
V
GS
100
t, TIME (ns)
10
1
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
100
10
VGS = 20 V
1
Single Pulse
, DRAIN CURRENT (A)
D
0.1
I
R
DS(on)
TC = 25°C
Limit
Thermal Limit
Package Limit
0.01
0.01110100
0.1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
t
d(off)
t
f
t
r
t
d(on)
10 ms
100 ms
1 ms
10 ms
dc
11
10
9
8
7
6
5
4
3
2
, GATE−TO−SOURCE VOLTAGE (V)
1
GS
0
V
30
0 2 4 6 8 101214161820222426283032
30
25
20
15
10
, SOURCE CURRENT (A)
S
I
5
0
100101
70
60
50
40
30
20
, SINGLE PULSE DRAIN−TO−
10
AS
E
SOURCE AVALANCHE ENERGY (mJ)
0
QT
TJ = 25°C
Qgd
Qgs
VDD = 15 V
V
= 10 V
GS
= 20 A
I
D
Drain−to−Source Voltage vs. Total Charge
VGS = 0 V
TJ = 125°C
TJ = 25°C
0.90.80.71.00.60.50.4
V
, SOURCE−TO−DRAIN VOLTAGE (V)
SD
Figure 10. Diode Forward Voltage vs. Current
ID = 37 A
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
150125100755025
http://onsemi.com
5
Page 6
100
10
1
R(t) (°C/W)
0.1
0.01
Duty Cycle = 50%
20%
10%
5%
2%
1%
Single Pulse
NTTFS4937N
TYPICAL CHARACTERISTICS
0.010.0010.00010.000010.000001
PULSE TIME (sec)
Figure 13. Thermal Response
0.11101001000
http://onsemi.com
6
Page 7
NTTFS4937N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB−01
ISSUE B
0.05
0.10 C
0.10 C
8X
A0.10BC
c
G
D
D1
78
1234
TOP VIEW
SIDE VIEW
b
L
14
E2
8
D2
BOTTOM VIEW
56
5
2X
E1
e/2
C
0.20
A
B
E
A
DETAIL A
K
M
L1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
2X
0.20 C
4X
q
c
6X
e
A1
C
SEATING
PLANE
DETAIL A
PROTRUSIONS OR GATE BURRS.
DIM MINNOM
A10.00−−−
D12.953.05
D21.982.11
E12.953.05
E21.471.60
L10.060.13
MILLIMETERS
A0.700.75
b0.230.30
c0.150.20
D
E
e0.65 BSC
G0.300.41
K0.64−−−
L0.300.43
M1.401.50
q0 −−−
3.30 BSC
3.30 BSC
_
MAX
0.80
0.05
0.40
0.25
3.15
2.24
3.15
1.73
0.51
−−−
0.56
0.20
1.60
12
_
INCHES
MINNOM
0.028 0.030
0.000−−−
0.009 0.012
0.006 0.008
0.130 BSC
0.116 0.120
0.078 0.083
0.130 BSC
0.116 0.120
0.058 0.063
0.026 BSC
0.012 0.016
0.025−−−
0.012 0.017
0.002 0.005
0.055 0.059
0 −−−
_
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.020
−−−
0.022
0.008
0.063
12
_
SOLDERING FOOTPRINT*
0.75
PACKAGE
OUTLINE
0.57
8X
0.650.42
PITCH
4X
0.66
3.60
2.30
0.47
2.37
3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTTFS4937N/D
7
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