Page 1
NTP30N20
Preferred Device
Power MOSFET
30 Amps, 200 Volts
N−Channel Enhancement−Mode TO−220
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• I
DSS
and R
Specified at Elevated Temperature
DS(on)
• Pb−Free Package is Available*
Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (T
Drain−to−Source Voltage V
Drain−to−Source Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (t
Drain Current
− Continuous @ T
− Continuous @ TA 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Drain−to−Source Avalanche Energy −
Starting T
(VDD = 100 Vdc, VGS = 10 Vdc,
(pk) = 20 A, L = 3.0 mH, RG = 25 W)
I
L
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
= 25°C
J
= 25°C unless otherwise noted)
C
Rating
v10 ms)
p
25°C
A
Symbol Value Unit
stg
200 Vdc
200 Vdc
Vdc
"30
"40
Adc
30
22
90
214
1.43WW/°C
−55 to
+175
450
°C/W
0.7
62.5
260 °C
°C
mJ
V
V
R
R
DSS
DGR
V
GSM
I
I
I
DM
P
E
T
q
q
GS
D
D
D
AS
JC
JA
L
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30 AMPERES
200 VOLTS
68 mW @ V
G
1
2
3
TO−220
CASE 221A
STYLE 5
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device Package Shipping
NTP30N20 TO−220 50 Units / Rail
NTP30N20G TO−220
Preferred devices are recommended choices for future use
and best overall value.
= 10 V (Typ)
GS
N−Channel
D
S
MARKING DIAGRAM &
PIN ASSIGNMENT
D
30N20G
AYWW
1
DS
G
(Pb−Free)
50 Units / Rail
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 5
1 Publication Order Number:
NTP30N20/D
Page 2
NTP30N20
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
C
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
= 0 Vdc, ID = 250 mAdc)
(V
GS
Temperature Coefficient (Positive)
Zero Gate Voltage Collector Current
(V
= 0 Vdc, VDS = 200 Vdc, TJ = 25°C)
GS
= 0 Vdc, VDS = 200 Vdc, TJ = 175°C)
(V
GS
Gate−Body Leakage Current (VGS = ± 30 Vdc, VDS = 0) I
ON CHARACTERISTICS
Gate Threshold Voltage
= V
(V
DS
ID = 250 mAdc)
GS,
Temperature Coefficient (Negative)
Static Drain−to−Source On−State Resistance
(V
= 10 Vdc, ID = 15 Adc)
GS
= 10 Vdc, ID = 10 Adc)
(V
GS
(VGS = 10 Vdc, ID = 15 Adc, TJ = 175°C)
Drain−to−Source On−Voltage
(V
= 10 Vdc, ID = 30 Adc)
GS
Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
(VDS = 160 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) C
SWITCHING CHARACTERISTICS (Notes 2 & 3)
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t
(V
= 100 Vdc, ID = 18 Adc,
DD
= 5.0 Vdc, RG = 2.5 W)
V
GS
(V
= 160 Vdc, ID = 30 Adc,
DD
= 10 Vdc, RG = 9.1 W)
V
GS
Fall Time t
Gate Charge
(VDS = 160 Vdc, ID = 30 Adc,
V
= 10 Vdc)
(V
GS
= 160 Vdc, ID = 18 Adc,
DS
VGS = 5.0 Vdc)
BODY−DRAIN DIODE RATINGS (Note 2)
Forward On−Voltage (IS = 30 Adc, VGS = 0 Vdc)
(I
= 30 Adc, VGS = 0 Vdc, TJ = 150°C)
S
Reverse Recovery Time
(IS = 30 Adc, VGS = 0 Vdc,
/dt = 100 A/ms)
dI
S
Reverse Recovery Stored Charge Q
2. Indicates Pulse Test: P. W. = 300 ms max, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperature.
Symbol Min Ty p Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
C
t
d(on)
d(off)
Q
Q
Q
V
t
t
t
FS
iss
oss
rss
r
f
tot
gs
gd
SD
rr
a
b
RR
200
−
−
−
−
307
−
−
−
−
5.0
125
− − ± 100 nAdc
2.0
−
−
−
−
2.9
−8.9
0.068
0.067
0.200
4.0
−
0.081
0.080
0.240
− 2.0 2.5
− 20 − Mhos
− 2335 − pF
−
−
380
148
−
−
− 75 −
−
−
−
−
−
−
−
−
−
−
−
−
10
12
20
70
40
82
24
88
75
48
20
16
−
−
−
−
−
−
−
−
100
−
−
−
− 32 −
−
−
0.91
0.80
1.1
−
− 230 −
− 140 −
− 85 −
− 1.85 −
Vdc
mV/°C
mAdc
Vdc
mV/°C
Vdc
ns
nC
Vdc
ns
mC
W
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2
Page 3
NTP30N20
60
50
40
30
20
, DRAIN CURRENT (AMPS)
10
D
I
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
9 V
Figure 1. On−Region Characteristics
0.2
VGS = 10 V
0.15
0.1
TJ = 100°C
TJ = 25°C
7 V
8 V
6 V
TJ = 25°C
5 V
4 V
60
VDS ≥ 10 V
50
40
30
20
, DRAIN CURRENT (AMPS)
D
10
I
0
106420
0
TJ = 25°C
TJ = 100°C
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = −55°C
8
106420
Figure 2. Transfer Characteristics
0.1
TJ = 25°C
0.09
0.08
0.07
VGS = 10 V
VGS = 15 V
0.05
, DRAIN−TO−SOURCE RESISTANCE (W)
DS(on)
R
0
TJ = −55°C
3525155
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
3
ID = 15 A
V
= 10 V
2.5
1.5
0.5
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
DS(on),
R
GS
2
1
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
150
0.06
, DRAIN−TO−SOURCE RESISTANCE (W)
5545
0.05
DS(on)
R
453525155
ID, DRAIN CURRENT (AMPS)
55
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100000
1751251007550250−25−50
10000
, LEAKAGE (nA)
DSS
I
1000
100
10
VGS = 0 V
TJ = 175°C
TJ = 100°C
60 200808100 120 140
4020
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
160 180
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
Page 4
NTP30N20
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
remains virtually constant at a level
GS
. Therefore, rise and fall
SGP
times may be approximated by the following:
t
= Q2 x RG/(VGG − V
r
tf = Q2 x RG/V
GSP
GSP
)
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
RG = the gate drive resistance
and Q
and V
2
are read from the gate charge curve.
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(V
iss
In (VGG/V
iss
GG
GSP
− V
)
GSP
)]
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
and is read at a voltage corresponding to the
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
6000
5000
C
iss
4000
3000
C
rss
2000
C, CAPACITANCE (pF)
1000
0
05 510 20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
V
Figure 7. Capacitance Variation
VGS = 0 VVDS = 0 V
C
rss
015
V
GS
DS
(VOLTS)
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4
TJ = 25°C
C
iss
C
oss
25
Page 5
10
12
NTP30N20
V
DS,
GS
180
150
120
90
60
30
Q
T
V
DS
8
Q
6
4
2
1
Q
2
V
ID = 30 A
T
= 25°C
J
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
100
t, TIME (ns)
10
VDD = 160 V
I
= 30 A
D
= 10 V
V
GS
t
r
t
d(off)
t
d(on)
t
f
0
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
GS
0
10 5030 60
20 7040
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
30
VGS = 0 V
25
T
= 25°C
J
20
15
10
, SOURCE CURRENT (AMPS)
5
S
I
0
Figure 10. Diode Forward Voltage versus Current
0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
10.5
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
) nor rated voltage (V
DM
transition time (t
) do not exceed 10 ms. In addition the total
r,tf
) is exceeded and the
DSS
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− TC)/(R
).
JC
q
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
), the energy rating is specified at rated
DM
), in accordance with industry custom.
D
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
can safely be assumed to
D
equal the values indicated.
5
Page 6
NTP30N20
SAFE OPERATING AREA
1000
VGS = 20 V
SINGLE PULSE
T
= 25°C
100
C
10
1
, DRAIN CURRENT (AMPS)
D
I
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1 1.0 100
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
10 175
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.1
0.05
(NORMALIZED)
0.02
0.01
SINGLE PULSE
0.01
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
500
400
10 ms
100 ms
1 ms
300
200
10 ms
dc
1000
100
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
0
AS
E
25 50 75 100 125
Figure 12. Maximum Avalanche Energy versus
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
t, TIME (ms)
Figure 13. Thermal Response
ID = 30 A
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Starting Junction Temperature
R
(t) = r(t) R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
− TC = P
J(pk)
2
q
JC
(pk)
1.0 100.10.010.0010.00010.00001
1
R
(t)
q
JC
di/dt
I
S
t
rr
t
t
a
b
TIME
I
S
0.25 I
S
t
p
Figure 14. Diode Reverse Recovery Waveform
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Page 7
NTP30N20
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
B
4
Q
123
F
SEATING
−T−
PLANE
A
T
C
S
H
K
Z
U
L
V
G
D
N
R
J
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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7
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