Datasheet ntms4920n Datasheet

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NTMS4920N

Power MOSFET

30 V, 17 A, N−Channel, SO−8

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

• DC−DC Converters

• Points of Loads

• Power Load Switch

• Motor Controls

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

Power Dissipation R (Note 1)

Continuous Drain Current R

Power Dissipation R (Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation R

, t v 10 s(Note 1)

Pulsed Drain Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 18 Apk, L = 1.0 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

THERMAL RESISTANCE MAXIMUM RATINGS

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t v 10 s (Note 1)

Junction−to−Foot (Drain)

Junction−to−Ambient – Steady State (Note 2)

1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).

2. Surfacemounted on FR4 board using the minimum recommended pad size.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter Symbol Value Unit

Steady

(Note 1)

(Note 2)

, t v 10 s

Parameter Symbol Value Unit

State

Steady

State

Steady

State

Steady

State

Steady

State

TA = 25°C, tp = 10 ms

DSS

TA = 25°C

TA = 70°C 11.3

TA = 25°C P

TA = 25°C

TA = 70°C 8.5

TA = 25°C P

TA = 25°C

TA = 70°C 13.6

TA = 25°C P

stg

30 V

±20 V

14.1

1.46 W

10.6

0.82 W

2.12 W

136 A

−55 to 150

2.1 A

162 mJ

260 °C

85.5

152

°C

°C/W

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(BR)DSS

30 V

DS(ON)

4.3 mW @ 10 V

5.7 mW @ 4.5 V

N−Channel

MAX ID MAX

17 A

MARKING DIAGRAM/

PIN ASSIGNMENT

SO−8 CASE 751 STYLE 12

4920N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

Source Source Source

Gate

Top View

AYWWG

4920N

Drain Drain Drain Drain

ORDERING INFORMATION

Device Package Shipping

NTMS4920NR2G SO−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Reel

†

September, 2009 − Rev. 1

1 Publication Order Number:

NTMS4920N/D

Page 2

NTMS4920N

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Ty p Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage Temperature Coefficient

(BR)DSS/TJ

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V, VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature

Coefficient

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V, ID = 7.5 A 3.6 4.3 mW

VGS = 4.5 V, ID = 6.5 A 4.6 5.7

Forward Transconductance g

VDS = 1.5 V, ID = 7.5 A 30.8 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

iss

oss

rss

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 25 V

VGS = 4.5 V, VDS = 15 V, ID = 7.5 A

VGS = 10 V, VDS = 15 V, ID = 7.5 A 58.9 nC

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

d(off)

VGS = 10 V, VDS = 15 V,

ID = 1.0 A, RG = 6.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, IS = 2.0 A

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 2.0 A

PACKAGE PARASITIC VALUES

Source Inductance L

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

30 V

12.2 mV/°C

TJ = 25°C 1.0 mA

TJ = 125°C 10

1.5 3.0 V

5.4 mV/°C

4068

1170

26.3

6.4

10.4

3.8

15.3

4.7

68.6

42.2

TJ = 25°C 0.7 1.0

TJ = 125°C 0.53

50.3

25.7

24.6

65 nC

0.66

0.2

1.5

0.4 1.0

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Page 3

NTMS4920N

TYPICAL PERFORMANCE CURVES

4.5 V

3.6 V

3.2 V

3 V

10V

TJ = 25°C

2.8 V

2.6 V

32 30 28 26 24 22 20 18 16 14 12 10

DRAIN CURRENT (AMPS)

4 2

2 V

2.4 V

2.2 V

0 0.5 1.0 1.5 2.0 1 2 3 4

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

65 60

VDS ≥ 10 V 55 50 45 40 35 30 25 20 15

DRAIN CURRENT (AMPS)

TJ = 25°C

5 0

1.5 2.5 3.5 4.5

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = 125°C

TJ = −55°C

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.050

0.045

0.040

TJ = 25°C ID = 7.5 A

0.035

0.030

0.025

0.020

0.015

0.010

0.005

DRAIN−TO−SOURCE RESISTANCE (W)

0.000 246810

DS(on),

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.006

TJ = 25°C

0.005

VGS = 4.5 V

0.004

VGS = 10 V

0.003

DRAIN−TO−SOURCE RESISTANCE (W)

0.002 5101520

DS(on),

7.5 12.5 17.5

ID, DRAIN CURRENT (AMPS)

25 3022.5 27.5

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.8 VGS = 10 V ID = 7.5 A

1.6

1.4

1.2

DRAIN−TO−SOURCE

1.0

DS(on),

0.8

RESISTANCE (NORMALIZED)

0.6

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

10000

1000

, LEAKAGE (nA)

DSS

100

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Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

VGS = 0 V

TJ = 125°C

TJ = 100°C

51015202530

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

Page 4

NTMS4920N

TYPICAL PERFORMANCE CURVES

5000

4500

4000

3500

3000

2500

2000

1500

C, CAPACITANCE (pF)

1000

500

0510

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source and

1000

VDS = 15 V ID = 1 A VGS = 10 V

100

TJ = 25°C VGS = 0 V

iss

oss

rss

15 25

, GATE-TO-SOURCE VOLTAGE (VOLTS)

30 0 20

Drain−To−Source Voltage vs. Total Charge

d(off)

VGS = 0 V TJ = 25°C

1.5

VGS = 10 V ID = 7.5 A TJ = 25°C

10 30 50

40 60

QG, TOTAL GATE CHARGE (nC)

t, TIME (ns)

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

SINGLE PULSE TC = 25°C

, DRAIN CURRENT (AMPS)

0.1

0.01

0.01 10 100

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

0.1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

d(on)

10 ms

100 ms

1 ms

10 ms

0.5

, SOURCE CURRENT (AMPS)

0.5 0.6 0.65 0.7

0.55

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

175

150

125

100

AVALANCHE ENERGY (mJ)

25 50 75 100

EAS, SINGLE PULSE DRAIN−TO−SOURCE

, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.75

ID = 18 A

0.8

150125

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Page 5

−Y−

−Z−

NTMS4920N

PACKAGE DIMENSIONS

SOIC−8

CASE 751−07

−X−

0.25 (0.010) Z

0.25 (0.010)

SEATING PLANE

SXS

0.10 (0.004)

X 45

SOLDERING FOOTPRINT*

1.52

0.060

ISSUE AJ

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMS4920N/D