Datasheet ntms4873nf-d Datasheet

Download

Page 1

NTMS4873NF

Power MOSFET

30 V, 11.5 A, N−Channel, SO−8

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Includes SyncFET Schottky Diode

• Optimized Gate Charge to Minimize Switching Losses

• SOIC−8 Surface Mount Package Saves Board Space

• This is a Pb−Free Device

Applications

• Synchronous FET for DC−DC Converters

• Low Side Notebook Non−VCORE Converters

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

Power Dissipation R (Note 1)

Continuous Drain Current R

Power Dissipation R (Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation

, t v 10 s(Note 1)

Pulsed Drain Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V,

= 11 Apk, L = 1 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

THERMAL RESISTANCE MAXIMUM RATINGS

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t v 10 s (Note 1)

Junction−to−Foot (Drain)

Junction−to−Ambient – Steady State (Note 2)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surfacemounted on FR4 board using 1 sq−in pad, 2 oz Cu.

2. Surfacemounted on FR4 board using the minimum recommended pad size.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter

(Note 1)

(Note 2)

, t v 10 s

Steady

State

TA = 25°C, tp = 10 ms

Parameter Symbol Value Unit

Symbol Value Unit

DSS

TA = 25°C

TA = 70°C 7.2

TA = 25°C P

TA = 25°C

TA = 70°C 5.7

TA = 25°C P

TA = 25°C

TA = 70°C 9.2

TA = 25°C P

stg

30 V

±20 V

8.9

1.39 W

7.1

0.87 W

11.5

2.31 W

56 A

−55 to 150

3.3 A

60.5 mJ

260 °C

89.9

54.2

35.6

143

°C

°C/W

http://onsemi.com

(BR)DSS

30 V

DS(ON)

12 mW @ 10 V

15 mW @ 4.5 V

N−Channel

MAX ID MAX

11.5 A

MARKING DIAGRAM/

PIN ASSIGNMENT

SO−8 CASE 751 STYLE 12

4873NF = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

Source Source Source

AYWWG

4873NF

Gate

Top View

Drain Drain Drain Drain

ORDERING INFORMATION

Device Package Shipping

NTMS4873NFR2G SO−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

2500/Tape & Reel

†

January, 2009 − Rev. 1

1 Publication Order Number:

NTMS4873NF/D

Page 2

NTMS4873NF

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V, VDS = 24 V TJ = 25°C 250

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V, ID = 10 A

VGS = 4.5 V, ID = 8.5 A

Forward Transconductance g

VDS = 1.5 V, ID = 10 A 22 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

iss

oss

rss

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1.0 MHz, VDS = 15 V

VGS = 4.5 V, VDS = 15 V, ID = 10 A

VGS = 10 V, VDS = 15 V, ID = 10 A 21.4 32 nC

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(on)

d(off)

VGS = 10 V, VDS = 15 V,

= 1.0 A, RG = 6.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, IS = 3.5 A

VGS = 0 V, dIS/dt = 100 A/ms,

= 10 A

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

TJ = 25°C

TJ = 125°C

30 V

10 mV/°C

1.45 2.5 V

6 mV/°C

9 12

12 15

1275 1900

345 525

145 225

10.5 16

1.3

3.7 6.0

3.9 6.5

9.8 16

3.8 7.0

22.3 45

14.3 25

0.55 0.7

0.5

20 35

9.5 15

10.6 20

9.0 14 nC

0.66 nH

0.20 nH

1.5 nH

1.5 3.0

http://onsemi.com

Page 3

NTMS4873NF

TYPICAL CHARACTERISTICS

10 V

3.5 V

, DRAIN CURRENT (A)

VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.045

0.035

0.025

5 V

4.5 V

4.2 V 4 V

VGS = 3.2 V

3 V

2.8 V

2.6 V

2.4 V

ID = 10 A

, DRAIN CURRENT (A)

2.52.01.51.00.50

0.015

0.013

0.011

0.009

VDS ≥ 10 V

TJ = 125°C

TJ = 25°C

TJ = −55°C

4.543.532.521.51

TJ = 25°C

VGS = 4.5 V

VGS = 10 V

0.015

, DRAIN−TO−SOURCE RESISTANCE (W)

0.005

DS(on)

VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

Figure 3. On−Resistance vs. Gate−to−Source

1.5

1.4

1.3

1.2

1.1

1.0

, DRAIN−TO−SOURCE

0.9

DS(on)

RESISTANCE (NORMALIZED)

0.8

0.7

ID = 11.5 V V

= 10 V

TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 5. On−Resistance Variation with

Voltage

Temperature

0.007

, DRAIN−TO−SOURCE RESISTANCE (W)

0.005

109876543

DS(on)

22.517.512.57.52.5

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

100 M

VGS = 0 V

10 M

, LEAKAGE (nA)

1 M

DSS

0.1 M

150

1251007550250−25−50

TJ = 125°C

TJ = 100°C

27.522.517.512.57.52.5

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

http://onsemi.com

Page 4

2000

1750

1500

1250

1000

750

500

C, CAPACITANCE (pF)

250

NTMS4873NF

TYPICAL CHARACTERISTICS

VGS = 0 V

= 25°C

iss

oss

rss

, GATE−TO−SOURCE VOLTAGE (V)

302520151050

VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

ID = 10 A T

= 25°C

, DRAIN−TO−SOURCE VOLTAGE (V)

201612840

1000

VDD = 15 V I

= 1 A

= 10 V

100

t, TIME (ns)

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation

100

VGS = 20 V Single Pulse T

= 25°C

0.1

, DRAIN CURRENT (A)

−I

0.01

−VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased

vs. Gate Resistance

Limit

DS(on)

Thermal Limit Package Limit

Safe Operating Area

d(off)

d(on)

10 ms

100 ms

1 ms

10 ms

, SOURCE CURRENT (A)

100101

, SINGLE PULSE DRAIN−TO−

SOURCE AVALANCHE ENERGY (mJ)

1001010.1

VGS = 0 V T

= 25°C

0.6 0.70.50.40.30.20.10

, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

ID = 11 A

125 150100755025

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

http://onsemi.com

Page 5

100

0.1

R(t) (°C/W)

0.01

NTMS4873NF

TYPICAL CHARACTERISTICS

50% Duty Cycle

20% 10%

5% 2%

Single Pulse

0.001

0.0010.00010.000010.0000010.0000001

PULSE TIME (sec)

Figure 13. Thermal Response − R

0.01 0.1 1 10 100 1000

at Steady State (1 inch sq pad)

http://onsemi.com

Page 6

−Y−

−Z−

NTMS4873NF

PACKAGE DIMENSIONS

SOIC−8

CASE 751−07

−X−

ISSUE AJ

0.25 (0.010)

SEATING PLANE

0.10 (0.004)

0.25 (0.010) Z

SXS

X 45

SOLDERING FOOTPRINT*

1.52

0.060

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local Sales Representative

NTMS4873NF/D