Pulsed Drain Current
Operating Junction and Storage TemperatureTJ,
Source Current (Body Diode)I
Single Pulse Drain−to−Source Avalanche Energy
(VDD = 25 V, VGS = 10 V, IL Peak = 7.5 A,
L = 10 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
THERMAL RESISTANCE MAXIMUM RATINGS
Junction−to−Ambient – Steady State (Note 1)
Junction−to−Ambient – t v 10 s (Note 1)
Junction−to−Ambient – Steady State (Note 2)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
2. Surfacemounted on FR4 board using the minimum recommended pad size.
DS(on)
ParameterSymbolValueUnit
ParameterSymbolValueUnit
[1 oz] including traces).
= 25°C unless otherwise stated)
J
DSS
GS
Steady
State
t v 10 sTA = 25°C10.3
Steady
State
t v 10 s2.2
Steady
State
TA = 25°C
TA = 85°C6.2
TA = 25°CP
TA = 25°C
TA = 85°C4.6
TA = 25°CP
tp = 10 ms
I
D
D
I
D
D
I
DM
T
stg
S
E
AS
T
L
R
q
JA
R
q
JA
R
q
JA
30V
±20V
8.6
1.5
6.4
0.83W
31A
−55 to
150
2.1A
150mJ
260°C
83.5
58
150
A
W
A
°C
°C/W
http://onsemi.com
V
(BR)DSS
30 V
R
TYPID MAX
DS(ON)
9.0 mW @ 10 V
11.4 mW @ 4.5 V
N−Channel
D
G
(Note 1)
10.3 A
S
MARKING DIAGRAM/
PIN ASSIGNMENT
Source
1
SO−8
CASE 751
STYLE 12
4706N = Device Code
A= Assembly Location
L= WaferLot
Y= Year
WW= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
Source
Source
18
G
Gate
Top View
ALYWG
4706N
Drain
Drain
Drain
Drain
ORDERING INFORMATION
DevicePackageShipping
NTMS4706NR2SO−82500/Tape & Reel
NTMS4706NR2GSO−8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
2500/Tape & Reel
†
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
4. Switching characteristics are independent of operating junction temperatures.
30V
21mV/°C
TJ = 25°C1.0mA
TJ = 125°C50
1.02.5V
−4.8mV/°C
950
400
100
1015
1.25
2.4
4.5
1.82
7.512
4.08.0
2440
1425
TJ = 25°C0.741.0
TJ = 125°C0.57
34
16
18
29nC
pF
nC
W
ns
V
ns
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2
Page 3
NTMS4706N
R
DRAIN−TO−SOURCE RESISTANCE (
)
0
30
0
35
5
TYPICAL PERFORMANCE CURVES
7
TJ = 25°C
2.8 V
2.6 V
2.4 V
2.2 V
8
TJ = 25°C
ID = 10 A
VDS ≥ 10 V
30
25
20
15
10
DRAIN CURRENT (AMPS)
D,
I
5
109
0
TJ = 125°C
TJ = 25°C
TJ = −55°C
3
2
2.51.54.
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
3.5
41
Figure 2. Transfer Characteristics
0.018
TJ = 25°C
0.015
VGS = 4.5 V
0.012
VGS = 10 V
16
81242
14
18
10
0.009
DRAIN−TO−SOURCE RESISTANCE (W)
0.006
DS(on),
R
ID, DRAIN CURRENT (AMPS)
10 V
25
20
15
10
DRAIN CURRENT (AMPS)
5
D,
I
0
0
5 V
3.2 V
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
3 V
62
5137
Figure 1. On−Region Characteristics
W
0.03
0.025
0.02
0.015
0.01
0.005
DS(on),
2
3186496102
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
5
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.8
ID = 10.3 A
VGS = 10 V
1.6
1.4
1.2
DRAIN−TO−SOURCE
1
DS(on),
0.8
R
RESISTANCE (NORMALIZED)
0.6
−500−2525
50150
75
TJ, JUNCTION TEMPERATURE (°C)
1251003
Figure 5. On−Resistance Variation with
Temperature
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
, LEAKAGE (nA)
DSS
I
1000
100
10
VGS = 0 V
TJ = 150°C
TJ = 100°C
126
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
18
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
27
24
21159
3
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3
Page 4
NTMS4706N
TYPICAL PERFORMANCE CURVES
1800
1500
C
iss
VDS = 0 V VGS = 0 V
TJ = 25°C
1200
C
900
C
rss
iss
600
C
C, CAPACITANCE (pF)
oss
300
C
0
1001020
V
V
DS
GS
20
rss
30
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
VDD = 10 V
ID = 10.3 A
VGS = 4.5 V
100
t
r
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
5
QT
V
DS
4
Q
GS
Q
GD
3
2
1
0
0
2
46
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
7
VGS = 0 V
TJ = 25°C
6
5
4
V
ID = 10 A
TJ = 25°C
8
GS
10
20
16
12
8
4
0
DS
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t
t, TIME (ns)
10
1
f
t
d(off)
t
d(on)
110100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
3
2
, SOURCE CURRENT (AMPS)
1
S
I
0
0.70.40.80.5
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
0.90.6
10.3
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4
Page 5
NTMS4706N
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
−Y−
−Z−
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
N
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010)Z
M
Y
SXS
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
4.0
0.155
1.270
0.050
SCALE 6:1
mm
ǒ
inches
Ǔ
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5
Page 6
NTMS4706N
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NTMS4706N/D
6
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