Datasheet ntmfs4845n Datasheet

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NTMFS4845N

Power MOSFET

30 V, 115 A, Single N−Channel, SO−8FL

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• Thermally Enhanced SO−8 Package

• These are Pb−Free Devices*

Applications

• Refer to Application Note AND8195/D

• CPU Power Delivery

• DC−DC Converters

• Low Side Switching

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

(Note 1)

Continuous Drain Current R 10 sec

Power Dissipation R

t v 10 sec

JA,

Continuous Drain Current R (Note 2)

Power Dissipation R

(Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation R

(Note 1)

Pulsed Drain Current

Current limited by package TA = 25°C I

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6 V/ns

Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 V, VGS = 10 V, IL = 39 Apk, L = 0.3 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter Symbol Value Unit

DSS

TA = 25°C

Steady

State

tp=10ms

TA = 85°C 15.8

TA = 25°C P

TA = 25°C

TA = 85°C 25.6

TA = 25°C P

TA = 25°C

TA = 85°C 9.9

TA = 25°C P

TC = 25°C

TC = 85°C 83

TC = 25°C P

TA = 25°C I

Dmaxpkg

TJ,

STG

EAS 228 mJ

30 V

±16 V

2.27 W

35.5

5.95 W

13.7

0.89 W

115

62.5 W

230 A

100 A

−55 to +150

62 A

260 °C

°C

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(BR)DSS

30 V

G (4)

MAX ID MAX

DS(ON)

2.9 mW @ 10 V

4.4 mW @ 4.5 V

D (5,6)

S (1,2,3)

N−CHANNEL MOSFET

115 A

MARKING DIAGRAM

SO−8 FLAT LEAD

CASE 488AA

STYLE 1

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

S S S

4845N

AYWWG

ORDERING INFORMATION

Device Package Shipping

NTMFS4845NT1G SO−8FL

NTMFS4845NT3G SO−8FL

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

(Pb−Free)

Tape & Reel

†

1500 /

5000 /

May, 2010 − Rev. 2

1 Publication Order Number:

NTMFS4845N/D

Page 2

NTMFS4845N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – Steady State (Note 2)

Junction−to−Ambient − t v 10 sec

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

2.0

55.1

140.1

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±16 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V to

11.5 V

VGS = 4.5 V

Forward Transconductance g

VDS = 1.5 V, ID = 30 A 87 S

CHARGES AND CAPACITANCES

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1 MHz, VDS = 12 V

VGS = 4.5 V, VDS = 15 V; ID = 30 A

VGS = 11.5 V, VDS = 15 V,

ID = 30 A

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

VGS = 4.5 V, VDS = 15 V, ID = 15 A,

RG = 3.0 W

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

30 V

TJ = 25 °C 1

TJ = 125°C 10

1.45 1.8 2.5 V

5.2 mV/°C

ID = 30 A 2.2 2.9

ID = 15 A 2.2

ID = 30 A 3.4 4.4

ID = 15 A 3.4

3720

650

335

25.6 39

3.2

9.4

8.6

20.5

48.4

28.9

12.2

mV/°C

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NTMFS4845N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter UnitMaxTypMinTest ConditionSymbol

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

VGS = 11.5 V, VDS = 15 V,

ID = 15 A, RG = 3.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

VGS = 0 V,

IS = 30 A

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 30 A

PACKAGE PARASITIC VALUES

Source Inductance L

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

12.5

27.1

37.7

9.7

TJ = 25°C 0.8 1.0

TJ = 125°C 0.7

20.8

12.6

8.2

9.0 nC

0.65

0.005

1.84

1.3 2.5

200

10 V

180

160

5.0 V

140

120

4.5 V

100

, DRAIN CURRENT (A)

VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

TYPICAL CHARACTERISTICS

TJ = 25°CVGS = 4.2 V

4.0 V

3.8 V

3.6 V

3.4 V

3.2 V

3.0 V

2.8 V

2.6 V

6543210

150 140 130

VDS ≥ 10 V 120 110 100

90 80 70 60 50 40

, DRAIN CURRENT (A)

TJ = 25°C

TJ = 125°C

TJ = −55°C

4321

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NTMFS4845N

TYPICAL CHARACTERISTICS

0.016

0.014

0.012

0.010

0.008

0.006

0.004

0.002

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

Figure 3. On−Resistance vs. Gate−to−Source

1.7 ID = 30 A

1.6 VGS = 10 V

1.5

1.4

1.3

1.2

1.1

1.0

, DRAIN−TO−SOURCE

0.9

0.8

DS(on)

RESISTANCE (NORMALIZED)

0.7

0.6

Figure 5. On−Resistance Variation with

4500

4000

3500

3000

2500

2000

1500

C, CAPACITANCE (pF)

1000

500

iss

oss

rss

42428 6055 65

VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

0.006

ID = 30 A T

= 25°C

0.005

0.004

0.003

TJ = 25°C

VGS = 4.5 V

VGS = 11.5 V

0.002

, DRAIN−TO−SOURCE RESISTANCE (W)

611

109875432

0.001

DS(on)

35 40 60

Figure 4. On−Resistance vs. Drain Current and

Voltage

10,000

, LEAKAGE (nA)

1251007550250−25−50

150

TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)

VGS = 0 V

1000

DSS

100

Gate Voltage

TJ = 150°C

TJ = 125°C

16 20

Figure 6. Drain−to−Source Leakage Current

Temperature

TJ = 25°C

3220161280

, GATE−TO−SOURCE VOLTAGE (V)

15 40 50

vs. Voltage

45353025201050

ID = 30 A TJ = 25°C

Drain−to−Source Voltage vs. Total Charge

5550453025201510

181412108642

, DRAIN−TO−SOURCE VOLTAGE (V)

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NTMFS4845N

TYPICAL CHARACTERISTICS

1000

VDS = 15 V ID = 15 A V

= 11.5 V

100

d(off)

t, TIME (ns)

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation

1000

100

VGS = 20 V Single Pulse

TC = 25°C

, DRAIN CURRENT (A)

Thermal Limit

0.1

Package Limit

VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE(°C)

Figure 11. Maximum Rated Forward Biased

160

140

vs. Gate Resistance

Limit

DS(on)

Safe Operating Area

d(on)

VGS = 0 V TJ = 25°C

, SOURCE CURRENT (A)

100101

0.90.80.70.60.50.4

VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

240

ID = 39 A

10 ms

100 ms

1 ms

10 ms

220

200

180

160

140

120

100

, SINGLE PULSE DRAIN−TO−

SOURCE AVALANCHE ENERGY (mJ)

1001010.1

75 1501251005025

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

1000

(S)

120

100

(A)

30 120

VDS = 1.5 V

90756045150

105

DRAIN CURRENT (A)

125°C

PULSE WIDTH (ms)

100°C

25°C

10,0001000100101

Figure 13. gFS vs. Drain Current Figure 14. Id vs. Pulse Width

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Page 6

0.10 C

0.05 c

1234

TOP VIEW

SIDE VIEW

A0.10 BC

BOTTOM VIEW

2 X

e/2

0.20 C

DETAIL A

NTMFS4845N

PACKAGE DIMENSIONS

DFN5 5x6, 1.27P

(SO−8FL)

CASE 488AA−01

ISSUE D

2 X

0.20 C

DETAIL A

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

3 X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

DIM MIN NOM

4 X

SEATING

PLANE

MILLIMETERS

A 0.90 1.00

A1 0.00 −−−

b 0.33 0.41 c 0.23 0.28

D 5.15 BSC D1 4.50 4.90 D2 3.50 −−−

E 6.15 BSC E1 5.50 5.80 E2 3.45 −−−

e 1.27 BSC G 0.51 0.61 K 0.51 −−−

L 0.51 0.61

L1 0.05 0.17

M 3.00 3.40

q 0 −−−

MAX

1.10

0.05

0.51

0.33

5.10

4.22

6.10

4.30

0.71

−−−

0.71

0.20

3.80 12

SOLDERING FOOTPRINT*

3X 4X

1.330

3.200

0.965

0.495

1.270

4.560

1.530

0.750

0.905

0.475

1.000

4.530

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMFS4845N/D