Datasheet ntmfs4841n Datasheet

NTMFS4841N

Power MOSFET

30 V, 57 A, Single N−Channel, SO−8FL

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These are Pb−Free Devices*

Applications

• Refer to Application Note AND8195/D

• CPU Power Delivery

• DC−DC Converters

to Minimize Conduction Losses

DS(on)

V

(BR)DSS

30 V

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R

MAX ID MAX

DS(ON)

7.0 mW @ 10 V

11.4 mW @ 4.5 V

57 A

MAXIMUM RATINGS (T

Parameter Symbol Value Unit

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1) Steady State

Power Dissipation R

Continuous Drain Current R t = 10 sec

Power Dissipation R

Continuous Drain Current R (Note 2)

Power Dissipation R

Continuous Drain Current R (Note 1)

Power Dissipation R

Pulsed Drain Current

Operating Junction and Storage Temperature

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6 V/ns

Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, IL = 19 Apk, L = 1.0 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

(Note 1)

q

JA

t v 10 sec

q

JA,

(Note 2)

q

JA

(Note 1)

q

JC

q

JA

−

q

JA

q

JA

q

JC

= 25°C unless otherwise stated)

J

TA = 25°C

TA = 85°C 9.5

TA = 25°C

TA = 85°C 1.13

TA = 25°C

TA = 85°C 14.4

Steady

State

tp=10ms

TA = 25°C

TA = 85°C 2.6

TA = 25°C

TA = 85°C 6

TA = 25°C

TA = 85°C 0.45

TC = 25°C

TC = 85°C 41

TC = 25°C

TC = 85°C 21.7

TA = 25°C I

DSS

GS

I

D

P

D

I

D

P

D

I

D

P

D

I

D

P

D

DM

TJ,

T

STG

S

EAS 180 mJ

T

L

30 V

±20 V

13.1

2.17

19.9

5

8.3

0.87

57

41.7

171 A

−55 to +150

35 A

260 °C

A

W

A

W

A

W

A

W

°C

D (5,6)

G (4)

S (1,2,3)

N−CHANNEL MOSFET

MARKING DIAGRAM

D

1

SO−8 FLAT LEAD

CASE 488AA

STYLE 1

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

S S S

G

4841N

AYWWG

G

D

ORDERING INFORMATION

Device Package Shipping

NTMFS4841NT1G SO−8FL

NTMFS4841NT3G SO−8FL

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

(Pb−Free)

Tape & Reel

†

1500 /

5000 /

May, 2010 − Rev. 7

1 Publication Order Number:

NTMFS4841N/D

NTMFS4841N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – Steady State (Note 2)

Junction−to−Ambient − t = 10 sec

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

R

q

JC

R

q

JA

R

q

JA

R

q

JA

3

57.7

143.4

25

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage

V

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

T

J

DSS

GSS

/

VGS = 0 V, ID = 250 mA

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V to

11.5 V

VGS = 4.5 V

Forward Transconductance g

FS

VDS = 15 V, ID = 15 A 16 S

CHARGES AND CAPACITANCES

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

VGS = 0 V, f = 1 MHz, VDS = 12 V

VGS = 4.5 V, VDS = 15 V; ID = 30 A

VGS = 11.5 V, VDS = 15 V,

ID = 30 A

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

r

d(OFF)

f

VGS = 4.5 V, VDS = 15 V, ID = 15 A,

RG = 3.0 W

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

30 V

25

TJ = 25 °C 1

TJ = 125°C 10

1.5 2.5 V

5.6 mV/°C

ID = 30 A 4.7 7.0

ID = 15 A 4.6

ID = 30 A 9.2 11.4

ID = 15 A 8.5

1436

348

177

11.5 17

2.0

5.0

5.1

25.4

13.5

66.5

15.5

7.5

mV/°C

mA

mW

pF

nC

ns

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2

NTMFS4841N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

J

Parameter UnitMaxTypMinTest ConditionSymbol

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

r

d(OFF)

f

VGS = 11.5 V, VDS = 15 V,

ID = 15 A, RG = 3.0 W

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

SD

VGS = 0 V,

IS = 30 A

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

RR

a

b

RR

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 30 A

PACKAGE PARASITIC VALUES

Source Inductance L

Drain Inductance L

Gate Inductance L

Gate Resistance R

S

D

G

TA = 25°C

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

8.1

24.2

22.8

5.7

TJ = 25°C 0.9 1.2

TJ = 125°C 0.8

20.5

11.6

8.9

10.7 nC

0.93

0.005

1.84

3.2

ns

V

ns

nH

W

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3

NTMFS4841N

TYPICAL PERFORMANCE CURVES

140 130 120

110

100

90 80 70 60 50 40 30

, DRAIN CURRENT (AMPS)

D

I

20 10

0

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.018

0.017

0.016

0.015

0.014

0.013

0.012

0.011

0.010

0.009

0.008

0.007

, DRAIN−TO−SOURCE RESISTANCE (W)

0.006

0.005

DS(on)

3

R

5

4

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 3. On−Resistance vs. Gate−to−Source

140

VDS = 10 V

5.5 V to 10 V

21

620

3

789

TJ = 25°C

VGS = 5 V

4.5 V

4 V

3.8 V

3.6 V

3.4 V

4 1

ID = 30 A TJ = 25°C

10 11

130 120

110

100

90 80 70 60 50 40 30

, DRAIN CURRENT (AMPS)

D

I

5

0.017

0.014

0.011

0.008

0.005

, DRAIN−TO−SOURCE RESISTANCE (W)

0.002

DS(on)

R

20 10

0

10

TJ = 25°C

15

TJ = 125°C

TJ = −55°C

23

, GATE−TO−SOURCE VOLTAGE (VOLTS)

V

GS

ID, DRAIN CURRENT (AMPS)

25

30

45

VGS = 4.5 V

VGS = 11.5 V

40 5545 5035

678

60

Figure 4. On−Resistance vs. Drain Current and

Voltage

Gate Voltage

1.8 ID = 30 A

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

(NORMALIZED)

0.9

0.8

, DRAIN−TO−SOURCE RESISTANCE

0.7

0.6

DS(on)

R

V

= 10 V

GS

−55 255−15−35 45 8565

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

125

105

145

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10000

1000

100

10

, LEAKAGE (nA)

DSS

I

1

0.1

4

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 25°C

1510 305

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

20

25

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

NTMFS4841N

TYPICAL PERFORMANCE CURVES

2200

2000

1800

1600

1400

C

iss

TJ = 25°C

C

iss

1200

1000

800

600

C, CAPACITANCE (pF)

400

200

C

rss

C

oss

C

0

10 0 10 15 30

55

V

GS

V

DS

rss

20

25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

1000

VDD = 15 V ID = 15 A VGS = 11.5 V

100

t

r

t

t, TIME (ns)

10

d(off)

t

d(on)

t

f

1

1 10 100

RG, GATE RESISTANCE (W)

12

11

Q

T

10

9 8

7

6

5

Q

GS

4

3

2 1

0

, GATE−TO−SOURCE VOLTAGE (VOLTS)

0

GS

V

Q

GD

8

426 1614 2612

10

QG, TOTAL GATE CHARGE (nC)

VDD = 15 V VGS = 11.5 V ID = 30 A TJ = 25°C

18 20 22

Figure 8. Gate−To−Source and Drain−To−Source

Voltage vs. Total Charge

30

VGS = 0 V

TJ = 25°C

25

20

15

10

, SOURCE CURRENT (AMPS)

5

S

I

0

0.5 1.0

0.6 0.7

0.8 0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

24

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

1000

100

VGS = 20 V

10

, DRAIN CURRENT (AMPS)

D

I

1

0.1 1 100

SINGLE PULSE TC = 25°C

R

LIMIT

DS(on)

THERMAL LIMIT PACKAGE LIMIT

10

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

dc

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

AS

E

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Figure 10. Diode Forward Voltage vs. Current

180

160

140

120

100

80

60

40

20

0 25

50 75

TJ, STARTING JUNCTION TEMPERATURE (°C)

ID = 19 A

100 125

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

150

100

NTMFS4841N

TYPICAL PERFORMANCE CURVES

100°C

25°C

125°C

10

, DRAIN CURRENT (AMPS)

D

I

1

10

10001 100

PULSE WIDTH (ms)

Figure 13. EAS vs. Pulse Width

1.0

0.1

0.01

, EFFECTIVE TRANSIENT

THERMAL RESPONSE

JA

q

R

Single Pulse

0.0086 W

0.00004

Normalized to R

0.026 W

0.078 W

0.0002

0.0006

0.748 W

0.004

at Steady State (1 inch)

q

JA

4.92 W

7.46 W

15.76 W

0.033

0.139

1.03

23 W

2.4

0.001 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03

t, time (s)

Figure 14. FET Thermal Response

57

51 W

Ambient

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0.10 C

l

0.10 C

0.05 c

D

2

D1

1234

TOP VIEW

SIDE VIEW

b

8X

A0.10 BC

L

14

E2

6

G

D2

BOTTOM VIEW

56

5

2 X

e/2

0.20 C

A

E1

E

2

A

DETAIL A

K

M

L1

NTMFS4841N

PACKAGE DIMENSIONS

DFN5 5x6, 1.27P

(SO−8FL)

CASE 488AA−01

ISSUE D

B

2 X

0.20 C

c

DETAIL A

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

3 X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

DIM MIN NOM

4 X

A1 0.00 −−−

q

D1 4.50 4.90

A1

D2 3.50 −−−

E1 5.50 5.80 E2 3.45 −−−

C

e

SEATING

PLANE

L1 0.05 0.17

MILLIMETERS

A 0.90 1.00

b 0.33 0.41

c 0.23 0.28

D 5.15 BSC

E 6.15 BSC

e 1.27 BSC G 0.51 0.61 K 0.51 −−− L 0.51 0.61

M 3.00 3.40

q 0 −−−

_

MAX

1.10

0.05

0.51

0.33

5.10

4.22

6.10

4.30

0.71

−−−

0.71

0.20

3.80 12

_

SOLDERING FOOTPRINT*

3X 4X

1.330

3.200

0.965

2X

0.495

1.270

4.560

2X

1.530

0.750

2X

0.905

0.475

4X

1.000

4.530

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMFS4841N/D

7