Datasheet ntmfs4837n-d Datasheet

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NTMFS4837N

Power MOSFET

30 V, 74 A, Single N−Channel, SO−8FL

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These are Pb−Free Devices*

Applications

• Refer to Application Note AND8195/D

• CPU Power Delivery

• DC−DC Converters

• Low Side Switching

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R (Note 1)

Power Dissipation R

(Note 1)

Continuous Drain Current R (Note 2)

Power Dissipation R

(Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation R

(Note 1)

Pulsed Drain Current

Operating Junction and Storage Temperature TJ,

Source Current (Body Diode) I

Drain to Source dV/dt dV/dt 6 V/ns

Single Pulse Drain−to−Source Avalanche Energy (VDD = 30 V, VGS = 10 V, IL = 22 Apk, L = 1.0 mH, RG = 25 W)

Lead Temperature for Soldering Purposes (1/8” from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Parameter Symbol Value Unit

DSS

TA = 25°C

Steady

State

tp=10ms

TA = 85°C 11.5

TA = 25°C P

TA = 25°C

TA = 85°C 7

TA = 25°C P

TC = 25°C

TC = 85°C 53

TC = 25°C P

TA = 25°C I

STG

EAS 242 mJ

30 V

±20 V

2.2 W

0.88 W

47.2 W

148 A

−55 to +150

39 A

260 °C

°C

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(BR)DSS

30 V

G (4)

MAX ID MAX

DS(ON)

5.0 mW @ 10 V

7.5 mW @ 4.5 V

D (5,6)

S (1,2,3)

N−CHANNEL MOSFET

74 A

MARKING DIAGRAM

4837N

SO−8 FLAT LEAD

CASE 488AA

STYLE 1

A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

AYWWG

ORDERING INFORMATION

Device Package Shipping

NTMFS4837NT1G SO−8FL

(Pb−Free)

NTMFS4837NT3G SO−8FL

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

1500 /

Tape & Reel

5000 /

Tape & Reel

†

May, 2010 − Rev. 5

1 Publication Order Number:

NTMFS4837N/D

Page 2

NTMFS4837N

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain)

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

2.65

56.75

142.2

°C/W

ELECTRICAL CHARACTERISTICS (T

Parameter

= 25°C unless otherwise specified)

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V

Drain−to−Source Breakdown Voltage

Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V,

VDS = 24 V

VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature Coefficient V

Drain−to−Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 10 V to

11.5 V

VGS = 4.5 V

Forward Transconductance g

VDS = 15 V, ID = 15 A 15 S

CHARGES AND CAPACITANCES

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

G(TOT)

VGS = 0 V, f = 1 MHz, VDS = 12 V

VGS = 4.5 V, VDS = 15 V; ID = 30 A

VGS = 11.5 V, VDS = 15 V;

ID = 15 A

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

Turn−On Delay Time t

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

d(ON)

d(OFF)

VGS = 4.5 V, VDS = 15 V, ID = 15 A,

RG = 3.0 W

VGS = 11.5 V, VDS = 15 V,

ID = 15 A, RG = 3.0 W

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

30 V

TJ = 25 °C 1

TJ = 125°C 10

1.5 2.5 V

5.7 mV/°C

ID = 30 A 3.5 5.0

ID = 15 A 3.5

ID = 30 A 5.9 7.5

ID = 15 A 5.9

2048

444

239

14.2 22

2.98

5.7

6.7

34.2

14.2

8.5

25.6

25.2

9.2

mV/°C

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NTMFS4837N

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

Parameter UnitMaxTypMinTest ConditionSymbol

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

VGS = 0 V,

IS = 30 A

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

VGS = 0 V, dIS/dt = 100 A/ms,

= 30 A

PACKAGE PARASITIC VALUES

Source Inductance L

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

100

, DRAIN CURRENT (A)

10 V to 4.5 V

GS =

TJ = 25°C

3.8 V

3.6 V

3.4 V

3.2 V

3254

100

, DRAIN CURRENT (A)

12345678

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 1. On−Region Characteristics

TJ = 25°C 0.85 1.2

TJ = 125°C 0.72

14 nC

0.93

0.005

1.84

2.8

VDS ≥ 10 V

TJ = −55°C

TJ = 25°C

TJ = 125°C

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 2. Transfer Characteristics

0.016

0.015

0.014

0.013

0.012

0.011

0.010

0.009

0.008

0.007

0.006

0.005

0.004

, DRAIN−TO−SOURCE RESISTANCE (W)

0.003

3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11

DS(on)

VGS, GATE−TO−SOURCE VOLTAGE (V)

Figure 3. On−Resistance vs. V

T = 25°C ID = 30 A

, DRAIN−TO−SOURCE RESISTANCE (W)

11.5

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0.01

0.009

0.008

0.007

0.006

0.005

0.004

0.003

0.002

0.001

DS(on)

TJ = 25°C

VGS = 4.5 V

VGS = 11.5 V

20 40 60 90

30 8010 50 70

ID, DRAIN CURRENT (A)

Figure 4. On−Resistance vs. Drain Current &

Gate Voltage

Page 4

NTMFS4837N

1.80 ID = 30 A

= 10 V & 4.5 V

1.60

1.40

1.20

1.00

(NORMALIZED)

0.80

, DRAIN−TO−SOURCE RESISTANCE

0.60

DS(on)

−50 250−25 50 75 125

100

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

3000

ISS

2000

1000

C, CAPACITANCE (pF)

OSS

RSS

10 5 0 5 10152025

GSVDS

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

TJ = 25°C

100000

10000

1000

100

, LEAKAGE (nA)

DSS

150

VGS = 0 V

TJ = 150°C

TJ = 125°C

TJ = 25°C

510152025

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 6. Drain−to−Source Leakage Current vs.

Voltage

, GATE−TO−SOURCE VOLTAGE (V)

QG, TOTAL GATE CHARGE (nC)

VDD = 15.0 V VGS = 11.5 V

ID = 30 A

TJ = 25°C

302520151050

Figure 7. Capacitance Variation Figure 8. Gate−to−Source & Drain−to−Source

1000

t, TIME (ns)

VDD = 15 V

ID = 15 A

VGS = 11.5 V

100

d(off)

d(on)

1 10 100

RG, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation vs.

Gate Resistance

, SOURCE CURRENT (A)

0.50 0.60 0.80

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Voltage vs. Total Charge

VGS = 0 V TJ = 25°C

VSD, SOURCE−TO−DRAIN VOLTAGE (V)

Figure 10. Diode Forward Voltage vs. Current

Page 5

NTMFS4837N

1000

VGS = 20 V

Single Pulse

TC = 25°C

100

Limit

, DRAIN CURRENT (A)

0.1

DS(on)

Thermal Limit Package Limit

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Figure 11. Maximum Rated Forward−Biased

Safe Operating Range

100

(A)

10 ms

100 ms

10 ms

100 ms

100

125°C

250

225

200

175

150

125

100

EAS, SINGLE PULSE DRAIN−TO−

SOURCE AVALANCHE ENERGY (mJ)

25 50 75 100 125 150

, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs,

Starting Junction Temperature

25°C

100°C

ID = 22 A

PULSE WIDTH (ms)

100

1000

Figure 13. EAS vs. Pulse Width

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Page 6

0.10 C

0.05 c

1234

TOP VIEW

SIDE VIEW

A0.10 BC

BOTTOM VIEW

2 X

e/2

0.20 C

DETAIL A

NTMFS4837N

PACKAGE DIMENSIONS

DFN5 5x6, 1.27P

(SO−8FL)

CASE 488AA−01

ISSUE D

2 X

0.20 C

3 X

DETAIL A

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

4 X

1.330

3.200

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

DIM MIN NOM

A 0.90 1.00

A1 0.00 −−−

b 0.33 0.41 c 0.23 0.28 D 5.15 BSC

D1 4.50 4.90

SEATING

PLANE

D2 3.50 −−−

E 6.15 BSC E1 5.50 5.80 E2 3.45 −−−

e 1.27 BSC

G 0.51 0.61

K 0.51 −−−

L 0.51 0.61 L1 0.05 0.17

M 3.00 3.40

q 0 −−−

SOLDERING FOOTPRINT*

3X 4X

1.270

0.965

0.495

1.530

4.560

MILLIMETERS

0.750

0.905

0.475

MAX

1.10

0.05

0.51

0.33

5.10

4.22

6.10

4.30

0.71

−−−

0.71

0.20

3.80 12

1.000

4.530

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMFS4837N/D