• Optimized Gate Charge to Minimize Switching Losses
• These are Pb−Free Devices
Applications
• Refer to Application Note AND8195/D
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
to Minimize Conduction Losses
DS(on)
V
(BR)DSS
30 V
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R
MAXID MAX
DS(ON)
4.0 mW @ 10 V
6.0 mW @ 4.5 V
D (5,6)
90 A
MAXIMUM RATINGS (T
ParameterSymbolValueUnit
Drain−to−Source VoltageV
Gate−to−Source VoltageV
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Continuous Drain
Current R
(Note 2)
Power Dissipation
R
Continuous Drain
Current R
(Note 1)
Power Dissipation
R
Pulsed Drain
Current
Operating Junction and Storage
Temperature
Source Current (Body Diode)I
Drain to Source DV/DTdV/dt6V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 22 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
(Note 1)
q
JA
(Note 2)
q
JA
(Note 1)
q
JC
q
JA
q
JA
q
JC
= 25°C unless otherwise stated)
J
TA = 25°C
TA = 85°C13
TA = 25°CP
TA = 25°C
Steady
State
TA = 85°C8
TA = 25°CP
TC = 25°C
TC = 85°C65
TC = 25°CP
TA = 25°C,
tp = 10 ms
DSS
GS
I
D
D
ID
D
I
D
D
I
DM
TJ,
T
STG
S
EAS242mJ
T
L
30V
±20V
18
2.25W
11
0.89W
90
55.6W
180A
−55 to
+150
46A
260°C
A
A
A
°C
G (4)
S (1,2,3)
N−CHANNEL MOSFET
MARKING
DIAGRAM
D
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
S
S
S
G
4836N
AYWWG
G
D
ORDERING INFORMATION
DevicePackageShipping
NTMFS4836NT1GSO−8FL
(Pb−Free)
NTMFS4836NT3GSO−8FL
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
R
q
JC
R
q
JA
R
q
JA
2.25
55.6
140.8
°C/W
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
SymbolTest ConditionMinTypMaxUnit
OFF CHARACTERISTICS
Drain−to−Source Breakdown VoltageV
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V
(BR)DSS/TJ
Zero Gate Voltage Drain CurrentI
Gate−to−Source Leakage CurrentI
(BR)DSS
DSS
GSS
VGS = 0 V, ID = 250 mA
VGS = 0 V,
VDS = 24 V
VDS = 0 V, VGS = ±20 V±100nA
ON CHARACTERISTICS (Note 5)
Gate Threshold VoltageV
Negative Threshold Temperature CoefficientV
Drain−to−Source On ResistanceR
GS(TH)
GS(TH)/TJ
DS(on)
VGS = VDS, ID = 250 mA
VGS = 10 V to
11.5 V
VGS = 4.5 V
Forward Transconductanceg
FS
VDS = 15 V, ID = 15 A24S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Total Gate ChargeQ
Threshold Gate ChargeQ
Gate−to−Source ChargeQ
Gate−to−Drain ChargeQ
Total Gate ChargeQ
ISS
OSS
RSS
G(TOT)
G(TH)
GS
GD
G(TOT)
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V;
VGS = 11.5 V, VDS = 15 V;
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Timet
Rise Timet
Turn−Off Delay Timet
Fall Timet
Turn−On Delay Timet
Rise Timet
Turn−Off Delay Timet
Fall Timet
d(ON)
r
d(OFF)
f
d(ON)
r
d(OFF)
f
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
ID = 30 A
ID = 30 A
30V
25
TJ = 25 °C1
TJ = 125°C10
1.52.5V
6.0mV/°C
ID = 30 A2.84.0
ID = 15 A2.8
ID = 30 A4.86.0
ID = 15 A4.8
2677
565
307
2028
3.2
8.0
8.0
45
14
30
20
12
8.0
27
31
7.0
mV/°C
mA
mW
pF
nC
nC
ns
ns
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2
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NTMFS4836N
ELECTRICAL CHARACTERISTICS (T
Parameter
= 25°C unless otherwise specified)
J
SymbolTest ConditionMinTypMaxUnit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode VoltageV
Reverse Recovery Timet
Charge Timet
Discharge Timet
Reverse Recovery ChargeQ
PACKAGE PARASITIC VALUES
Source InductanceL
Drain InductanceL
Gate InductanceL
Gate ResistanceR
RR
SD
a
b
RR
S
D
G
G
VGS = 0 V,
IS = 30 A
TJ = 25°C0.831.2
TJ = 125°C0.7
VGS = 0 V, dIS/dt = 100 A/ms,
= 30 A
I
S
TA = 25°C
27.1
13.8
ns
13.3
16nC
0.65nH
0.005nH
1.84nH
1.2
W
V
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3
Page 4
NTMFS4836N
TYPICAL PERFORMANCE CURVES
120
110
100
90
80
70
60
50
40
30
, DRAIN CURRENT (AMPS)
20
D
I
10
0
021
VGS = 4.5 to 5.0 V
3
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region CharacteristicsFigure 2. Transfer Characteristics
0.030
0.025
0.020
0.015
110
TJ = 25°C
40
5
768910
4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
ID = 30 A
TJ = 25°C
0.008
0.007
0.006
0.005
0.004
VDS ≥ 10 V
100
90
80
70
60
50
40
30
, DRAIN CURRENT (AMPS)
20
D
I
10
0
TJ = 25°C
TJ = 25°C
TJ = 125°C
1
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
23
TJ = −55°C
46
VGS = 4.5 V
5
0.010
0.005
, DRAIN−TO−SOURCE RESISTANCE (W)
0
DS(on)
2
R
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source
1.80
ID = 30 A
V
= 10 V & 4.5 V
1.60
1.40
1.20
1.00
(NORMALIZED)
0.80
, DRAIN−TO−SOURCE RESISTANCE
0.60
DS(on)
R
GS
−50250−255075
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
0.003
0.002
0.001
, DRAIN−TO−SOURCE RESISTANCE (W)
0
615
8
1012
DS(on)
R
10
20
253055
ID, DRAIN CURRENT (AMPS)
VGS = 11.5 V
35
405045
Figure 4. On−Resistance vs. Drain Current and
Voltage
100
125
100,000
10,000
1,000
, LEAKAGE (nA)
100
DSS
I
150
VGS = 0 V
10
8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Gate Voltage
TJ = 150°C
TJ = 125°C
1612304
20
24
28
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
60
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4
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NTMFS4836N
TYPICAL PERFORMANCE CURVES
5000
4500
C
iss
TJ = 25°C
4000
3500
3000
2500
2000
C
rss
C
iss
1500
C, CAPACITANCE (pF)
1000
500
C
oss
0
1501015
55
1025
V
GS
V
DS
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
VDS = 15 V
ID = 15 A
100
t, TIME (ns)
10
VGS = 11.5 V
t
f
t
d(off)
t
r
t
d(on)
30
12
Q
T
10
8
V
DS
V
GS
6
Q
4
2
Q
gs
gd
ID = 30 A
TJ = 25°C
0
, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
GS
V
QG, TOTAL GATE CHARGE (nC)
2010254540
155
30
35
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
VGS = 0 V
TJ = 25°C
25
20
15
10
20
18
16
14
12
10
8
6
4
2
0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
110100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
100
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1
, DRAIN CURRENT (AMPS)
D
I
0.1
0.11100
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10 ms
100 ms
1 ms
10 ms
dc
, SOURCE CURRENT (AMPS)
5
S
I
0
0.50.6
0.41.1
0.70.8
0.91.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
260
240
220
200
180
160
140
120
100
80
60
40
AVALANCHE ENERGY (mJ)
20
, SINGLE PULSE DRAIN−TO−SOURCE
0
AS
25
E
5075
100125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
ID = 22 A
150
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NTMFS4836N
TYPICAL PERFORMANCE CURVES
100
10
125°C
100°C
, DRAIN CURRENT (AMPS)
D
I
1
125°C
10
PULSE WIDTH (ms)
10001100
Figure 13. Avalanche Characteristics
10000
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6
Page 7
0.10 C
0.10 C
0.05 c
D
2
D1
1234
TOP VIEW
SIDE VIEW
b
8X
A0.10BC
L
14
E2
6
G
D2
BOTTOM VIEW
56
5
2 X
e/2
0.20 C
A
E1
E
2
A
DETAIL A
K
M
L1
NTMFS4836N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA−01
ISSUE D
B
2 X
0.20 C
c
DETAIL A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
3 X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
DIM MINNOM
4 X
q
A1
C
e
SEATING
PLANE
MILLIMETERS
A0.901.00
A10.00−−−
b0.330.41
c0.230.28
D5.15 BSC
D14.504.90
D23.50−−−
E6.15 BSC
E15.505.80
E23.45−−−
e1.27 BSC
G0.510.61
K0.51−−−
L0.510.61
L10.050.17
M3.003.40
q0 −−−
_
MAX
1.10
0.05
0.51
0.33
5.10
4.22
6.10
4.30
0.71
−−−
0.71
0.20
3.80
12
_
SOLDERING FOOTPRINT*
3X4X
1.330
3.200
0.965
2X
0.495
1.270
4.560
2X
1.530
0.750
2X
0.905
0.475
4X
1.000
4.530
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTMFS4836N/D
7
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