Datasheet ntmfs4701n Datasheet

NTMFS4701N

Power MOSFET

30 V, 20 A, Single N-Channel,
SOIC-8 Flat Lead Package

Features

•Thermally and Electrically Enhanced Packaging Compatible with

Standard SOIC-8

•New Package Provides Capability of Inspection and Probe After

Board Mounting

•Ultra Low R

•Optimized for High Side Control Applications

•High Speed Switching Capability

•These are Pb-Free Devices

Applications

•Notebook Computer VCORE Applications

•Network Applications

•DC-DC Converters

(at 4.5 VGS), Low Gate Resistance and Low Q

DS(on)

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R

Typ

G

(BR)DSS

30 V

DS(on)

6.0 mW @ 10 V

8.0 mW @ 4.5 V

N-Channel

D

ID MaxV

20 A

MAXIMUM RATINGS (T

Drain-to-Source Voltage V

Gate-to-Source Voltage V

Continuous Drain Current

(Note 1 )

Power Dissipation

(Note 1)

Continuous Drain Current

(Note 2)

Power Dissipation

(Note 2)

Pulsed Drain Current

Operating and Storage Temperature TJ, T

Source Current (Body Diode) I

Single Pulse Drain-to-Source Avalanche Energy

(VDD = 25 V, VGS = 10 V, IPK = 7.5 A,
L = 10 mH, RG = 25 W)

Lead Temperature for Soldering Purposes

(1/8 in from case for 10 s)

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

1. Surface-mounted on FR4 board using 1 in sq. pad size
(Cu area 1.127 in sq. [1 oz} including traces).

2. Surface-mounted on FR4 board using minimum recommended pad size
(Cu area 0.412 in sq.).

= 25°C unless otherwise noted)

J

Rating Symbol Value Unit

D

D

D

stg

L

30 V

$20 V

12.3

20

2.3 W

6.0

7.7

0.9 W

60 A

-55 to
150

6.0 A

280 mJ

260 °C

A

A

°C

Steady

State

t v10 s TA = 25°C I

Steady

State

t v10 s TA = 25°C P

Steady

State

TA = 25°C

TA = 70°C 9.8

TA = 25°C

TA = 25°C

TA = 70°C 6.2

TA = 25°C

tp = 10 ms

P

P

I

E

DSS

GS

I

D

D

I

D

DM

S

AS

T

G

S

MARKING DIAGRAM &

PIN ASSIGNMENT

D

1

SOIC-8 FLAT LEAD

CASE 488AA

STYLE 1

4701N = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb-Free Package

(Note: Microdot may be in either location)

S
S
S
G

4701N

AYWWG

G

D

ORDERING INFORMATION

Device Package Shipping

NTMFS4701NT1G SOIC-8 FL

(Pb-Free)

NTMFS4701NT3G 5000/Tape & ReelSOIC-8 FL

(Pb-Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

1500/Tape & Reel

†

D

D

© Semiconductor Components Industries, LLC, 2007

July, 2007 - Rev. 3

1 Publication Order Number:

NTMFS4701N/D

THERMAL RESISTANCE RATINGS

Rating Symbol Value Unit

Junction-to-Case - Steady State

Junction-to-Ambient - Steady State (Note 2)

Junction-to-Ambient - t v10 s (Note 1)

Junction-to-Ambient - Steady State (Note 1)

NTMFS4701N

R

q

JC

R

q

JA

R

q

JA

R

q

JA

4.0

140

21

55

°C/W

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

J

Characteristic Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain-to-Source Breakdown Voltage V

Drain-to-Source Breakdown Voltage

Temperature Coefficient

V

(BR)DSS/TJ

Zero Gate Voltage Drain Current I

Gate-to-Source Leakage Current I

(BR)DSS

DSS

GSS

VGS = 0 V, ID = 250 mA

VGS = 0 V, VDS = 24 V

VDS = 0 V, VGS = $20 V $100 nA

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage V

Negative Threshold Temperature Coefficient V

Drain-to-Source On Resistance R

GS(TH)

GS(TH)/TJ

DS(on)

VGS = VDS, ID = 250 mA

VGS = 4.5 V, ID = 17 A

VGS = 10 V, ID = 20 A

Forward Transconductance g

FS

VDS = 15 V, ID = 20 A 70 S

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate-to-Source Charge Q

Gate-to-Drain Charge Q

Gate Resistance R

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G

V

= 0 V, f = 1.0 MHz, V

GS

VGS = 4.5 V, VDS = 15 V, ID = 20 A

SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 4)

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

d(ON)

r

d(OFF)

f

VGS = 10 V, VDD = 15 V,

ID = 1.0 A, RG = 6.0 W

DRAIN-SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V

Reverse Recovery Time t

Charge Time t

Discharge Time t

Reverse Recovery Charge Q

RR

SD

a

b

RR

VGS = 0 V, IS = 6.0 A

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 6.0 A

3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

TJ = 25°C

TJ = 125°C

= 24 V

DS

TJ = 25°C

TJ = 125°C

30 V

7.2 mV/°C

1.0 mA

50

1.0 3.0 V

5.0 mV/°C

8.0 11 mW

6.0 8.0

1280

500

120

11 15

1.1

2.0

6.0

1.4

9.0

4.0

29

19

0.75 1.0

0.55

34

16

18

27 nC

pF

nC

W

ns

V

ns

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2

NTMFS4701N

TYPICAL PERFORMANCE CURVES

42

36

30

24

18

12

DRAIN CURRENT (AMPS)

D,

I

6

0

0

VGS = 10 V

6 V
4 V

3.4 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. On-Region Characteristics

0.01

0.008

0.006

2

TJ = 125°C

31

TJ = 25°C

TJ = 25°C

3 V

2.6 V

2.2 V

4

42

VDS ≥ 10 V

36

30

24

18

12

DRAIN CURRENT (AMPS)

D,

I

6

5

0

0

TJ = 25°C

TJ = 125°C

TJ = -55°C

1

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

23

4

5

Figure 2. Transfer Characteristics

0.01
TJ = 25°C

VGS = 4.5 V

0.008

VGS = 10 V

0.006

0.004
TJ = -55°C

DRAIN-TO-SOURCE RESISTANCE (W)

0.002

042

DS(on),

R

12 24

620

ID, DRAIN CURRENT (AMPS)

VGS = 10 V

30 36

Figure 3. On-Resistance vs. Drain Current and

Temperature

2

ID = 20 A
VGS = 10 V

1.5

1

DRAIN-TO-SOURCE

0.5

DS(on),

R

RESISTANCE (NORMALIZED)

0

-50 0-25 25

TJ, JUNCTION TEMPERATURE (°C)

50 150

75

125100 0

0.004

DRAIN-TO-SOURCE RESISTANCE (W)

0.002

DS(on),

R

12 24

620042

ID, DRAIN CURRENT (AMPS)

Figure 4. On-Resistance vs. Drain Current and

Gate Voltage

100000

10000

, LEAKAGE (nA)

1000

DSS

I

100

VGS = 0 V

TJ = 150°C

TJ = 125°C

5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

10 20

15

30 36

25

30

Figure 5. On-Resistance Variation with

Temperature

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Figure 6. Drain-to-Source Leakage Current

vs. Voltage

3

NTMFS4701N

TYPICAL PERFORMANCE CURVES

2500

2000

1500

VDS = 0 V VGS = 0 V

C

iss

TJ = 25°C

C

iss

1000

C

500

rss

C

oss

C

rss

C, CAPACITANCE (pF)

0

10 0 5 105

V

V

DS

GS

15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

100

VDD = 15 V
ID = 1 A
VGS = 4.5 V

t

d(off)

t

f

t

10

t, TIME (ns)

d(on)

t

r

10

8

6

QT

4

Q

GS

Q

GD

2

, GATE-TO-SOURCE VOLTAGE (V)

GS

V

0

0

14 16 20

121024 68

QG, TOTAL GATE CHARGE (nC)

Figure 8. Gate-To-Source and

Drain-To-Source Voltage vs. Total Charge

10

VGS = 0 V
TJ = 25°C

8

6

4

V

GS

ID = 20 A
TJ = 25°C

18

22

1

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

10

1

VGS = 20 V
SINGLE PULSE
TC = 25°C

0.1

, DRAIN CURRENT (AMPS)

D

I

0.01

0.1

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

dc

100

2

, SOURCE CURRENT (AMPS)

S

I

0

0.2

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

280

240

200

160

120

80

AVALANCHE ENERGY (mJ)

40

0

EAS, SINGLE PULSE DRAIN-TO-SOURCE

50

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.40

0.80.6

1

ID = 7.5 A

10025

12575

150

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4

NTMFS4701N

PACKAGE DIMENSIONS

DFN6 5x6, 1.27P (SO8 FL)

CASE 488AA-01

ISSUE C

0.10 C

0.10 C

0.05 c

D

2

D1

1234

TOP VIEW

SIDE VIEW

b

8X

A0.10 BC

L

14

E2

6

G

D2

BOTTOM VIEW

56

5

2 X

e/2

0.20 C

A

E1

E

2

A

DETAIL A

K

M

L1

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE

B

2 X

0.20 C

4 X

q

c

3 X

e

A1

C

SEATING

PLANE

DETAIL A

BURRS.

DIM MIN NOM

A1 0.00 ---

D1 4.50 4.90
D2 3.50 ---

E1 5.50 5.80
E2 3.45 ---

L1 0.05 0.17

MILLIMETERS

A 0.90 1.00

b 0.33 0.41
c 0.23 0.28
D 5.15 BSC

E 6.15 BSC

e 1.27 BSC
G 0.51 0.61
K 0.51 ---
L 0.51 0.61

M 3.00 3.40

q 0 ---

_

MAX

1.10

0.05

0.51

0.33

5.10

4.22

6.10

4.30

0.71

---

0.71

0.20

3.80
12

_

SOLDERING FOOTPRINT*

3X 4X

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

1.330

3.200

0.965

2X

0.495

1.270

4.560

2X

1.530

0.750

2X

0.905

0.475

4X

1.000

4.530

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NTMFS4701N/D

5