Datasheet ntmd4n03r2 Datasheet

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Page 1

NTMD4N03R2

Power MOSFET

4 Amps, 30 Volts N−Channel SO−8 Dual

Features

• Designed for use in low voltage, high speed switching applications

• Ultra Low On−Resistance Provides

Higher Efficiency and Extends Battery Life

− R

= 0.048 W, VGS = 10 V (Typ)

DS(on)

= 0.065 W, VGS = 4.5 V (Typ)

DS(on)

• Miniature SO−8 Surface Mount Package − Saves Board Space

• Diode is Characterized for Use in Bridge Circuits

• Diode Exhibits High Speed, with Soft Recovery

• Pb−Free Package is Available

Applications

• DC−DC Converters

• Computers

• Printers

• Cellular and Cordless Phones

• Disk Drives and Tape Drives

MAXIMUM RATINGS (T

Rating

Drain−to−Source Voltage V

Gate−to−Source Voltage − Continuous V

Drain Current

− Continuous @ T

− Single Pulse (tp ≤ 10 ms)

Total Power Dissipation

@ TA = 25°C (Note 1)

Operating and Storage

Temperature Range

Single Pulse Drain−to−Source

Avalanche Energy − Starting T (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 4.45 Apk, L = 8 mH,

= 25 W)

Thermal Resistance

− Junction−to−Ambient (Note 1)

Maximum Lead Temperature for

Soldering Purposes for 10 seconds

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s

= 25°C unless otherwise noted)

= 25°C

Symbol Value Unit

DSS

TJ, T

stg

30 V

"20 V

4.0 12

2.0 W

−55 to +150

80 mJ

62.5 °C/W

260 °C

Adc Apk

°C

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DSS

30 V

48 mW @ V

Typ ID Max

DS(ON)

= 10 V

N−Channel

4.0 A

MARKING DIAGRAM*

SOIC−8

SUFFIX NB

CASE 751

STYLE 11

E4N03 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

AND PIN ASSIGNMENT

D1 D1 D2 D2

E4N03

AYWW G

S1 G1 S2 G2

ORDERING INFORMATION

Device Package Shipping

NTMD4N03R2 SOIC−8 2500/Tape & Reel

NTMD4N03R2G SOIC−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D

2500/Tape & Reel

†

February, 2006 − Rev. 2

1 Publication Order Number:

NTMD4N03R2/D

Page 2

NTMD4N03R2

ELECTRICAL CHARACTERISTICS (T

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

= 0 Vdc, ID = 250 mA)

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

= 30 Vdc, VGS = 0 Vdc, TJ = 25°C)

(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate−Body Leakage Current

= ±20 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS (Note 2)

Gate Threshold Voltage

= VGS, ID = 250 mAdc)

Temperature Coefficient (Negative)

Static Drain−to−Source On−State Resistance

= 10 Vdc, ID = 4 Adc)

= 4.5 Vdc, ID = 2 Adc)

Forward Transconductance

= 3 Vdc, ID = 2 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

= 25°C unless otherwise noted)

(VDS = 20 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Symbol Min Ty p Max Unit

(BR)DSS

DSS

GSS

GS(th)

DS(on)

iss

oss

rss

−

1.0 10

− − 100

1.0

−

1.9

4.2

0.048

0.065

3.0

−

0.060

0.080

− 6.0 −

− 285 400 pF

− 95 135

− 35 70

Vdc

mV/°C

mAdc

nAdc

Vdc

mV/°C

Mhos

SWITCHING CHARACTERISTICS (Notes 2 & 3)

Turn−On Delay Time

Rise Time

Turn−Off Delay Time t

(VDD = 20 Vdc, ID = 2 A,

= 10 V,

= 2 W)

Fall Time t

Gate Charge

(VDS = 10 Vdc,

= 10 Vdc,

= 3.5 A)

BODY−DRAIN DIODE RATINGS (Note 2)

Diode Forward On−Voltage

(IS = 2 Adc, VGS = 0 V)

= 2 Adc, VGS = 0 V, TJ = 150°C)

Reverse Recovery Time

(IS = 2 A, VGS = 0 V,

/dt = 100 A/ms)

Reverse Recovery Stored Charge

= 2 A, dIS/dt = 100 A/ms, VGS = 0 V)

2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperature.

d(on)

d(off)

− 7.0 15

− 14 30

− 16 30

− 10 20

− 8.0 16

− 1.1 −

− 1.9 −

−

0.82

0.63

1.0

− 14 −

− 10 −

− 4.0 −

− 0.008 −

Vdc

−

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NTMD4N03R2

TYPICAL MOSFET ELECTRICAL CHARACTERISTICS

5 V

, DRAIN CURRENT (AMPS)

0 1.0

10 V

8 V

6 V

0.2

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

0.4 0.8

4 V

4.5 V

TJ = 25°C

0.6

VGS = 3 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.10

0.075

0.05

VGS = 10

T = 125°C

T = 25°C

T = −55°C

3.6 V

VDS ≥ 10 V

, DRAIN CURRENT (AMPS)

04215

0.10

TJ = 25°C

0.08

0.06

0.04

TJ = 25°C

TJ = 125°C

TJ = −55°C

, GATE−TO−SOURCE VOLTAGE (VOLTS)

VGS = 4.5 V

VGS = 10 V

0.025

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

Figure 3. On−Resistance versus Drain Current

1.5

1.375

1.25

1.125

0.875

0.75

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

DS(on)

ID = 2 A V

= 10 V

−50 0−25 5025

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

ID, DRAIN CURRENT (AMPS)

and Temperature

10075 125

Temperature

0.02

, DRAIN−TO−SOURCE RESISTANCE (W)

DS(on)

765

287

ID, DRAIN CURRENT (AMPS)

654

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

10,000

VGS = 0 V

1000

TJ = 150°C

, LEAKAGE (nA)

150

DSS

100

0152010 305

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

TJ = 125°C

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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Page 4

NTMD4N03R2

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, V known as the plateau voltage, V

remains virtually constant at a level

. Therefore, rise and fall

SGP

times may be approximated by the following:

= Q2 x RG/(VGG − V

tf = Q2 x RG/V

GSP

)

where

= the gate drive voltage, which varies from zero to V

RG = the gate drive resistance

and Q

and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when calculating t on−state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

800

iss

600

rss

400

200

C, CAPACITANCE (pF)

VDS = 0 V

10 15 2010550 25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE

VGS = 0 V

VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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TJ = 25°C

iss

oss

rss

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NTMD4N03R2

, GATE−TO−SOURCE VOLTAGE (VOLTS)

04 8

123 567

, TOTAL GATE CHARGE (nC)

ID = 4 A T

= 25°C

910

Figure 8. Gate−to−Source and

Drain−to−Source Voltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, t to the storage of minority carrier charge, Q

, as shown in

, due

the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t

and low QRR specifications to

minimize these losses.

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by

VGS = 0 V T

= 25°C

100

t, TIME (ns)

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VDD = 15 V I

= 4 A

= 10 V

1 100

, GATE RESISTANCE (W)

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

high di/dts. The diode’s negative di/dt during t controlled by the device clearing the stored charge. However, the positive di/dt during t

is an uncontrollable

diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of t

serves as a good indicator of recovery

b/ta

abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter t

), have less stored charge and a softer

reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

d(off)

d(on)

is directly

, SOURCE CURRENT (AMPS)

0.5 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

0.7 0.8 0.9

Figure 10. Diode Forward Voltage versus Current

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NTMD4N03R2

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T

) of 25°C.

Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.”

Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (I

) nor rated voltage (V

transition time (t

100

VGS = 20 V SINGLE PULSE TC = 25°C

0.1

, DRAIN CURRENT (AMPS)

0.01

0.1

, tf) does not exceed 10 ms. In addition the

DS(on)

THERMAL LIMIT PACKAGE LIMIT

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

1.0

Safe Operating Area

) is exceeded, and that the

DSS

LIMIT

1.0 ms

10 ms

100

total power averaged over a complete switching cycle must not exceed (T

J(MAX)

− TC)/(R

A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature.

ID = 4.45 A

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN−TO−SOURCE

25 125 1501007550

, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

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Page 7

NTMD4N03R2

TYPICAL ELECTRICAL CHARACTERISTICS

1.0 D = 0.5

0.2

0.1

0.05

0.02

0.01

THERMAL RESISTANCE

0.01

CHIP JUNCTION

Rthja(t), EFFECTIVE TRANSIENT

SINGLE PULSE

0.001

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 t, TIME (s)

Figure 13. Thermal Response

0.0106 W

0.0253 F

0.0431 W

0.1406 F

0.1643 W

0.5064 F

0.3507 W

2.9468 F

0.4302 W

177.14 F

1.0E+02 1.0E+03

AMBIENT

di/dt

TIME

0.25 I

Figure 14. Diode Reverse Recovery Waveform

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Page 8

−Y−

−Z−

NTMD4N03R2

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AG

−X−

0.25 (0.010) Z

0.25 (0.010)

SEATING PLANE

SXS

0.10 (0.004)

X 45

SOLDERING FOOTPRINT*

1.52

0.060

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMD4N03R2/D