Datasheet ntmd4840n Datasheet

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NTMD4840N

Power MOSFET

30 V, 7.5 A, Dual N−Channel, SOIC−8

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• Dual SOIC−8 Surface Mount Package Saves Board Space

• This is a Pb−Free Device

Applications

• Disk Drives

• DC−DC Converters

• Printers

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain Current R

Power Dissipation

(Note 1)

Continuous Drain Current R

Power Dissipation

(Note 2)

Continuous Drain Current R (Note 1)

Power Dissipation

t < 10 s (Note 1)

Pulsed Drain Current T

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche Energy T

= 7.5 Apk, L = 1.0 mH, RG = 25 W

Lead Temperature for Soldering Purposes (1/8″ from case for 10 s)

THERMAL RESISTANCE RATINGS

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t≤10 s (Note 1)

Junction−to−FOOT (Drain)

Junction−to−Ambient – Steady State (Note 2)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

Rating

= 25°C

(Note 1)

(Note 2)

Steady

State

t < 10 s

= 25°C, VDD = 30 V, VGS = 10 V,

= 70°C 4.4

= 25°C P

= 25°C

= 70°C 3.5

= 25°C P

= 25°C

= 70°C 6.0

= 25°C P

= 25°C,

= 10 ms

Rating Symbol Max Unit

Symbol Value Unit

DSS

STG

30 V

±20 V

5.5

1.14 W

4.5

0.68 W

7.5

1.95 W

30 A

−55 to +150

2.0 A

°C

EAS 28 mJ

260 °C

110

183.5

°C/W

http://onsemi.com

(BR)DSS

30 V

24 mW @ 10 V

DS(on)

Max

7.5 A

Max

36 mW @ 4.5 V

N−Channel

MARKING DIAGRAM

& PIN ASSIGNMENT

D1 D1 D2 D2

SOIC−8

CASE 751

STYLE 11

4840N

AYWW

S1 G1 S2 G2

4840N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

NTMD4840NR2G SOIC−8

2500/Tape & Reel

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

†

September, 2009 − Rev. 1

1 Publication Order Number:

NTMD4840N/D

Page 2

NTMD4840N

ELECTRICAL CHARACTERISTICS (T

Characteristic

= 25°C unless otherwise noted)jk

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Temperature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

(BR)DSS

(BR)DSS/TJ

DSS

GSS

= 0 V, I

= 0 V,

= 24 V

= 0 V, V

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coefficient

Drain−to−Source On Resistance R

Forward Transconductance g

GS(TH)

GS(TH)/TJ

DS(on)

= VDS, I

= 10 V I

= 4.5 V I

= 1.5 V, I

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

ISS

OSS

RSS

G(TOT)

G(TH)

G(TOT)

= 0 V, f = 1.0 MHz, V

= 4.5 V, V

= 10 V, V

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

d(ON)

d(OFF)

= 10 V, V

= 1.0 A, R

DRAIN−TO−SOURCE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time T

Discharge Time T

Reverse Recovery Time Q

VGS = 0 V I

= 2.0 A

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 2.0 A

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance L

Gate Inductance L

Gate Resistance R

TA = 25°C

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

= 250 mA

30 V

TJ = 25°C

TJ = 100°C

= ±20 V ±100 nA

= 250 mA

1.5 3.0 V

1.0

6.0

= 6.9 A

= 5.0 A

= 6.9 A 15 S

16 24

26 36

520

= 15 V

140

4.8

= 15 V, I

= 6.9 A

1.1

2.1

1.9

= 15 V, I

= 6.9 A 9.5 nC

7.6

= 15 V,

= 3.0 W

5.0

3.0

TJ = 25°C

TJ = 125°C

0.76 1.0

0.58

12.5

7.3

5.2

6.0

0.66 nH

0.20 nH

1.50 nH

2.0 3.0

mV/°C

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Page 3

NTMD4840N

TYPICAL PERFORMANCE CURVES

10V

4.5 V

4.2 V

4 V

3.8 V

TJ = 25°C

3.4 V

3.2 V

DRAIN CURRENT (AMPS)

0 1.0 2.0 3.0

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

3.0 V

2.8 V

2.6 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.060

0.055

0.050

0.045

0.040

0.035

0.030

0.025

0.020

DRAIN−TO−SOURCE RESISTANCE (W)

0.015 357 9

DS(on),

46 810

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = 25°C I

= 6.9 A

VDS ≥ 10 V

DRAIN CURRENT (AMPS)

TJ = 125°C

TJ = 25°C

TJ = −55°C

5.04.0

1.5 2.5 3.5 4.5

234

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.030

0.028

TJ = 25°C

0.026 VGS = 4.5 V

0.024

0.022

0.020

0.018

0.016

DRAIN−TO−SOURCE RESISTANCE (W)

0.014

DS(on),

3.5 8 14

25 11

VGS = 10 V

6.5 9.5 12.5

DRAIN CURRENT (AMPS)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.65 ID = 7.5 A

1.55 V

= 10 V

1.45

1.35

1.25

1.15

1.05

DRAIN−TO−SOURCE

0.95

0.85

DS(on),

RESISTANCE (NORMALIZED)

0.75

0.65

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

100000

10000

, LEAKAGE (nA)

1000

DSS

100

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Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

VGS = 0 V

TJ = 150°C

TJ = 125°C

51015202530

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

Page 4

NTMD4840N

TYPICAL PERFORMANCE CURVES

700

600

500

400

300

200

C, CAPACITANCE (pF)

100

rss

0510

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source and

100

VDD = 15 V I

= 1 A

= 10 V

t, TIME (ns)

d(on)

TJ = 25°C

iss

oss

15 25

VGS = 0 V

d(off)

, GATE-TO-SOURCE VOLTAGE (VOLTS)

2610

15 937

QG, TOTAL GATE CHARGE (nC)

Drain−To −Source Voltage vs. Total Charge

2.5

VGS = 0 V T

= 25°C

1.5

VGS = 10 V

= 6.9 A

= 25°C

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

VGS = 20 V SINGLE PULSE

0.1

, DRAIN CURRENT (AMPS)

0.01

0.01 10 100

TC = 25°C

DS(on)

THERMAL LIMIT PACKAGE LIMIT

0.1

LIMIT

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

0.5

, SOURCE CURRENT (AMPS)

0.4 0.5 0.6 0.7

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

AVALANCHE ENERGY (mJ)

25 50 75 100

EAS, SINGLE PULSE DRAIN−TO−SOURCE

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.8

ID = 7.5 A

150125

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Page 5

−Y−

−Z−

NTMD4840N

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

X 45

−X− A

0.25 (0.010)

SEATING PLANE

0.10 (0.004)

0.25 (0.010) Z

SXS

SOLDERING FOOTPRINT*

1.52

0.060

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTMD4840N/D