Datasheet ntmd4820n Datasheet

NTMD4820N

Power MOSFET

30 V, 8 A, Dual N−Channel, SOIC−8

Features

• Low R

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• Dual SOIC−8 Surface Mount Package Saves Board Space

Applications

• Disk Drives

• DC−DC Converters

• Printers

MAXIMUM RATINGS (T

Drain−to−Source Voltage V

Gate−to−Source Voltage V

Continuous Drain
Current R

Power Dissipation

(Note 1)

R

q

JA

Continuous Drain
Current R

Power Dissipation

(Note 2)

R

q

JA

Continuous Drain
Current R
(Note 1)

Power Dissipation

t < 10 s (Note 1)

R

q

JA

Pulsed Drain Current T

Operating Junction and Storage Temperature TJ, T

Source Current (Body Diode) I

Single Pulse Drain−to−Source Avalanche
Energy T

= 11 Apk, L = 1.0 mH, RG = 25 W

I

L

Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)

THERMAL RESISTANCE RATINGS

Junction−to−Ambient – Steady State (Note 1)

Junction−to−Ambient – t ≤ 10 s (Note 1)

Junction−to−FOOT (Drain)

Junction−to−Ambient – Steady State (Note 2)

1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

to Minimize Conduction Losses

DS(on)

= 25°C unless otherwise stated)

J

Rating

T

= 25°C,

A

= 10 ms

t

p

T

T

A

T

T

T

A

T

T

T

A

A

A

= 25°C P

A

A

= 25°C P

A

A

= 25°C P

(Note 1)

q

JA

(Note 2)

q

JA

Steady

State

t < 10 s

q

JA

= 25C, VDD = 30 V, VGS = 10 V,

J

Rating Symbol Max Unit

Symbol Value Unit

30 V

±20 V

6.4

= 25°C

DSS

GS

I

D

= 70°C 5.1

1.28 W

4.9

= 25°C

D

I

D

= 70°C 3.9

0.75 W

8.0

= 25°C

D

I

D

= 70°C 6.4

2.0 W

32 A

−55 to
+150

2.0 A

I

D

DM

STG

S

EAS 60.5 mJ

T

L

R

q

JA

R

q

JA

R

q

JF

R

q

JA

260 °C

97.5

62

40

167.5

A

A

A

°C

°C/W

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R

V

(BR)DSS

30 V

20 mW @ 10 V

DS(on)

Max

I

D

Max

8 A

27 mW @ 4.5 V

N−Channel

D

G

S

MARKING DIAGRAM

& PIN ASSIGNMENT

D1 D1 D2 D2

8

8

1

SOIC−8

CASE 751

STYLE 11

4820N

AYWW

G

1

S1 G1 S2 G2

4820N = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

NTMD4820NR2G SOIC−8

2500/Tape & Reel

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

†

© Semiconductor Components Industries, LLC, 2009

August, 2009 − Rev. 2

1 Publication Order Number:

NTMD4820N/D

NTMD4820N

ELECTRICAL CHARACTERISTICS (T

Characteristic

= 25°C unless otherwise noted)jk

J

Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

Drain−to−Source Breakdown Voltage Tem­perature Coefficient

Zero Gate Voltage Drain Current I

Gate−to−Source Leakage Current I

V

(BR)DSS

V

(BR)DSS/TJ

DSS

GSS

V

= 0 V, I

GS

V

= 0 V,

GS

V

= 24 V

DS

V

= 0 V, V

DS

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage

Negative Threshold Temperature Coeffi­cient

Drain−to−Source On Resistance R

Forward Transconductance g

V

GS(TH)

V

GS(TH)/TJ

DS(on)

FS

V

= VDS, I

GS

V

= 10 V I

GS

V

= 4.5 V I

GS

V

= 1.5 V, I

DS

CHARGES, CAPACITANCES AND GATE RESISTANCE

Input Capacitance

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Threshold Gate Charge Q

Gate−to−Source Charge Q

Gate−to−Drain Charge Q

Total Gate Charge Q

C

ISS

OSS

RSS

G(TOT)

G(TH)

GS

GD

G(TOT)

V

= 0 V, f = 1.0 MHz, V

GS

V

= 4.5 V, V

GS

V

= 10 V, V

GS

DS

DS

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

Fall Time t

t

d(ON)

r

d(OFF)

f

V

GS

I

D

= 10 V, V

= 1.0 A, R

DRAIN−TO−SOURCE CHARACTERISTICS

Forward Diode Voltage

Reverse Recovery Time t

Charge Time T

Discharge Time T

Reverse Recovery Time Q

V

SD

RR

a

b

RR

VGS = 0 V
I

= 2.0 A

D

VGS = 0 V, dIS/dt = 100 A/ms,

IS = 2.0 A

PACKAGE PARASITIC VALUES

Source Inductance

Drain Inductance L

Gate Inductance L

Gate Resistance R

L

S

D

G

G

TA = 25°C

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

4. Switching characteristics are independent of operating junction temperatures.

= 250 mA

D

30 V

26

TJ = 25°C

TJ = 100°C

= ±20 V ±100 nA

GS

= 250 mA

D

1.5 3.0 V

1.0

10

5.0

= 7.5 A

D

= 6.5 A

D

= 7.5 A 21 S

D

15 20

20 27

940

DS

= 15 V

225

125

7.7

= 15 V, I

= 7.5 A

D

1.1

3.3

3.2

= 15 V, I

= 7.5 A 15.2 nC

D

9.4

= 15 V,

DD

= 6.0 W

G

4.0

21

6.5

TJ = 25°C

TJ = 125°C

0.75 1.0

0.59

17.8

8.3

9.5

8.0

0.66 nH

0.20 nH

1.50 nH

1.5 3.0

mV/°C

mA

mV/°C

mW

pF

nC

ns

V

ns

nC

W

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2

NTMD4820N

TYPICAL PERFORMANCE CURVES

15

12.5

5 V

6 V

10V

TJ = 25°C

3.6 V

4.5 V

10

7.5

5

DRAIN CURRENT (AMPS)

2.5

D,

I

0

0 0.5 1.0 1.5 2.0 2.5 3.0

4.2 V

4 V

3.8 V

2.8 V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

3.4 V

3.2 V

3.0 V

3.5 4.0

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.095

0.085

0.075

0.065

0.055

0.045

0.035

0.025

0.015

DRAIN−TO−SOURCE RESISTANCE (W)

0.005
34 6 8 10

DS(on),

R

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

579

TJ = 25°C
I

= 7.5 A

D

15

VDS ≥ 10 V

10

5

DRAIN CURRENT (AMPS)

D,

I

TJ = 125°C

TJ = 25°C

TJ = −55°C

0

1.5 2.5 3.5 4.5

1234

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.030
TJ = 25°C

0.025

0.020

VGS = 4.5 V

0.015

0.010

VGS = 10 V

0.005

DRAIN−TO−SOURCE RESISTANCE (W)

0

2 6 10 14

DS(on),

R

4812

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

1.6
ID = 7.5 A

1.5
V

= 10 V

GS

1.4

1.3

1.2

1.1

1.0

DRAIN−TO−SOURCE

0.9

0.8

DS(on),

R

RESISTANCE (NORMALIZED)

0.7

0.6

−50 −25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

100000

10000

, LEAKAGE (nA)

1000

DSS

I

100

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3

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

VGS = 0 V

TJ = 150°C

TJ = 100°C

3 6 9 12151821242730

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

NTMD4820N

TYPICAL PERFORMANCE CURVES

1300
1200

1100

1000

C

iss

900
800
700
600
500
400

C, CAPACITANCE (pF)

300

C

oss

200

C

100

rss

0

0510

DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation Figure 8. Gate−To−Source and

1000

VDD = 10 V
I

= 1 A

D

= 15 V

V

GS

100

t, TIME (ns)

10

TJ = 25°C

VGS = 0 V

15 25

20

t

d(off)

t

f

t

r

t

d(on)

10

9

V

8

DS

7

6

5

Q

GS

4

3

2

, GATE-TO-SOURCE VOLTAGE (VOLTS)

1

GS

V

0

30

2 6 10 14

04

Drain−To −Source Voltage vs. Total Charge

3

VGS = 0 V
T

= 25°C

J

2

1

QT

Q

GD

8

12

QG, TOTAL GATE CHARGE (nC)

V

GS

ID = 7.5 A
T

= 25°C

J

16

20

16

12

8

4

0

DS

V

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation vs. Gate Resistance

100

10

1

VGS = 20 V
SINGLE PULSE
TC = 25°C

0.1

, DRAIN CURRENT (AMPS)

D

I

0.01

0.1 10 100

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

10 ms

100 ms

1 ms

10 ms

dc

, SOURCE CURRENT (AMPS)

S

I

0

0.3 0.5 0.6 0.7

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage vs. Current

75

50

25

AVALANCHE ENERGY (mJ)

0

25 50 75 100

EAS, SINGLE PULSE DRAIN−TO−SOURCE

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature

0.80.4

ID = 11 A

150125

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4

−Y−

−Z−

NTMD4820N

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

M

Y

N

ISSUE AJ

X 45

_

M

K

J

1.52

0.060

−X−
A

58

B

1

S

0.25 (0.010)

4

M

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

SOLDERING FOOTPRINT*

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMD4820N/D